From: Andy Chiu <andybnac@gmail.com>
To: linux-riscv@lists.infradead.org, alexghiti@rivosinc.com,
palmer@dabbelt.com
Cc: Andy Chiu <andybnac@gmail.com>,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
Alexandre Ghiti <alex@ghiti.fr>,
bjorn@rivosinc.com, puranjay12@gmail.com,
paul.walmsley@sifive.com, greentime.hu@sifive.com,
nick.hu@sifive.com, nylon.chen@sifive.com, eric.lin@sifive.com,
vicent.chen@sifive.com, zong.li@sifive.com,
yongxuan.wang@sifive.com, samuel.holland@sifive.com,
olivia.chu@sifive.com, c2232430@gmail.com
Subject: [PATCH v4 12/12] riscv: Documentation: add a description about dynamic ftrace
Date: Tue, 8 Apr 2025 02:08:36 +0800 [thread overview]
Message-ID: <20250407180838.42877-12-andybnac@gmail.com> (raw)
In-Reply-To: <20250407180838.42877-1-andybnac@gmail.com>
Add a section in cmodx to describe how dynamic ftrace works on riscv,
limitations, and assumptions.
Signed-off-by: Andy Chiu <andybnac@gmail.com>
---
Documentation/arch/riscv/cmodx.rst | 46 +++++++++++++++++++++++++-----
1 file changed, 39 insertions(+), 7 deletions(-)
diff --git a/Documentation/arch/riscv/cmodx.rst b/Documentation/arch/riscv/cmodx.rst
index 8c48bcff3df9..e009873b2d17 100644
--- a/Documentation/arch/riscv/cmodx.rst
+++ b/Documentation/arch/riscv/cmodx.rst
@@ -10,13 +10,45 @@ modified by the program itself. Instruction storage and the instruction cache
program must enforce its own synchronization with the unprivileged fence.i
instruction.
-However, the default Linux ABI prohibits the use of fence.i in userspace
-applications. At any point the scheduler may migrate a task onto a new hart. If
-migration occurs after the userspace synchronized the icache and instruction
-storage with fence.i, the icache on the new hart will no longer be clean. This
-is due to the behavior of fence.i only affecting the hart that it is called on.
-Thus, the hart that the task has been migrated to may not have synchronized
-instruction storage and icache.
+CMODX in the Kernel Space
+---------------------
+
+Dynamic ftrace
+---------------------
+
+Essentially, dynamic ftrace directs the control flow by inserting a function
+call at each patchable function entry, and patches it dynamically at runtime to
+enable or disable the redirection. In the case of RISC-V, 2 instructions,
+AUIPC + JALR, are required to compose a function call. However, it is impossible
+to patch 2 instructions and expect that a concurrent read-side executes them
+without a race condition. This series makes atmoic code patching possible in
+RISC-V ftrace. Kernel preemption makes things even worse as it allows the old
+state to persist across the patching process with stop_machine().
+
+In order to get rid of stop_machine() and run dynamic ftrace with full kernel
+preemption, we partially initialize each patchable function entry at boot-time,
+setting the first instruction to AUIPC, and the second to NOP. Now, atmoic
+patching is possible because the kernel only has to update one instruction.
+According to Ziccif, as long as an instruction is naturally aligned, the ISA
+guarantee an atomic update.
+
+By fixing down the first instruction, AUIPC, the range of the ftrace trampoline
+is limited to +-2K from the predetermined target, ftrace_caller, due to the lack
+of immediate encoding space in RISC-V. To address the issue, we introduce
+CALL_OPS, where an 8B naturally align metadata is added in front of each
+pacthable function. The metadata is resolved at the first trampoline, then the
+execution can be derect to another custom trampoline.
+
+CMODX in the User Space
+---------------------
+
+Though fence.i is an unprivileged instruction, the default Linux ABI prohibits
+the use of fence.i in userspace applications. At any point the scheduler may
+migrate a task onto a new hart. If migration occurs after the userspace
+synchronized the icache and instruction storage with fence.i, the icache on the
+new hart will no longer be clean. This is due to the behavior of fence.i only
+affecting the hart that it is called on. Thus, the hart that the task has been
+migrated to may not have synchronized instruction storage and icache.
There are two ways to solve this problem: use the riscv_flush_icache() syscall,
or use the ``PR_RISCV_SET_ICACHE_FLUSH_CTX`` prctl() and emit fence.i in
--
2.39.3 (Apple Git-145)
next prev parent reply other threads:[~2025-04-07 18:09 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-07 18:08 [PATCH v4 01/12] riscv: ftrace: support fastcc in Clang for WITH_ARGS Andy Chiu
2025-04-07 18:08 ` [PATCH v4 02/12] riscv: ftrace factor out code defined by !WITH_ARG Andy Chiu
2025-04-07 18:08 ` [PATCH v4 03/12] riscv: ftrace: align patchable functions to 4 Byte boundary Andy Chiu
2025-04-07 18:08 ` [PATCH v4 04/12] kernel: ftrace: export ftrace_sync_ipi Andy Chiu
2025-04-08 22:31 ` kernel test robot
2025-04-23 8:13 ` Alexandre Ghiti
2025-04-07 18:08 ` [PATCH v4 05/12] riscv: ftrace: prepare ftrace for atomic code patching Andy Chiu
2025-04-11 13:15 ` Robbin Ehn
2025-04-23 8:22 ` Alexandre Ghiti
2025-05-05 14:06 ` Alexandre Ghiti
2025-05-07 14:18 ` Andy Chiu
2025-05-07 14:35 ` Alexandre Ghiti
2025-04-07 18:08 ` [PATCH v4 06/12] riscv: ftrace: do not use stop_machine to update code Andy Chiu
2025-04-07 18:08 ` [PATCH v4 07/12] riscv: vector: Support calling schedule() for preemptible Vector Andy Chiu
2025-04-07 18:08 ` [PATCH v4 08/12] riscv: add a data fence for CMODX in the kernel mode Andy Chiu
2025-04-07 18:08 ` [PATCH v4 09/12] riscv: ftrace: support PREEMPT Andy Chiu
2025-04-07 18:08 ` [PATCH v4 10/12] riscv: Implement HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS Andy Chiu
2026-02-21 12:15 ` Conor Dooley
2026-02-23 15:18 ` Puranjay Mohan
2026-02-23 15:27 ` Conor Dooley
2026-02-23 15:41 ` Puranjay Mohan
2026-02-23 16:29 ` Conor Dooley
2026-02-23 17:36 ` Puranjay Mohan
2026-02-23 17:41 ` Conor Dooley
2025-04-07 18:08 ` [PATCH v4 11/12] riscv: ftrace: support direct call using call_ops Andy Chiu
2025-04-07 18:08 ` Andy Chiu [this message]
2025-04-11 12:02 ` [PATCH v4 12/12] riscv: Documentation: add a description about dynamic ftrace Robbin Ehn
2025-04-10 20:05 ` [PATCH v4 01/12] riscv: ftrace: support fastcc in Clang for WITH_ARGS Björn Töpel
2025-05-07 13:58 ` Andy Chiu
2025-06-02 22:12 ` patchwork-bot+linux-riscv
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20250407180838.42877-12-andybnac@gmail.com \
--to=andybnac@gmail.com \
--cc=alex@ghiti.fr \
--cc=alexghiti@rivosinc.com \
--cc=bjorn@rivosinc.com \
--cc=c2232430@gmail.com \
--cc=eric.lin@sifive.com \
--cc=greentime.hu@sifive.com \
--cc=linux-doc@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=nick.hu@sifive.com \
--cc=nylon.chen@sifive.com \
--cc=olivia.chu@sifive.com \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=puranjay12@gmail.com \
--cc=samuel.holland@sifive.com \
--cc=vicent.chen@sifive.com \
--cc=yongxuan.wang@sifive.com \
--cc=zong.li@sifive.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox