* [PATCH v3 3/3] drm/bridge:anx7625: Enable DSC feature
2025-04-14 10:05 [PATCH v3 1/3] drm/bridge:anx7625: Refactoring timing programming Xin Ji
2025-04-14 10:05 ` [PATCH v3 2/3] drm/mipi-dsi: Add compression supported flag in drm_mipi_dsi Xin Ji
@ 2025-04-14 10:05 ` Xin Ji
2025-04-15 14:26 ` kernel test robot
1 sibling, 1 reply; 4+ messages in thread
From: Xin Ji @ 2025-04-14 10:05 UTC (permalink / raw)
To: Andrzej Hajda, Neil Armstrong, Robert Foss, Laurent Pinchart,
Jonas Karlman, Jernej Skrabec, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter
Cc: bliang, qwen, treapking, Xin Ji, dri-devel, linux-kernel
4K30(3840x2160 30Hz) timing pixel clock around 297M, for 24bits RGB
pixel data format, total transport bandwidth need 297M*24(at least
7.2Gbps) more than anx7625 mipi rx lane bandwidth(maximum 6Gbps,
4lanes, each lane 1.5Gbps). Without DSC function, anx7625 cannot
receive 4K30 video timing.
When display pixel clock exceed 250M, driver will enable DSC feature,
and the compression ratio is 3:1, eg: 4K30's pixel clock around 297M,
bandwidth 7.2G will be compressed to 7.2G/3 = 2.4G. Then anx7625
can receive 4K30 video timing and do decompress, then package video
data and send to sink device through DP link.
Anx7625 will check DSI host capability to make sure whether it support
compression feature, if not, anx7625 driver will limit maximum pixel
clock to 250M.
Note:
Anx7625 is bridge IC, sink monitor only receive normal DP signal from
anx7625, sink device didn't know DSC information between SOC and anx7625
v2:
1. Remove dsc_en flag
v3:
1. Split timing refactoring code to a individual patch.
2. Add drm_dsi_host compression_supported flag check. If DSI host not
supported compression, anx7625 bridge driver will limit maximum
pixel clock to 250M.
Signed-off-by: Xin Ji <xji@analogixsemi.com>
---
drivers/gpu/drm/bridge/analogix/anx7625.c | 191 ++++++++++++++++++++--
drivers/gpu/drm/bridge/analogix/anx7625.h | 26 +++
2 files changed, 203 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c b/drivers/gpu/drm/bridge/analogix/anx7625.c
index 8928971558d2..fe8ccd6bad96 100644
--- a/drivers/gpu/drm/bridge/analogix/anx7625.c
+++ b/drivers/gpu/drm/bridge/analogix/anx7625.c
@@ -9,6 +9,7 @@
#include <linux/interrupt.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
+#include <linux/math64.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/pm_runtime.h>
@@ -22,6 +23,7 @@
#include <drm/display/drm_dp_aux_bus.h>
#include <drm/display/drm_dp_helper.h>
+#include <drm/display/drm_dsc_helper.h>
#include <drm/display/drm_hdcp_helper.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_bridge.h>
@@ -476,9 +478,14 @@ static int anx7625_set_k_value(struct anx7625_data *ctx)
MIPI_DIGITAL_ADJ_1, 0x3D);
}
-static bool anx7625_dsc_check(struct anx7625_data *ctx)
+static bool anx7625_dsc_check(struct anx7625_data *ctx, int pixelclock)
{
- if (ctx->dt.pixelclock.min > DSC_PIXEL_CLOCK)
+ struct mipi_dsi_host *host = ctx->host;
+
+ if (!host)
+ return false;
+
+ if (host->compression_supported && pixelclock > DSC_PIXEL_CLOCK)
return true;
return false;
@@ -491,7 +498,7 @@ static inline int anx7625_h_timing_reg_write(struct anx7625_data *ctx,
{
int ret;
- if (dsc_check && anx7625_dsc_check(ctx))
+ if (dsc_check && anx7625_dsc_check(ctx, ctx->dt.pixelclock.min))
val = dsc_div(val);
ret = anx7625_reg_write(ctx, client, reg_addr, val);
@@ -551,6 +558,79 @@ static int anx7625_v_timing_write(struct anx7625_data *ctx,
return ret;
}
+static int anx7625_set_dsc_params(struct anx7625_data *ctx)
+{
+ int ret, i;
+ u16 htotal, vtotal;
+
+ /* Video Horizontal timing */
+ ret = anx7625_h_timing_write(ctx, ctx->i2c.tx_p2_client, false);
+
+ /* Video Vertical timing */
+ ret |= anx7625_v_timing_write(ctx, ctx->i2c.tx_p2_client);
+
+ /* Vtotal */
+ vtotal = ctx->dt.vactive.min + ctx->dt.vfront_porch.min +
+ ctx->dt.vback_porch.min + ctx->dt.vsync_len.min;
+ ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, TOTAL_LINES_L,
+ vtotal);
+ ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, TOTAL_LINES_H,
+ vtotal >> 8);
+ /* Htotal */
+ htotal = ctx->dt.hactive.min + ctx->dt.hfront_porch.min +
+ ctx->dt.hback_porch.min + ctx->dt.hsync_len.min;
+ ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, TOTAL_PIXEL_L_7E,
+ htotal);
+ ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, TOTAL_PIXEL_H_7E,
+ htotal >> 8);
+ /* Hactive */
+ ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
+ ACTIVE_PIXEL_L_7E, ctx->dt.hactive.min);
+ ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
+ ACTIVE_PIXEL_H_7E, ctx->dt.hactive.min >> 8);
+ /* HFP */
+ ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
+ HORIZON_FRONT_PORCH_L_7E,
+ ctx->dt.hfront_porch.min);
+ ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
+ HORIZON_FRONT_PORCH_H_7E,
+ ctx->dt.hfront_porch.min >> 8);
+ /* HWS */
+ ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
+ HORIZON_SYNC_WIDTH_L_7E,
+ ctx->dt.hsync_len.min);
+ ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
+ HORIZON_SYNC_WIDTH_H_7E,
+ ctx->dt.hsync_len.min >> 8);
+ /* HBP */
+ ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
+ HORIZON_BACK_PORCH_L_7E,
+ ctx->dt.hback_porch.min);
+ ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
+ HORIZON_BACK_PORCH_H_7E,
+ ctx->dt.hback_porch.min >> 8);
+
+ /* Config DSC decoder internal blank timing for decoder to start */
+ ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
+ H_BLANK_L,
+ dsc_div(htotal - ctx->dt.hactive.min));
+ ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
+ H_BLANK_H,
+ dsc_div(htotal - ctx->dt.hactive.min) >> 8);
+
+ /* Compress ratio RATIO bit[7:6] */
+ ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, R_I2C_1, 0x3F);
+ ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, R_I2C_1,
+ (5 - DSC_COMPRESS_RATIO) << 6);
+ /*PPS table*/
+ for (i = 0; i < PPS_SIZE; i += PPS_BLOCK_SIZE)
+ ret |= anx7625_reg_block_write(ctx, ctx->i2c.rx_p2_client,
+ R_PPS_REG_0 + i, PPS_BLOCK_SIZE,
+ &ctx->pps_table[i]);
+
+ return ret;
+}
+
static int anx7625_dsi_video_timing_config(struct anx7625_data *ctx)
{
struct device *dev = ctx->dev;
@@ -697,13 +777,20 @@ static int anx7625_api_dsi_config(struct anx7625_data *ctx)
static int anx7625_dsi_config(struct anx7625_data *ctx)
{
struct device *dev = ctx->dev;
- int ret;
+ int ret = 0;
DRM_DEV_DEBUG_DRIVER(dev, "config dsi.\n");
- /* DSC disable */
- ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
- R_DSC_CTRL_0, ~DSC_EN);
+ if (anx7625_dsc_check(ctx, ctx->dt.pixelclock.min)) {
+ ret = anx7625_set_dsc_params(ctx);
+ /* DSC enable */
+ ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
+ R_DSC_CTRL_0, DSC_EN);
+ } else {
+ /* DSC disable */
+ ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
+ R_DSC_CTRL_0, ~DSC_EN);
+ }
ret |= anx7625_api_dsi_config(ctx);
@@ -2121,6 +2208,8 @@ static int anx7625_setup_dsi_device(struct anx7625_data *ctx)
MIPI_DSI_MODE_VIDEO_HSE |
MIPI_DSI_HS_PKT_END_ALIGNED;
+ dsi->host = host;
+ dsi->dsc = &ctx->dsc;
ctx->dsi = dsi;
return 0;
@@ -2224,21 +2313,79 @@ anx7625_bridge_mode_valid(struct drm_bridge *bridge,
{
struct anx7625_data *ctx = bridge_to_anx7625(bridge);
struct device *dev = ctx->dev;
+ int maximum_pixelclock = SUPPORT_PIXEL_CLOCK;
DRM_DEV_DEBUG_DRIVER(dev, "drm mode checking\n");
+ if (!ctx->host->compression_supported) {
+ DRM_DEV_DEBUG_DRIVER(dev, "host not support DSC");
+ maximum_pixelclock = DSC_PIXEL_CLOCK;
+ }
- /* Max 1200p at 5.4 Ghz, one lane, pixel clock 300M */
- if (mode->clock > SUPPORT_PIXEL_CLOCK) {
+ if (mode->clock > maximum_pixelclock) {
DRM_DEV_DEBUG_DRIVER(dev,
"drm mode invalid, pixelclock too high.\n");
return MODE_CLOCK_HIGH;
}
+ if (mode->clock < SUPPORT_MIN_PIXEL_CLOCK)
+ return MODE_CLOCK_LOW;
+
+ /*
+ * If hdisplay cannot be divided by DSC compress ratio, then display
+ * will have overlap/shift issue
+ */
+ if (mode->clock > DSC_PIXEL_CLOCK &&
+ (mode->hdisplay % DSC_COMPRESS_RATIO != 0))
+ return MODE_CLOCK_HIGH;
+
DRM_DEV_DEBUG_DRIVER(dev, "drm mode valid.\n");
return MODE_OK;
}
+static void anx7625_dsc_enable(struct anx7625_data *ctx, bool en)
+{
+ int ret;
+ struct device *dev = ctx->dev;
+
+ if (en) {
+ ctx->dsc.dsc_version_major = 1;
+ ctx->dsc.dsc_version_minor = 1;
+ ctx->dsc.slice_height = 8;
+ ctx->dsc.slice_width = ctx->dt.hactive.min / DSC_SLICE_NUM;
+ ctx->dsc.slice_count = DSC_SLICE_NUM;
+ ctx->dsc.bits_per_component = 8;
+ ctx->dsc.bits_per_pixel = 8 << 4; /* 4 fractional bits */
+ ctx->dsc.block_pred_enable = true;
+ ctx->dsc.native_420 = false;
+ ctx->dsc.native_422 = false;
+ ctx->dsc.simple_422 = false;
+ ctx->dsc.vbr_enable = false;
+ ctx->dsc.convert_rgb = 1;
+
+ drm_dsc_set_rc_buf_thresh(&ctx->dsc);
+ drm_dsc_set_const_params(&ctx->dsc);
+
+ ctx->dsc.initial_scale_value = drm_dsc_initial_scale_value(&ctx->dsc);
+ ctx->dsc.line_buf_depth = ctx->dsc.bits_per_component + 1;
+ ret = drm_dsc_setup_rc_params(&ctx->dsc, DRM_DSC_1_2_444);
+ if (ret < 0)
+ dev_warn(dev, "drm_dsc_setup_rc_params ret %d\n", ret);
+
+ ret = drm_dsc_compute_rc_parameters(&ctx->dsc);
+ if (ret)
+ dev_warn(dev, "drm dsc compute rc parameters failed ret %d\n", ret);
+
+ drm_dsc_pps_payload_pack((struct drm_dsc_picture_parameter_set *)&ctx->pps_table,
+ &ctx->dsc);
+ dev_dbg(dev, "anx7625 enable dsc\n");
+ } else {
+ ctx->dsc.dsc_version_major = 0;
+ ctx->dsc.dsc_version_minor = 0;
+ dev_dbg(dev, "anx7625 disable dsc\n");
+ }
+}
+
static void anx7625_bridge_mode_set(struct drm_bridge *bridge,
const struct drm_display_mode *old_mode,
const struct drm_display_mode *mode)
@@ -2283,6 +2430,8 @@ static void anx7625_bridge_mode_set(struct drm_bridge *bridge,
DRM_DEV_DEBUG_DRIVER(dev, "vsync_end(%d),vtotal(%d).\n",
mode->vsync_end,
mode->vtotal);
+
+ anx7625_dsc_enable(ctx, anx7625_dsc_check(ctx, ctx->dt.pixelclock.min));
}
static bool anx7625_bridge_mode_fixup(struct drm_bridge *bridge,
@@ -2297,10 +2446,6 @@ static bool anx7625_bridge_mode_fixup(struct drm_bridge *bridge,
DRM_DEV_DEBUG_DRIVER(dev, "drm mode fixup set\n");
- /* No need fixup for external monitor */
- if (!ctx->pdata.panel_bridge)
- return true;
-
hsync = mode->hsync_end - mode->hsync_start;
hfp = mode->hsync_start - mode->hdisplay;
hbp = mode->htotal - mode->hsync_end;
@@ -2311,12 +2456,24 @@ static bool anx7625_bridge_mode_fixup(struct drm_bridge *bridge,
hsync, hfp, hbp, adj->clock);
DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n",
adj->hsync_start, adj->hsync_end, adj->htotal);
-
adj_hfp = hfp;
adj_hsync = hsync;
adj_hbp = hbp;
adj_hblanking = hblanking;
+ if (anx7625_dsc_check(ctx, mode->clock)) {
+ adj_hsync = DSC_HSYNC_LEN;
+ adj_hfp = DSC_HFP_LEN;
+ adj_hbp = DSC_HBP_LEN;
+ vref = (u32)div_u64((u64)adj->clock * 1000 * 1000,
+ adj->htotal * adj->vtotal);
+ goto calculate_timing;
+ }
+
+ /* No need fixup for external monitor */
+ if (!ctx->pdata.panel_bridge)
+ return true;
+
/* HFP needs to be even */
if (hfp & 0x1) {
adj_hfp += 1;
@@ -2388,6 +2545,8 @@ static bool anx7625_bridge_mode_fixup(struct drm_bridge *bridge,
adj_hfp -= delta_adj;
}
+calculate_timing:
+
DRM_DEV_DEBUG_DRIVER(dev, "after mode fixup\n");
DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n",
adj_hsync, adj_hfp, adj_hbp, adj->clock);
@@ -2396,6 +2555,10 @@ static bool anx7625_bridge_mode_fixup(struct drm_bridge *bridge,
adj->hsync_start = adj->hdisplay + adj_hfp;
adj->hsync_end = adj->hsync_start + adj_hsync;
adj->htotal = adj->hsync_end + adj_hbp;
+ if (anx7625_dsc_check(ctx, mode->clock))
+ adj->clock = (u32)div_u64((u64)vref * adj->htotal * adj->vtotal,
+ 1000 * 1000);
+
DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n",
adj->hsync_start, adj->hsync_end, adj->htotal);
diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.h b/drivers/gpu/drm/bridge/analogix/anx7625.h
index df9efecae55a..e0953864062a 100644
--- a/drivers/gpu/drm/bridge/analogix/anx7625.h
+++ b/drivers/gpu/drm/bridge/analogix/anx7625.h
@@ -149,6 +149,8 @@
#define HFP_HBP_DEF ((HBLANKING_MIN - SYNC_LEN_DEF) / 2)
#define VIDEO_CONTROL_0 0x08
+#define TOTAL_LINES_L 0x12
+#define TOTAL_LINES_H 0x13
#define ACTIVE_LINES_L 0x14
#define ACTIVE_LINES_H 0x15 /* Bit[7:6] are reserved */
#define VERTICAL_FRONT_PORCH 0x16
@@ -168,7 +170,27 @@
#define DSC_COMPRESS_RATIO 3
#define dsc_div(X) ((X) / DSC_COMPRESS_RATIO)
+#define DSC_SLICE_NUM 2
#define DSC_PIXEL_CLOCK 250000
+#define DSC_HSYNC_LEN 90
+#define DSC_HFP_LEN 177
+#define DSC_HBP_LEN 297
+
+#define TOTAL_PIXEL_L_7E 0x50
+#define TOTAL_PIXEL_H_7E 0x51 /* bit[7:6] are reserved */
+#define ACTIVE_PIXEL_L_7E 0x52
+#define ACTIVE_PIXEL_H_7E 0x53 /* bit[7:6] are reserved */
+#define HORIZON_FRONT_PORCH_L_7E 0x54
+#define HORIZON_FRONT_PORCH_H_7E 0x55
+#define HORIZON_SYNC_WIDTH_L_7E 0x56
+#define HORIZON_SYNC_WIDTH_H_7E 0x57
+#define HORIZON_BACK_PORCH_L_7E 0x58
+#define HORIZON_BACK_PORCH_H_7E 0x59
+
+#define PPS_SIZE 128
+#define PPS_BLOCK_SIZE 32
+#define R_PPS_REG_0 0x80
+#define R_I2C_1 0x81
/******** END of I2C Address 0x72 *********/
@@ -419,6 +441,7 @@ enum audio_wd_len {
#define MAX_EDID_BLOCK 3
#define EDID_TRY_CNT 3
#define SUPPORT_PIXEL_CLOCK 300000
+#define SUPPORT_MIN_PIXEL_CLOCK 38000
/***************** Display End *****************/
@@ -482,7 +505,10 @@ struct anx7625_data {
u8 bridge_attached;
struct drm_connector *connector;
struct mipi_dsi_device *dsi;
+ struct mipi_dsi_host *host;
struct drm_dp_aux aux;
+ struct drm_dsc_config dsc;
+ char pps_table[PPS_SIZE];
};
#endif /* __ANX7625_H__ */
--
2.25.1
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