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From: Aleksandrs Vinarskis <alex.vinarskis@gmail.com>
To: Dmitry Baryshkov <lumag@kernel.org>,
	linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
	freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org,
	dmitry.baryshkov@oss.qualcomm.com
Cc: Rob Clark <robdclark@gmail.com>,
	Abhinav Kumar <quic_abhinavk@quicinc.com>,
	Sean Paul <sean@poorly.run>,
	Marijn Suijten <marijn.suijten@somainline.org>,
	David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
	laurentiu.tudor1@dell.com, abel.vesa@linaro.org,
	johan@kernel.org, Aleksandrs Vinarskis <alex.vinarskis@gmail.com>
Subject: [PATCH v3 2/4] drm/msm/dp: Account for LTTPRs capabilities
Date: Thu, 17 Apr 2025 04:10:33 +0200	[thread overview]
Message-ID: <20250417021349.148911-3-alex.vinarskis@gmail.com> (raw)
In-Reply-To: <20250417021349.148911-1-alex.vinarskis@gmail.com>

Take into account LTTPR capabilities when selecting maximum allowed
link rate, number of data lines.

Signed-off-by: Aleksandrs Vinarskis <alex.vinarskis@gmail.com>
---
 drivers/gpu/drm/msm/dp/dp_display.c |  5 ++---
 drivers/gpu/drm/msm/dp/dp_link.h    |  3 +++
 drivers/gpu/drm/msm/dp/dp_panel.c   | 12 +++++++++++-
 3 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c
index fc07cce68382..5c57c1d7ac60 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -369,13 +369,12 @@ static int msm_dp_display_send_hpd_notification(struct msm_dp_display_private *d
 
 static void msm_dp_display_lttpr_init(struct msm_dp_display_private *dp, u8 *dpcd)
 {
-	u8 lttpr_caps[DP_LTTPR_COMMON_CAP_SIZE];
 	int rc;
 
-	if (drm_dp_read_lttpr_common_caps(dp->aux, dpcd, lttpr_caps))
+	if (drm_dp_read_lttpr_common_caps(dp->aux, dpcd, dp->link->lttpr_common_caps))
 		return;
 
-	rc = drm_dp_lttpr_init(dp->aux, drm_dp_lttpr_count(lttpr_caps));
+	rc = drm_dp_lttpr_init(dp->aux, drm_dp_lttpr_count(dp->link->lttpr_common_caps));
 	if (rc)
 		DRM_ERROR("failed to set LTTPRs transparency mode, rc=%d\n", rc);
 }
diff --git a/drivers/gpu/drm/msm/dp/dp_link.h b/drivers/gpu/drm/msm/dp/dp_link.h
index 8db5d5698a97..c47d75cfc720 100644
--- a/drivers/gpu/drm/msm/dp/dp_link.h
+++ b/drivers/gpu/drm/msm/dp/dp_link.h
@@ -7,6 +7,7 @@
 #define _DP_LINK_H_
 
 #include "dp_aux.h"
+#include <drm/display/drm_dp_helper.h>
 
 #define DS_PORT_STATUS_CHANGED 0x200
 #define DP_TEST_BIT_DEPTH_UNKNOWN 0xFFFFFFFF
@@ -60,6 +61,8 @@ struct msm_dp_link_phy_params {
 };
 
 struct msm_dp_link {
+	u8 lttpr_common_caps[DP_LTTPR_COMMON_CAP_SIZE];
+
 	u32 sink_request;
 	u32 test_response;
 
diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_panel.c
index 92415bf8aa16..4e8ab75c771b 100644
--- a/drivers/gpu/drm/msm/dp/dp_panel.c
+++ b/drivers/gpu/drm/msm/dp/dp_panel.c
@@ -47,7 +47,7 @@ static void msm_dp_panel_read_psr_cap(struct msm_dp_panel_private *panel)
 
 static int msm_dp_panel_read_dpcd(struct msm_dp_panel *msm_dp_panel)
 {
-	int rc;
+	int rc, max_lttpr_lanes, max_lttpr_rate;
 	struct msm_dp_panel_private *panel;
 	struct msm_dp_link_info *link_info;
 	u8 *dpcd, major, minor;
@@ -75,6 +75,16 @@ static int msm_dp_panel_read_dpcd(struct msm_dp_panel *msm_dp_panel)
 	if (link_info->rate > msm_dp_panel->max_dp_link_rate)
 		link_info->rate = msm_dp_panel->max_dp_link_rate;
 
+	/* Limit data lanes from LTTPR capabilities, if any */
+	max_lttpr_lanes = drm_dp_lttpr_max_lane_count(panel->link->lttpr_common_caps);
+	if (max_lttpr_lanes && max_lttpr_lanes < link_info->num_lanes)
+		link_info->num_lanes = max_lttpr_lanes;
+
+	/* Limit link rate from LTTPR capabilities, if any */
+	max_lttpr_rate = drm_dp_lttpr_max_link_rate(panel->link->lttpr_common_caps);
+	if (max_lttpr_rate && max_lttpr_rate < link_info->rate)
+		link_info->rate = max_lttpr_rate;
+
 	drm_dbg_dp(panel->drm_dev, "version: %d.%d\n", major, minor);
 	drm_dbg_dp(panel->drm_dev, "link_rate=%d\n", link_info->rate);
 	drm_dbg_dp(panel->drm_dev, "lane_count=%d\n", link_info->num_lanes);
-- 
2.45.2


  parent reply	other threads:[~2025-04-17  2:13 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-04-17  2:10 drm/msm/dp: Introduce link training per-segment for LTTPRs Aleksandrs Vinarskis
2025-04-17  2:10 ` [PATCH v3 1/4] drm/msm/dp: Fix support of LTTPR initialization Aleksandrs Vinarskis
2025-04-24 21:48   ` Dmitry Baryshkov
2025-04-17  2:10 ` Aleksandrs Vinarskis [this message]
2025-04-25  6:53   ` [PATCH v3 2/4] drm/msm/dp: Account for LTTPRs capabilities Abel Vesa
2025-04-25  9:20   ` Dmitry Baryshkov
2025-04-17  2:10 ` [PATCH v3 3/4] drm/msm/dp: Prepare for link training per-segment for LTTPRs Aleksandrs Vinarskis
2025-04-25  6:53   ` Abel Vesa
2025-04-25 19:05   ` Dmitry Baryshkov
2025-04-17  2:10 ` [PATCH v3 4/4] drm/msm/dp: Introduce " Aleksandrs Vinarskis
2025-04-25 19:07   ` Dmitry Baryshkov
2025-04-28 20:07   ` Rob Clark
2025-04-24 21:12 ` Rob Clark
2025-04-24 22:14   ` Dmitry Baryshkov
2025-04-28  7:45 ` Johan Hovold
2025-04-28  9:06   ` Aleksandrs Vinarskis
2025-04-28 12:47     ` Johan Hovold
2025-04-28 14:17       ` Abel Vesa
2025-04-28 18:23         ` Aleksandrs Vinarskis
2025-04-29  6:52           ` Abel Vesa
2025-04-29  7:29             ` Aleksandrs Vinarskis
2025-04-29  7:23         ` Johan Hovold
2025-04-29  7:50           ` Abel Vesa
2025-04-29  8:03             ` Johan Hovold
2025-04-29 10:57               ` Aleksandrs Vinarskis
2025-04-29 11:31                 ` Johan Hovold
2025-04-29 13:07                 ` Dmitry Baryshkov

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