[PATCH V2 0/5] Several fixes for group flag and counters-snapshotting

[PATCH V2 0/5] Several fixes for group flag and counters-snapshotting

[kan.liang]

From: Kan Liang <kan.liang@linux.intel.com>

The patch series includes several fixes for the new Intel features.

The first 4 patches are to fix the group flag issue which impacts the
branch counters, PEBS counters-snapshotting and ACR.
The V1 can be found at
https://lore.kernel.org/lkml/20250423221015.268949-1-kan.liang@linux.intel.com/

The last patch is to fix an issue of counters-snapshotting.
The V1 can be found at
https://lore.kernel.org/lkml/20250204210514.4089680-1-kan.liang@linux.intel.com/

Kan Liang (5):
  perf/x86/intel: Only check the group flag for X86 leader
  perf/x86/intel: Check the X86 leader for pebs_counter_event_group
  perf/x86/intel: Check the X86 leader for ACR group
  perf/x86: Optimize the is_x86_event
  perf/x86/intel/ds: Fix counter backwards of non-precise events
    counters-snapshotting

 arch/x86/events/core.c       | 19 ++++++++++---------
 arch/x86/events/intel/ds.c   | 21 +++++++++++++++++++--
 arch/x86/events/perf_event.h | 14 ++++++++++----
 3 files changed, 39 insertions(+), 15 deletions(-)

-- 
2.38.1

[PATCH V2 1/5] perf/x86/intel: Only check the group flag for X86 leader

[kan.liang]

From: Kan Liang <kan.liang@linux.intel.com>

A warning in intel_pmu_lbr_counters_reorder() may be triggered by below
perf command.

perf record -e "{cpu-clock,cycles/call-graph="lbr"/}" -- sleep 1

It's because the group is mistakenly treated as a branch counter group.

The hw.flags of the leader are used to determine whether a group is a
branch counters group. However, the hw.flags is only available for a
hardware event. The field to store the flags is a union type. For a
software event, it's a hrtimer. The corresponding bit may be set if the
leader is a software event.

For a branch counter group and other groups that have a group flag
(e.g., topdown, PEBS counters snapshotting, and ACR), the leader must
be a X86 event. Check the X86 event before checking the flag.
The patch only fixes the issue for the branch counter group.
The following patch will fix the other groups.

There may be an alternative way to fix the issue by moving the hw.flags
out of the union type. It should work for now. But it's still possible
that the flags will be used by other types of events later. As long as
that type of event is used as a leader, a similar issue will be
triggered. So the alternative way is dropped.

Fixes: 33744916196b ("perf/x86/intel: Support branch counters logging")
Reported-by: Luo Gengkun <luogengkun@huaweicloud.com>
Closes: https://lore.kernel.org/lkml/20250412091423.1839809-1-luogengkun@huaweicloud.com/
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Cc: stable@vger.kernel.org
---
 arch/x86/events/perf_event.h | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 902bc42a6cfe..4fc61a09c30e 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -110,9 +110,16 @@ static inline bool is_topdown_event(struct perf_event *event)
 	return is_metric_event(event) || is_slots_event(event);
 }
 
+int is_x86_event(struct perf_event *event);
+
+static inline bool check_leader_group(struct perf_event *leader, int flags)
+{
+	return is_x86_event(leader) ? !!(leader->hw.flags & flags) : false;
+}
+
 static inline bool is_branch_counters_group(struct perf_event *event)
 {
-	return event->group_leader->hw.flags & PERF_X86_EVENT_BRANCH_COUNTERS;
+	return check_leader_group(event->group_leader, PERF_X86_EVENT_PEBS_CNTR);
 }
 
 static inline bool is_pebs_counter_event_group(struct perf_event *event)
@@ -1129,7 +1136,6 @@ static struct perf_pmu_format_hybrid_attr format_attr_hybrid_##_name = {\
 	.pmu_type	= _pmu,						\
 }
 
-int is_x86_event(struct perf_event *event);
 struct pmu *x86_get_pmu(unsigned int cpu);
 extern struct x86_pmu x86_pmu __read_mostly;
 
-- 
2.38.1

[tip: perf/core] perf/x86/intel: Only check the group flag for X86 leader

[tip-bot2 for Kan Liang]

The following commit has been merged into the perf/core branch of tip:

Commit-ID:     75aea4b0656ead0facd13d2aae4cb77326e53d2f
Gitweb:        https://git.kernel.org/tip/75aea4b0656ead0facd13d2aae4cb77326e53d2f
Author:        Kan Liang <kan.liang@linux.intel.com>
AuthorDate:    Thu, 24 Apr 2025 06:47:14 -07:00
Committer:     Peter Zijlstra <peterz@infradead.org>
CommitterDate: Fri, 25 Apr 2025 14:55:19 +02:00

perf/x86/intel: Only check the group flag for X86 leader

A warning in intel_pmu_lbr_counters_reorder() may be triggered by below
perf command.

perf record -e "{cpu-clock,cycles/call-graph="lbr"/}" -- sleep 1

It's because the group is mistakenly treated as a branch counter group.

The hw.flags of the leader are used to determine whether a group is a
branch counters group. However, the hw.flags is only available for a
hardware event. The field to store the flags is a union type. For a
software event, it's a hrtimer. The corresponding bit may be set if the
leader is a software event.

For a branch counter group and other groups that have a group flag
(e.g., topdown, PEBS counters snapshotting, and ACR), the leader must
be a X86 event. Check the X86 event before checking the flag.
The patch only fixes the issue for the branch counter group.
The following patch will fix the other groups.

There may be an alternative way to fix the issue by moving the hw.flags
out of the union type. It should work for now. But it's still possible
that the flags will be used by other types of events later. As long as
that type of event is used as a leader, a similar issue will be
triggered. So the alternative way is dropped.

Fixes: 33744916196b ("perf/x86/intel: Support branch counters logging")
Closes: https://lore.kernel.org/lkml/20250412091423.1839809-1-luogengkun@huaweicloud.com/
Reported-by: Luo Gengkun <luogengkun@huaweicloud.com>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: stable@vger.kernel.org
Link: https://lkml.kernel.org/r/20250424134718.311934-2-kan.liang@linux.intel.com
---
 arch/x86/events/core.c       |  2 +-
 arch/x86/events/perf_event.h |  9 ++++++++-
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index 3a4f031..139ad80 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -754,7 +754,7 @@ void x86_pmu_enable_all(int added)
 	}
 }
 
-static inline int is_x86_event(struct perf_event *event)
+int is_x86_event(struct perf_event *event)
 {
 	int i;
 
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 2c0ce0e..4237c37 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -110,9 +110,16 @@ static inline bool is_topdown_event(struct perf_event *event)
 	return is_metric_event(event) || is_slots_event(event);
 }
 
+int is_x86_event(struct perf_event *event);
+
+static inline bool check_leader_group(struct perf_event *leader, int flags)
+{
+	return is_x86_event(leader) ? !!(leader->hw.flags & flags) : false;
+}
+
 static inline bool is_branch_counters_group(struct perf_event *event)
 {
-	return event->group_leader->hw.flags & PERF_X86_EVENT_BRANCH_COUNTERS;
+	return check_leader_group(event->group_leader, PERF_X86_EVENT_BRANCH_COUNTERS);
 }
 
 static inline bool is_pebs_counter_event_group(struct perf_event *event)

[PATCH V2 2/5] perf/x86/intel: Check the X86 leader for pebs_counter_event_group

[kan.liang]

From: Kan Liang <kan.liang@linux.intel.com>

The PEBS counters snapshotting group also requires a group flag in the
leader. The leader must be a X86 event.

Fixes: e02e9b0374c3 ("perf/x86/intel: Support PEBS counters snapshotting")
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---
 arch/x86/events/perf_event.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 4fc61a09c30e..fd409d70e568 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -124,7 +124,7 @@ static inline bool is_branch_counters_group(struct perf_event *event)
 
 static inline bool is_pebs_counter_event_group(struct perf_event *event)
 {
-	return event->group_leader->hw.flags & PERF_X86_EVENT_PEBS_CNTR;
+	return check_leader_group(event->group_leader, PERF_X86_EVENT_PEBS_CNTR);
 }
 
 static inline bool is_acr_event_group(struct perf_event *event)
-- 
2.38.1

[tip: perf/core] perf/x86/intel: Check the X86 leader for pebs_counter_event_group

[tip-bot2 for Kan Liang]

The following commit has been merged into the perf/core branch of tip:

Commit-ID:     e9988ad7b1744991118ac348a804f9395368a284
Gitweb:        https://git.kernel.org/tip/e9988ad7b1744991118ac348a804f9395368a284
Author:        Kan Liang <kan.liang@linux.intel.com>
AuthorDate:    Thu, 24 Apr 2025 06:47:15 -07:00
Committer:     Peter Zijlstra <peterz@infradead.org>
CommitterDate: Fri, 25 Apr 2025 14:55:19 +02:00

perf/x86/intel: Check the X86 leader for pebs_counter_event_group

The PEBS counters snapshotting group also requires a group flag in the
leader. The leader must be a X86 event.

Fixes: e02e9b0374c3 ("perf/x86/intel: Support PEBS counters snapshotting")
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20250424134718.311934-3-kan.liang@linux.intel.com
---
 arch/x86/events/perf_event.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 4237c37..46d1205 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -124,7 +124,7 @@ static inline bool is_branch_counters_group(struct perf_event *event)
 
 static inline bool is_pebs_counter_event_group(struct perf_event *event)
 {
-	return event->group_leader->hw.flags & PERF_X86_EVENT_PEBS_CNTR;
+	return check_leader_group(event->group_leader, PERF_X86_EVENT_PEBS_CNTR);
 }
 
 struct amd_nb {

[PATCH V2 3/5] perf/x86/intel: Check the X86 leader for ACR group

[kan.liang]

From: Kan Liang <kan.liang@linux.intel.com>

The auto counter reload group also requires a group flag in the leader.
The leader must be a X86 event.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---
 arch/x86/events/perf_event.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index fd409d70e568..bac252ba3da6 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -129,7 +129,7 @@ static inline bool is_pebs_counter_event_group(struct perf_event *event)
 
 static inline bool is_acr_event_group(struct perf_event *event)
 {
-	return event->group_leader->hw.flags & PERF_X86_EVENT_ACR;
+	return check_leader_group(event->group_leader, PERF_X86_EVENT_ACR);
 }
 
 struct amd_nb {
-- 
2.38.1

[tip: perf/core] perf/x86/intel: Check the X86 leader for ACR group

[tip-bot2 for Kan Liang]

The following commit has been merged into the perf/core branch of tip:

Commit-ID:     efd448540e6243dbdaf0a7e1bcf49734e73f3c93
Gitweb:        https://git.kernel.org/tip/efd448540e6243dbdaf0a7e1bcf49734e73f3c93
Author:        Kan Liang <kan.liang@linux.intel.com>
AuthorDate:    Thu, 24 Apr 2025 06:47:16 -07:00
Committer:     Peter Zijlstra <peterz@infradead.org>
CommitterDate: Fri, 25 Apr 2025 14:55:22 +02:00

perf/x86/intel: Check the X86 leader for ACR group

The auto counter reload group also requires a group flag in the leader.
The leader must be a X86 event.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20250424134718.311934-4-kan.liang@linux.intel.com
---
 arch/x86/events/perf_event.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 9c5cab8..e8bce89 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -129,7 +129,7 @@ static inline bool is_pebs_counter_event_group(struct perf_event *event)
 
 static inline bool is_acr_event_group(struct perf_event *event)
 {
-	return event->group_leader->hw.flags & PERF_X86_EVENT_ACR;
+	return check_leader_group(event->group_leader, PERF_X86_EVENT_ACR);
 }
 
 struct amd_nb {

[PATCH V2 4/5] perf/x86: Optimize the is_x86_event

[kan.liang]

From: Kan Liang <kan.liang@linux.intel.com>

The current is_x86_event has to go through the hybrid_pmus list to find
the matched pmu, then check if it's a X86 PMU and a X86 event. It's not
necessary.

The X86 PMU has a unique type ID on a non-hybrid machine, and a unique
capability type. They are good enough to do the check.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---
 arch/x86/events/core.c | 19 ++++++++++---------
 1 file changed, 10 insertions(+), 9 deletions(-)

diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index b0ef07d14c83..43053ddd7073 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -757,15 +757,16 @@ void x86_pmu_enable_all(int added)
 
 int is_x86_event(struct perf_event *event)
 {
-	int i;
-
-	if (!is_hybrid())
-		return event->pmu == &pmu;
-
-	for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) {
-		if (event->pmu == &x86_pmu.hybrid_pmu[i].pmu)
-			return true;
-	}
+	/*
+	 * For a non-hybrid platforms, the type of X86 pmu is
+	 * always PERF_TYPE_RAW.
+	 * For a hybrid platform, the PERF_PMU_CAP_EXTENDED_HW_TYPE
+	 * is a unique capability for the X86 PMU.
+	 * Use them to detect a X86 event.
+	 */
+	if (event->pmu->type == PERF_TYPE_RAW ||
+	    event->pmu->capabilities & PERF_PMU_CAP_EXTENDED_HW_TYPE)
+		return true;
 
 	return false;
 }
-- 
2.38.1

[tip: perf/core] perf/x86: Optimize the is_x86_event

[tip-bot2 for Kan Liang]

The following commit has been merged into the perf/core branch of tip:

Commit-ID:     3e830f657f69ab6a4822d72ec2f364c6d51beef8
Gitweb:        https://git.kernel.org/tip/3e830f657f69ab6a4822d72ec2f364c6d51beef8
Author:        Kan Liang <kan.liang@linux.intel.com>
AuthorDate:    Thu, 24 Apr 2025 06:47:17 -07:00
Committer:     Peter Zijlstra <peterz@infradead.org>
CommitterDate: Fri, 25 Apr 2025 14:55:22 +02:00

perf/x86: Optimize the is_x86_event

The current is_x86_event has to go through the hybrid_pmus list to find
the matched pmu, then check if it's a X86 PMU and a X86 event. It's not
necessary.

The X86 PMU has a unique type ID on a non-hybrid machine, and a unique
capability type. They are good enough to do the check.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20250424134718.311934-5-kan.liang@linux.intel.com
---
 arch/x86/events/core.c | 19 ++++++++++---------
 1 file changed, 10 insertions(+), 9 deletions(-)

diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index b2762f2..92c3fb6 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -762,15 +762,16 @@ void x86_pmu_enable_all(int added)
 
 int is_x86_event(struct perf_event *event)
 {
-	int i;
-
-	if (!is_hybrid())
-		return event->pmu == &pmu;
-
-	for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) {
-		if (event->pmu == &x86_pmu.hybrid_pmu[i].pmu)
-			return true;
-	}
+	/*
+	 * For a non-hybrid platforms, the type of X86 pmu is
+	 * always PERF_TYPE_RAW.
+	 * For a hybrid platform, the PERF_PMU_CAP_EXTENDED_HW_TYPE
+	 * is a unique capability for the X86 PMU.
+	 * Use them to detect a X86 event.
+	 */
+	if (event->pmu->type == PERF_TYPE_RAW ||
+	    event->pmu->capabilities & PERF_PMU_CAP_EXTENDED_HW_TYPE)
+		return true;
 
 	return false;
 }

[PATCH V2 5/5] perf/x86/intel/ds: Fix counter backwards of non-precise events counters-snapshotting

[kan.liang]

From: Kan Liang <kan.liang@linux.intel.com>

The counter backwards may be observed in the PMI handler when
counters-snapshotting some non-precise events in the freq mode.

For the non-precise events, it's possible the counters-snapshotting
records a positive value for an overflowed PEBS event. Then the HW
auto-reload mechanism reset the counter to 0 immediately. Because the
pebs_event_reset is cleared in the freq mode, which doesn't set the
PERF_X86_EVENT_AUTO_RELOAD.
In the PMI handler, 0 will be read rather than the positive value
recorded in the counters-snapshotting record.

The counters-snapshotting case has to be specially handled. Since the
event value has been updated when processing the counters-snapshotting
record, only needs to set the new period for the counter via
x86_pmu_set_period().

Fixes: e02e9b0374c3 ("perf/x86/intel: Support PEBS counters snapshotting")
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---
 arch/x86/events/intel/ds.c | 21 +++++++++++++++++++--
 1 file changed, 19 insertions(+), 2 deletions(-)

diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index 486881fe162e..83ffbfdf4982 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -2376,8 +2376,25 @@ __intel_pmu_pebs_last_event(struct perf_event *event,
 			 */
 			intel_pmu_save_and_restart_reload(event, count);
 		}
-	} else
-		intel_pmu_save_and_restart(event);
+	} else {
+		/*
+		 * For a non-precise event, it's possible the
+		 * counters-snapshotting records a positive value for the
+		 * overflowed event. Then the HW auto-reload mechanism
+		 * reset the counter to 0 immediately, because the
+		 * pebs_event_reset is cleared if the PERF_X86_EVENT_AUTO_RELOAD
+		 * is not set. The counter backwards may be observed in a
+		 * PMI handler.
+		 *
+		 * Since the event value has been updated when processing the
+		 * counters-snapshotting record, only needs to set the new
+		 * period for the counter.
+		 */
+		if (is_pebs_counter_event_group(event))
+			static_call(x86_pmu_set_period)(event);
+		else
+			intel_pmu_save_and_restart(event);
+	}
 }
 
 static __always_inline void
-- 
2.38.1

[tip: perf/core] perf/x86/intel/ds: Fix counter backwards of non-precise events counters-snapshotting

[tip-bot2 for Kan Liang]

The following commit has been merged into the perf/core branch of tip:

Commit-ID:     7da9960b59fb7e590eb8538c9428db55a4ea2d23
Gitweb:        https://git.kernel.org/tip/7da9960b59fb7e590eb8538c9428db55a4ea2d23
Author:        Kan Liang <kan.liang@linux.intel.com>
AuthorDate:    Thu, 24 Apr 2025 06:47:18 -07:00
Committer:     Peter Zijlstra <peterz@infradead.org>
CommitterDate: Fri, 25 Apr 2025 14:55:19 +02:00

perf/x86/intel/ds: Fix counter backwards of non-precise events counters-snapshotting

The counter backwards may be observed in the PMI handler when
counters-snapshotting some non-precise events in the freq mode.

For the non-precise events, it's possible the counters-snapshotting
records a positive value for an overflowed PEBS event. Then the HW
auto-reload mechanism reset the counter to 0 immediately. Because the
pebs_event_reset is cleared in the freq mode, which doesn't set the
PERF_X86_EVENT_AUTO_RELOAD.
In the PMI handler, 0 will be read rather than the positive value
recorded in the counters-snapshotting record.

The counters-snapshotting case has to be specially handled. Since the
event value has been updated when processing the counters-snapshotting
record, only needs to set the new period for the counter via
x86_pmu_set_period().

Fixes: e02e9b0374c3 ("perf/x86/intel: Support PEBS counters snapshotting")
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20250424134718.311934-6-kan.liang@linux.intel.com
---
 arch/x86/events/intel/ds.c | 21 +++++++++++++++++++--
 1 file changed, 19 insertions(+), 2 deletions(-)

diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index 18c3ab5..9b20acc 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -2379,8 +2379,25 @@ __intel_pmu_pebs_last_event(struct perf_event *event,
 			 */
 			intel_pmu_save_and_restart_reload(event, count);
 		}
-	} else
-		intel_pmu_save_and_restart(event);
+	} else {
+		/*
+		 * For a non-precise event, it's possible the
+		 * counters-snapshotting records a positive value for the
+		 * overflowed event. Then the HW auto-reload mechanism
+		 * reset the counter to 0 immediately, because the
+		 * pebs_event_reset is cleared if the PERF_X86_EVENT_AUTO_RELOAD
+		 * is not set. The counter backwards may be observed in a
+		 * PMI handler.
+		 *
+		 * Since the event value has been updated when processing the
+		 * counters-snapshotting record, only needs to set the new
+		 * period for the counter.
+		 */
+		if (is_pebs_counter_event_group(event))
+			static_call(x86_pmu_set_period)(event);
+		else
+			intel_pmu_save_and_restart(event);
+	}
 }
 
 static __always_inline void

Re: [PATCH V2 0/5] Several fixes for group flag and counters-snapshotting

[Peter Zijlstra]

On Thu, Apr 24, 2025 at 06:47:13AM -0700, kan.liang@linux.intel.com wrote:
> From: Kan Liang <kan.liang@linux.intel.com>
> 
> The patch series includes several fixes for the new Intel features.
> 
> The first 4 patches are to fix the group flag issue which impacts the
> branch counters, PEBS counters-snapshotting and ACR.
> The V1 can be found at
> https://lore.kernel.org/lkml/20250423221015.268949-1-kan.liang@linux.intel.com/
> 
> The last patch is to fix an issue of counters-snapshotting.
> The V1 can be found at
> https://lore.kernel.org/lkml/20250204210514.4089680-1-kan.liang@linux.intel.com/
> 
> Kan Liang (5):
>   perf/x86/intel: Only check the group flag for X86 leader
>   perf/x86/intel: Check the X86 leader for pebs_counter_event_group
>   perf/x86/intel: Check the X86 leader for ACR group
>   perf/x86: Optimize the is_x86_event
>   perf/x86/intel/ds: Fix counter backwards of non-precise events
>     counters-snapshotting

It didn't apply cleanly, but I stomped on it and pushed out new
perf/urgent and perf/core branches that contain these patches. Hopefully
I didn't mess it up ;-)

Re: [PATCH V2 0/5] Several fixes for group flag and counters-snapshotting

[Liang, Kan]

On 2025-04-24 10:25 a.m., Peter Zijlstra wrote:
> On Thu, Apr 24, 2025 at 06:47:13AM -0700, kan.liang@linux.intel.com wrote:
>> From: Kan Liang <kan.liang@linux.intel.com>
>>
>> The patch series includes several fixes for the new Intel features.
>>
>> The first 4 patches are to fix the group flag issue which impacts the
>> branch counters, PEBS counters-snapshotting and ACR.
>> The V1 can be found at
>> https://lore.kernel.org/lkml/20250423221015.268949-1-kan.liang@linux.intel.com/
>>
>> The last patch is to fix an issue of counters-snapshotting.
>> The V1 can be found at
>> https://lore.kernel.org/lkml/20250204210514.4089680-1-kan.liang@linux.intel.com/
>>
>> Kan Liang (5):
>>   perf/x86/intel: Only check the group flag for X86 leader
>>   perf/x86/intel: Check the X86 leader for pebs_counter_event_group
>>   perf/x86/intel: Check the X86 leader for ACR group
>>   perf/x86: Optimize the is_x86_event
>>   perf/x86/intel/ds: Fix counter backwards of non-precise events
>>     counters-snapshotting
> 
> It didn't apply cleanly,

Sorry for it.

> but I stomped on it and pushed out new
> perf/urgent and perf/core branches that contain these patches. Hopefully
> I didn't mess it up ;-)

Something is missed in this patch 5d4d71ebc737 ("perf/x86/intel: Only
check the group flag for X86 leader")

diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index a73b1ff031b2..1f72a4f77b5c 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -119,7 +119,7 @@ static inline bool check_leader_group(struct
perf_event *leader, int flags)

 static inline bool is_branch_counters_group(struct perf_event *event)
 {
-	return check_leader_group(event->group_leader, PERF_X86_EVENT_PEBS_CNTR);
+	return check_leader_group(event->group_leader,
PERF_X86_EVENT_BRANCH_COUNTERS);
 }

 static inline bool is_pebs_counter_event_group(struct perf_event *event)
@@ -1123,7 +1123,6 @@ static struct perf_pmu_format_hybrid_attr
format_attr_hybrid_##_name = {\
 	.pmu_type	= _pmu,                                         \
 }

-int is_x86_event(struct perf_event *event);
 struct pmu *x86_get_pmu(unsigned int cpu);
 extern struct x86_pmu x86_pmu __read_mostly;


Thanks,
Kan

Re: [PATCH V2 0/5] Several fixes for group flag and counters-snapshotting

[Peter Zijlstra]

On Thu, Apr 24, 2025 at 12:00:02PM -0400, Liang, Kan wrote:
> 
> 
> On 2025-04-24 10:25 a.m., Peter Zijlstra wrote:
> > On Thu, Apr 24, 2025 at 06:47:13AM -0700, kan.liang@linux.intel.com wrote:
> >> From: Kan Liang <kan.liang@linux.intel.com>
> >>
> >> The patch series includes several fixes for the new Intel features.
> >>
> >> The first 4 patches are to fix the group flag issue which impacts the
> >> branch counters, PEBS counters-snapshotting and ACR.
> >> The V1 can be found at
> >> https://lore.kernel.org/lkml/20250423221015.268949-1-kan.liang@linux.intel.com/
> >>
> >> The last patch is to fix an issue of counters-snapshotting.
> >> The V1 can be found at
> >> https://lore.kernel.org/lkml/20250204210514.4089680-1-kan.liang@linux.intel.com/
> >>
> >> Kan Liang (5):
> >>   perf/x86/intel: Only check the group flag for X86 leader
> >>   perf/x86/intel: Check the X86 leader for pebs_counter_event_group
> >>   perf/x86/intel: Check the X86 leader for ACR group
> >>   perf/x86: Optimize the is_x86_event
> >>   perf/x86/intel/ds: Fix counter backwards of non-precise events
> >>     counters-snapshotting
> > 
> > It didn't apply cleanly,
> 
> Sorry for it.
> 
> > but I stomped on it and pushed out new
> > perf/urgent and perf/core branches that contain these patches. Hopefully
> > I didn't mess it up ;-)
> 
> Something is missed in this patch 5d4d71ebc737 ("perf/x86/intel: Only
> check the group flag for X86 leader")
> 
> diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
> index a73b1ff031b2..1f72a4f77b5c 100644
> --- a/arch/x86/events/perf_event.h
> +++ b/arch/x86/events/perf_event.h
> @@ -119,7 +119,7 @@ static inline bool check_leader_group(struct
> perf_event *leader, int flags)
> 
>  static inline bool is_branch_counters_group(struct perf_event *event)
>  {
> -	return check_leader_group(event->group_leader, PERF_X86_EVENT_PEBS_CNTR);
> +	return check_leader_group(event->group_leader,
> PERF_X86_EVENT_BRANCH_COUNTERS);
>  }
> 
>  static inline bool is_pebs_counter_event_group(struct perf_event *event)

Right.

> @@ -1123,7 +1123,6 @@ static struct perf_pmu_format_hybrid_attr
> format_attr_hybrid_##_name = {\
>  	.pmu_type	= _pmu,                                         \
>  }
> 
> -int is_x86_event(struct perf_event *event);
>  struct pmu *x86_get_pmu(unsigned int cpu);
>  extern struct x86_pmu x86_pmu __read_mostly;

See, that isn't there in tip/perf/urgent :-)


I've pushed out an updated set. Please check.

Re: [PATCH V2 0/5] Several fixes for group flag and counters-snapshotting

[Liang, Kan]

On 2025-04-25 8:55 a.m., Peter Zijlstra wrote:
> On Thu, Apr 24, 2025 at 12:00:02PM -0400, Liang, Kan wrote:
>>
>>
>> On 2025-04-24 10:25 a.m., Peter Zijlstra wrote:
>>> On Thu, Apr 24, 2025 at 06:47:13AM -0700, kan.liang@linux.intel.com wrote:
>>>> From: Kan Liang <kan.liang@linux.intel.com>
>>>>
>>>> The patch series includes several fixes for the new Intel features.
>>>>
>>>> The first 4 patches are to fix the group flag issue which impacts the
>>>> branch counters, PEBS counters-snapshotting and ACR.
>>>> The V1 can be found at
>>>> https://lore.kernel.org/lkml/20250423221015.268949-1-kan.liang@linux.intel.com/
>>>>
>>>> The last patch is to fix an issue of counters-snapshotting.
>>>> The V1 can be found at
>>>> https://lore.kernel.org/lkml/20250204210514.4089680-1-kan.liang@linux.intel.com/
>>>>
>>>> Kan Liang (5):
>>>>   perf/x86/intel: Only check the group flag for X86 leader
>>>>   perf/x86/intel: Check the X86 leader for pebs_counter_event_group
>>>>   perf/x86/intel: Check the X86 leader for ACR group
>>>>   perf/x86: Optimize the is_x86_event
>>>>   perf/x86/intel/ds: Fix counter backwards of non-precise events
>>>>     counters-snapshotting
>>>
>>> It didn't apply cleanly,
>>
>> Sorry for it.
>>
>>> but I stomped on it and pushed out new
>>> perf/urgent and perf/core branches that contain these patches. Hopefully
>>> I didn't mess it up ;-)
>>
>> Something is missed in this patch 5d4d71ebc737 ("perf/x86/intel: Only
>> check the group flag for X86 leader")
>>
>> diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
>> index a73b1ff031b2..1f72a4f77b5c 100644
>> --- a/arch/x86/events/perf_event.h
>> +++ b/arch/x86/events/perf_event.h
>> @@ -119,7 +119,7 @@ static inline bool check_leader_group(struct
>> perf_event *leader, int flags)
>>
>>  static inline bool is_branch_counters_group(struct perf_event *event)
>>  {
>> -	return check_leader_group(event->group_leader, PERF_X86_EVENT_PEBS_CNTR);
>> +	return check_leader_group(event->group_leader,
>> PERF_X86_EVENT_BRANCH_COUNTERS);
>>  }
>>
>>  static inline bool is_pebs_counter_event_group(struct perf_event *event)
> 
> Right.
> 
>> @@ -1123,7 +1123,6 @@ static struct perf_pmu_format_hybrid_attr
>> format_attr_hybrid_##_name = {\
>>  	.pmu_type	= _pmu,                                         \
>>  }
>>
>> -int is_x86_event(struct perf_event *event);
>>  struct pmu *x86_get_pmu(unsigned int cpu);
>>  extern struct x86_pmu x86_pmu __read_mostly;
> 
> See, that isn't there in tip/perf/urgent :-)
> >
> I've pushed out an updated set. Please check.

It looks good to me. Thanks a lot! :)

Kan