From: Heiko Stuebner <heiko@sntech.de>
To: heiko@sntech.de
Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
ziyao@disroot.org, kever.yang@rock-chips.com,
nicolas.frattaroli@collabora.com, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH 4/6] arm64: dts: rockchip: move rk3528 pinctrl node outside the soc node
Date: Mon, 19 May 2025 00:04:46 +0200 [thread overview]
Message-ID: <20250518220449.2722673-5-heiko@sntech.de> (raw)
In-Reply-To: <20250518220449.2722673-1-heiko@sntech.de>
The non-mmio pinctrl node is not supposed to be inside the soc simple-bus
as dtc points out:
../arch/arm64/boot/dts/rockchip/rk3528.dtsi:870.20-936.5: Warning (simple_bus_reg): /soc/pinctrl: missing or empty reg/ranges property
Move the pinctrl node outside and adapt the indentation.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk3528.dtsi | 136 +++++++++++------------
1 file changed, 68 insertions(+), 68 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
index b2724c969a76..d1c72b52aa4e 100644
--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
@@ -95,6 +95,74 @@ scmi_clk: protocol@14 {
};
};
+ pinctrl: pinctrl {
+ compatible = "rockchip,rk3528-pinctrl";
+ rockchip,grf = <&ioc_grf>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio0: gpio@ff610000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xff610000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 0 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio@ffaf0000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xffaf0000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 32 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@ffb00000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xffb00000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 64 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@ffb10000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xffb10000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 96 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@ffb20000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xffb20000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 128 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
@@ -866,74 +934,6 @@ dmac: dma-controller@ffd60000 {
#dma-cells = <1>;
arm,pl330-periph-burst;
};
-
- pinctrl: pinctrl {
- compatible = "rockchip,rk3528-pinctrl";
- rockchip,grf = <&ioc_grf>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- gpio0: gpio@ff610000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xff610000 0x0 0x200>;
- clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
- interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pinctrl 0 0 32>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio1: gpio@ffaf0000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xffaf0000 0x0 0x200>;
- clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
- interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pinctrl 0 32 32>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio2: gpio@ffb00000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xffb00000 0x0 0x200>;
- clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
- interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pinctrl 0 64 32>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio3: gpio@ffb10000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xffb10000 0x0 0x200>;
- clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
- interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pinctrl 0 96 32>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio4: gpio@ffb20000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xffb20000 0x0 0x200>;
- clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
- interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pinctrl 0 128 32>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
- };
};
};
--
2.47.2
next prev parent reply other threads:[~2025-05-18 22:05 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-18 22:04 [PATCH 0/6] Fix some warnings about PCIe and pinctrl on RK3528/RK3562/RK3576 Heiko Stuebner
2025-05-18 22:04 ` [PATCH 1/6] arm64: dts: rockchip: fix rk3576 pcie unit addresses Heiko Stuebner
2025-05-18 22:04 ` [PATCH 2/6] arm64: dts: rockchip: move rk3576 pinctrl node outside the soc node Heiko Stuebner
2025-05-18 22:04 ` [PATCH 3/6] arm64: dts: rockchip: remove a double-empty line from rk3576 core dtsi Heiko Stuebner
2025-05-18 22:04 ` Heiko Stuebner [this message]
2025-05-18 22:04 ` [PATCH 5/6] arm64: dts: rockchip: fix rk3562 pcie unit addresses Heiko Stuebner
2025-05-18 22:04 ` [PATCH 6/6] arm64: dts: rockchip: move rk3562 pinctrl node outside the soc node Heiko Stuebner
2025-05-20 19:09 ` [PATCH 0/6] Fix some warnings about PCIe and pinctrl on RK3528/RK3562/RK3576 Heiko Stuebner
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