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From: Ard Biesheuvel <ardb+git@google.com>
To: linux-kernel@vger.kernel.org
Cc: x86@kernel.org, Ard Biesheuvel <ardb@kernel.org>,
	Ingo Molnar <mingo@kernel.org>,
	 Linus Torvalds <torvalds@linux-foundation.org>,
	Brian Gerst <brgerst@gmail.com>,
	 "Kirill A. Shutemov" <kirill@shutemov.name>,
	Borislav Petkov <bp@alien8.de>
Subject: [PATCH v5 7/7] x86/boot: Remove KASAN workaround for 4/5 level paging switch
Date: Tue, 20 May 2025 12:41:46 +0200	[thread overview]
Message-ID: <20250520104138.2734372-16-ardb+git@google.com> (raw)
In-Reply-To: <20250520104138.2734372-9-ardb+git@google.com>

From: Ard Biesheuvel <ardb@kernel.org>

pgtable_l5_enabled() is no longer based on a CPU feature bit that might
change values and confuse KASAN, so we no longer need to disable it
temporarily.

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
---
 arch/x86/kernel/alternative.c | 12 ------------
 1 file changed, 12 deletions(-)

diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c
index f3c68b586a95..e39823d8d1ae 100644
--- a/arch/x86/kernel/alternative.c
+++ b/arch/x86/kernel/alternative.c
@@ -589,16 +589,6 @@ void __init_or_module noinline apply_alternatives(struct alt_instr *start,
 
 	DPRINTK(ALT, "alt table %px, -> %px", start, end);
 
-	/*
-	 * KASAN_SHADOW_START is defined using
-	 * cpu_feature_enabled(X86_FEATURE_LA57) and is therefore patched here.
-	 * During the process, KASAN becomes confused seeing partial LA57
-	 * conversion and triggers a false-positive out-of-bound report.
-	 *
-	 * Disable KASAN until the patching is complete.
-	 */
-	kasan_disable_current();
-
 	/*
 	 * The scan order should be from start to end. A later scanned
 	 * alternative code can overwrite previously scanned alternative code.
@@ -666,8 +656,6 @@ void __init_or_module noinline apply_alternatives(struct alt_instr *start,
 
 		text_poke_early(instr, insn_buff, insn_buff_sz);
 	}
-
-	kasan_enable_current();
 }
 
 static inline bool is_jcc32(struct insn *insn)
-- 
2.49.0.1101.gccaa498523-goog


      parent reply	other threads:[~2025-05-20 10:42 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-20 10:41 [PATCH v5 0/7] x86: Robustify pgtable_l5_enabled() Ard Biesheuvel
2025-05-20 10:41 ` [PATCH v5 1/7] x86/mm: Decouple MAX_PHYSMEM_BITS from LA57 state Ard Biesheuvel
2025-05-20 10:59   ` Kirill A. Shutemov
2025-05-20 11:27     ` Ard Biesheuvel
2025-05-20 10:41 ` [PATCH v5 2/7] x86/mm: Use a single cache hot per-CPU variable to record pgdir_shift Ard Biesheuvel
2025-05-20 11:03   ` Kirill A. Shutemov
2025-05-20 11:28     ` Ard Biesheuvel
2025-05-20 14:35       ` Borislav Petkov
2025-05-20 17:03         ` Ard Biesheuvel
2025-05-20 17:38           ` Borislav Petkov
2025-05-20 17:46             ` Ard Biesheuvel
2025-05-20 18:01               ` Borislav Petkov
2025-05-20 18:28                 ` Linus Torvalds
2025-05-20 18:35                   ` Borislav Petkov
2025-05-20 19:49                   ` Ard Biesheuvel
2025-05-20 10:41 ` [PATCH v5 3/7] x86/mm: Define PTRS_PER_P4D in terms of pgdir_shift() Ard Biesheuvel
2025-05-20 11:08   ` Kirill A. Shutemov
2025-05-20 11:29     ` Ard Biesheuvel
2025-05-20 10:41 ` [PATCH v5 4/7] x86/mm: Derive pgtable_l5_enabled() from pgdir_shift() Ard Biesheuvel
2025-05-20 10:41 ` [PATCH v5 5/7] x86/boot: Drop USE_EARLY_PGTABLE_L5 definitions Ard Biesheuvel
2025-05-20 10:41 ` [PATCH v5 6/7] x86/boot: Drop 5-level paging related global variable Ard Biesheuvel
2025-05-20 10:41 ` Ard Biesheuvel [this message]

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