From: Rik van Riel <riel@surriel.com>
To: linux-kernel@vger.kernel.org
Cc: kernel-team@meta.com, dave.hansen@linux.intel.com,
luto@kernel.org, peterz@infradead.org, bp@alien8.de,
x86@kernel.org, yu-cheng.yu@intel.com
Subject: [PATCH 0/3] TLB flush fixes
Date: Mon, 2 Jun 2025 09:30:54 -0400 [thread overview]
Message-ID: <20250602133402.3385163-1-riel@surriel.com> (raw)
Some TLB flush fixes extracted from, or encountered while developing
the Intel RAR functionality.
1) Fix a potential overflow in user_pcid_flush_mask.
I do not think anybody is hitting this in practice,
but they could if they wanted to.
2) Change the early boot initialized value of invlpgb_count_max
to 1, to avoid an infinite loop when...
3) Having cpa_flush() call flush_kernel_range(), which results
in the INVPLGB code being called very early at boot time.
next reply other threads:[~2025-06-02 13:34 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-02 13:30 Rik van Riel [this message]
2025-06-02 13:30 ` [PATCH 1/3] x86/mm: Fix potential overflow in user_pcid_flush_mask Rik van Riel
2025-06-02 16:55 ` Dave Hansen
2025-06-03 21:20 ` Rik van Riel
2025-06-03 21:33 ` Dave Hansen
2025-06-02 13:30 ` [PATCH 2/3] x86/mm: Fix early boot use of INVPLGB Rik van Riel
2025-06-02 17:21 ` Dave Hansen
2025-06-02 13:30 ` [PATCH 3/3] x86/mm: Change cpa_flush() to call flush_kernel_range() directly Rik van Riel
2025-06-02 17:22 ` Dave Hansen
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