Re: [Patch v4 07/13] perf/x86/intel: Allocate arch-PEBS buffer and initialize PEBS_BASE MSR

[Peter Zijlstra <peterz@infradead.org>]

On Fri, Jun 20, 2025 at 10:39:03AM +0000, Dapeng Mi wrote:

> diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
> index b6eface4dccd..72b925b8c482 100644
> --- a/arch/x86/events/intel/ds.c
> +++ b/arch/x86/events/intel/ds.c
> @@ -625,13 +625,22 @@ static int alloc_pebs_buffer(int cpu)
>  	int max, node = cpu_to_node(cpu);
>  	void *buffer, *insn_buff, *cea;
>  
> -	if (!x86_pmu.ds_pebs)
> +	if (!intel_pmu_has_pebs())
>  		return 0;
>  
> -	buffer = dsalloc_pages(bsiz, GFP_KERNEL, cpu);
> +	/*
> +	 * alloc_pebs_buffer() could be called by init_arch_pebs_buf_on_cpu()
> +	 * which is in atomic context.
> +	 */
> +	buffer = dsalloc_pages(bsiz, preemptible() ? GFP_KERNEL : GFP_ATOMIC, cpu);
>  	if (unlikely(!buffer))
>  		return -ENOMEM;

Here we go again.. that is CPU_STARTING context, that has IRQs disabled
and as such no allocation is allowed. Not even GFP_ATOMIC -- this will
break PREEMPT_RT.