[PATCH v1 0/3] Workarounds and optimizations for Neoverse-V3AE

[PATCH v1 0/3] Workarounds and optimizations for Neoverse-V3AE

[Ryan Roberts]

Hi All,

I know it's late in the cycle, but I thought I'd try my luck at sneaking this
in.

Neoverse-V3AE has a different MIDR value to Neoverse-V3, but qualifies for the
same workarounds and optimizations ("SSBS not fully self-synchronizing" and
BBML2_NOABORT) so this just adds Neoverse-V3AE wherever Neoverse-V3 appears.
Details in the commits.

The last patch adds Neoverse-3VAE to the BBML2_NOABORT allow list. That will
conflict with the patch you have already queued to add AmpereOne, and with the
patch you said you would do to remove X4. But this is a one-liner so trivial to
resolve.

Applies on v6.17-rc5.

Thanks,
Ryan


Mark Rutland (2):
  arm64: cputype: Add Neoverse-V3AE definitions
  arm64: errata: Apply workarounds for Neoverse-V3AE

Ryan Roberts (1):
  arm64: cpufeature: add Neoverse-V3AE to BBML2 allow list

 Documentation/arch/arm64/silicon-errata.rst | 2 ++
 arch/arm64/Kconfig                          | 1 +
 arch/arm64/include/asm/cputype.h            | 2 ++
 arch/arm64/kernel/cpu_errata.c              | 1 +
 arch/arm64/kernel/cpufeature.c              | 1 +
 5 files changed, 7 insertions(+)

--
2.43.0

[PATCH v1 1/3] arm64: cputype: Add Neoverse-V3AE definitions

[Ryan Roberts]

From: Mark Rutland <mark.rutland@arm.com>

Add cputype definitions for Neoverse-V3AE. These will be used for errata
detection in subsequent patches.

These values can be found in the Neoverse-V3AE TRM:

  https://developer.arm.com/documentation/SDEN-2615521/9-0/

... in section A.6.1 ("MIDR_EL1, Main ID Register").

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: James Morse <james.morse@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Ryan Roberts <ryan.roberts@arm.com>
---
 arch/arm64/include/asm/cputype.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 661735616787..eaec55dd3dbe 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -93,6 +93,7 @@
 #define ARM_CPU_PART_NEOVERSE_V2	0xD4F
 #define ARM_CPU_PART_CORTEX_A720	0xD81
 #define ARM_CPU_PART_CORTEX_X4		0xD82
+#define ARM_CPU_PART_NEOVERSE_V3AE	0xD83
 #define ARM_CPU_PART_NEOVERSE_V3	0xD84
 #define ARM_CPU_PART_CORTEX_X925	0xD85
 #define ARM_CPU_PART_CORTEX_A725	0xD87
@@ -182,6 +183,7 @@
 #define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2)
 #define MIDR_CORTEX_A720 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720)
 #define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4)
+#define MIDR_NEOVERSE_V3AE	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3AE)
 #define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)
 #define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925)
 #define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725)
-- 
2.43.0

[PATCH v1 2/3] arm64: errata: Apply workarounds for Neoverse-V3AE

[Ryan Roberts]

From: Mark Rutland <mark.rutland@arm.com>

Neoverse-V3AE is also affected by erratum #3312417, as described in its
Software Developer Errata Notice (SDEN) document:

  Neoverse V3AE (MP172) SDEN v9.0, erratum 3312417
  https://developer.arm.com/documentation/SDEN-2615521/9-0/

Enable the workaround for Neoverse-V3AE, and document this.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: James Morse <james.morse@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Ryan Roberts <ryan.roberts@arm.com>
---
 Documentation/arch/arm64/silicon-errata.rst | 2 ++
 arch/arm64/Kconfig                          | 1 +
 arch/arm64/kernel/cpu_errata.c              | 1 +
 3 files changed, 4 insertions(+)

diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst
index b18ef4064bc0..a7ec57060f64 100644
--- a/Documentation/arch/arm64/silicon-errata.rst
+++ b/Documentation/arch/arm64/silicon-errata.rst
@@ -200,6 +200,8 @@ stable kernels.
 +----------------+-----------------+-----------------+-----------------------------+
 | ARM            | Neoverse-V3     | #3312417        | ARM64_ERRATUM_3194386       |
 +----------------+-----------------+-----------------+-----------------------------+
+| ARM            | Neoverse-V3AE   | #3312417        | ARM64_ERRATUM_3194386       |
++----------------+-----------------+-----------------+-----------------------------+
 | ARM            | MMU-500         | #841119,826419  | ARM_SMMU_MMU_500_CPRE_ERRATA|
 |                |                 | #562869,1047329 |                             |
 +----------------+-----------------+-----------------+-----------------------------+
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index e9bbfacc35a6..93f391e67af1 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -1138,6 +1138,7 @@ config ARM64_ERRATUM_3194386
 	  * ARM Neoverse-V1 erratum 3324341
 	  * ARM Neoverse V2 erratum 3324336
 	  * ARM Neoverse-V3 erratum 3312417
+	  * ARM Neoverse-V3AE erratum 3312417
 
 	  On affected cores "MSR SSBS, #0" instructions may not affect
 	  subsequent speculative instructions, which may permit unexepected
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index 59d723c9ab8f..21f86c160aab 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -545,6 +545,7 @@ static const struct midr_range erratum_spec_ssbs_list[] = {
 	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1),
 	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2),
 	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3),
+	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3AE),
 	{}
 };
 #endif
-- 
2.43.0

[PATCH v1 3/3] arm64: cpufeature: add Neoverse-V3AE to BBML2 allow list

[Ryan Roberts]

Neoverse-V3AE advertises support for BBML2 and is known to not raise
conflict aborts. So add it to the BBML2_NOABORT allow list.

However, just like Neoverse-V3, Neoverse-V3AE r0p0 and r0p1 suffer from
erratum #3053180, for which the workaround is to always observe
break-before-make requirements for affected revisions. Therefore only
add to the allow list from r0p2 onwards.

For more details see Software Developer Errata Notice (SDEN) document:
    Neoverse V3AE (MP172) SDEN v9.0, erratum 3053180
    https://developer.arm.com/documentation/SDEN-2615521/9-0/

Signed-off-by: Ryan Roberts <ryan.roberts@arm.com>
---
 arch/arm64/kernel/cpufeature.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index ef269a5a37e1..61180b211293 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -2235,6 +2235,7 @@ static bool has_bbml2_noabort(const struct arm64_cpu_capabilities *caps, int sco
 	static const struct midr_range supports_bbml2_noabort_list[] = {
 		MIDR_REV_RANGE(MIDR_CORTEX_X4, 0, 3, 0xf),
 		MIDR_REV_RANGE(MIDR_NEOVERSE_V3, 0, 2, 0xf),
+		MIDR_REV_RANGE(MIDR_NEOVERSE_V3AE, 0, 2, 0xf),
 		{}
 	};
 
-- 
2.43.0

Re: [PATCH v1 0/3] Workarounds and optimizations for Neoverse-V3AE

[Will Deacon]

On Fri, 19 Sep 2025 15:58:27 +0100, Ryan Roberts wrote:
> I know it's late in the cycle, but I thought I'd try my luck at sneaking this
> in.
> 
> Neoverse-V3AE has a different MIDR value to Neoverse-V3, but qualifies for the
> same workarounds and optimizations ("SSBS not fully self-synchronizing" and
> BBML2_NOABORT) so this just adds Neoverse-V3AE wherever Neoverse-V3 appears.
> Details in the commits.
> 
> [...]

Applied to arm64 (for-next/cpufeature), thanks!

[1/3] arm64: cputype: Add Neoverse-V3AE definitions
      https://git.kernel.org/arm64/c/3bbf004c4808
[2/3] arm64: errata: Apply workarounds for Neoverse-V3AE
      https://git.kernel.org/arm64/c/0c33aa1804d1
[3/3] arm64: cpufeature: add Neoverse-V3AE to BBML2 allow list
      https://git.kernel.org/arm64/c/8fca3852e33d

Cheers,
-- 
Will

https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev

Re: [PATCH v1 0/3] Workarounds and optimizations for Neoverse-V3AE

[Ryan Roberts]

On 22/09/2025 14:14, Will Deacon wrote:
> On Fri, 19 Sep 2025 15:58:27 +0100, Ryan Roberts wrote:
>> I know it's late in the cycle, but I thought I'd try my luck at sneaking this
>> in.
>>
>> Neoverse-V3AE has a different MIDR value to Neoverse-V3, but qualifies for the
>> same workarounds and optimizations ("SSBS not fully self-synchronizing" and
>> BBML2_NOABORT) so this just adds Neoverse-V3AE wherever Neoverse-V3 appears.
>> Details in the commits.
>>
>> [...]
> 
> Applied to arm64 (for-next/cpufeature), thanks!
> 
> [1/3] arm64: cputype: Add Neoverse-V3AE definitions
>       https://git.kernel.org/arm64/c/3bbf004c4808
> [2/3] arm64: errata: Apply workarounds for Neoverse-V3AE
>       https://git.kernel.org/arm64/c/0c33aa1804d1
> [3/3] arm64: cpufeature: add Neoverse-V3AE to BBML2 allow list
>       https://git.kernel.org/arm64/c/8fca3852e33d
> 
> Cheers,

Thank you!