[PATCH] RISC-V: Don't print details of CPUs disabled in DT

[PATCH] RISC-V: Don't print details of CPUs disabled in DT

[Anup Patel]

Early boot stages may disable CPU DT nodes for unavailable
CPUs based on SKU, pinstraps, eFuse, etc. Currently, the
riscv_early_of_processor_hartid() prints details of a CPU
if it is disabled in DT which has no value and gives a
false impression to the users that there some issue with
the CPU.

Fixes: e3d794d555cd ("riscv: treat cpu devicetree nodes without status as enabled")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 arch/riscv/kernel/cpu.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index f6b13e9f5e6c..3dbc8cc557dd 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -62,10 +62,8 @@ int __init riscv_early_of_processor_hartid(struct device_node *node, unsigned lo
 		return -ENODEV;
 	}
 
-	if (!of_device_is_available(node)) {
-		pr_info("CPU with hartid=%lu is not available\n", *hart);
+	if (!of_device_is_available(node))
 		return -ENODEV;
-	}
 
 	if (of_property_read_string(node, "riscv,isa-base", &isa))
 		goto old_interface;
-- 
2.43.0

Re: [PATCH] RISC-V: Don't print details of CPUs disabled in DT

[Andrew Jones]

On Tue, Oct 14, 2025 at 10:00:09PM +0530, Anup Patel wrote:
> Early boot stages may disable CPU DT nodes for unavailable
> CPUs based on SKU, pinstraps, eFuse, etc. Currently, the
> riscv_early_of_processor_hartid() prints details of a CPU
> if it is disabled in DT which has no value and gives a
> false impression to the users that there some issue with
> the CPU.
> 
> Fixes: e3d794d555cd ("riscv: treat cpu devicetree nodes without status as enabled")
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
>  arch/riscv/kernel/cpu.c | 4 +---
>  1 file changed, 1 insertion(+), 3 deletions(-)
> 
> diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
> index f6b13e9f5e6c..3dbc8cc557dd 100644
> --- a/arch/riscv/kernel/cpu.c
> +++ b/arch/riscv/kernel/cpu.c
> @@ -62,10 +62,8 @@ int __init riscv_early_of_processor_hartid(struct device_node *node, unsigned lo
>  		return -ENODEV;
>  	}
>  
> -	if (!of_device_is_available(node)) {
> -		pr_info("CPU with hartid=%lu is not available\n", *hart);
> +	if (!of_device_is_available(node))
>  		return -ENODEV;
> -	}
>  
>  	if (of_property_read_string(node, "riscv,isa-base", &isa))
>  		goto old_interface;
> -- 
> 2.43.0
>

Maybe we should keep the message as a pr_debug()?

Otherwise,

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

Re: [PATCH] RISC-V: Don't print details of CPUs disabled in DT

[Conor Dooley]

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On Tue, Oct 14, 2025 at 12:50:11PM -0500, Andrew Jones wrote:
> On Tue, Oct 14, 2025 at 10:00:09PM +0530, Anup Patel wrote:
> > Early boot stages may disable CPU DT nodes for unavailable
> > CPUs based on SKU, pinstraps, eFuse, etc. Currently, the
> > riscv_early_of_processor_hartid() prints details of a CPU
> > if it is disabled in DT which has no value and gives a
> > false impression to the users that there some issue with
> > the CPU.
> > 
> > Fixes: e3d794d555cd ("riscv: treat cpu devicetree nodes without status as enabled")
> > Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> > ---
> >  arch/riscv/kernel/cpu.c | 4 +---
> >  1 file changed, 1 insertion(+), 3 deletions(-)
> > 
> > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
> > index f6b13e9f5e6c..3dbc8cc557dd 100644
> > --- a/arch/riscv/kernel/cpu.c
> > +++ b/arch/riscv/kernel/cpu.c
> > @@ -62,10 +62,8 @@ int __init riscv_early_of_processor_hartid(struct device_node *node, unsigned lo
> >  		return -ENODEV;
> >  	}
> >  
> > -	if (!of_device_is_available(node)) {
> > -		pr_info("CPU with hartid=%lu is not available\n", *hart);
> > +	if (!of_device_is_available(node))
> >  		return -ENODEV;
> > -	}
> >  
> >  	if (of_property_read_string(node, "riscv,isa-base", &isa))
> >  		goto old_interface;
> > -- 
> > 2.43.0
> >
> 
> Maybe we should keep the message as a pr_debug()?

I don't even know if that really has any value, there's plenty of places
in userspace to get access to what CPUs are enabled and having no CPUs
triggers a BUG().
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

> 
> Otherwise,
> 
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

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Re: [PATCH] RISC-V: Don't print details of CPUs disabled in DT

[patchwork-bot+linux-riscv]

Hello:

This patch was applied to riscv/linux.git (fixes)
by Paul Walmsley <pjw@kernel.org>:

On Tue, 14 Oct 2025 22:00:09 +0530 you wrote:
> Early boot stages may disable CPU DT nodes for unavailable
> CPUs based on SKU, pinstraps, eFuse, etc. Currently, the
> riscv_early_of_processor_hartid() prints details of a CPU
> if it is disabled in DT which has no value and gives a
> false impression to the users that there some issue with
> the CPU.
> 
> [...]

Here is the summary with links:
  - RISC-V: Don't print details of CPUs disabled in DT
    https://git.kernel.org/riscv/c/d2721bb165b3

You are awesome, thank you!
-- 
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