From: Anshuman Khandual <anshuman.khandual@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: Anshuman Khandual <anshuman.khandual@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>,
Ryan Roberts <ryan.roberts@arm.com>,
Ard Biesheuvel <ardb@kernel.org>,
linux-kernel@vger.kernel.org
Subject: [PATCH 2/6] arm64/mm: Directly use TTBRx_EL1_CnP
Date: Mon, 3 Nov 2025 05:26:14 +0000 [thread overview]
Message-ID: <20251103052618.586763-3-anshuman.khandual@arm.com> (raw)
In-Reply-To: <20251103052618.586763-1-anshuman.khandual@arm.com>
Replace all TTBR_CNP_BIT macro instances with TTBRx_EL1_CNP_BIT which
is a standard field from tools sysreg format. No functional change.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
arch/arm64/kernel/mte.c | 4 ++--
arch/arm64/mm/context.c | 2 +-
arch/arm64/mm/mmu.c | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/kernel/mte.c b/arch/arm64/kernel/mte.c
index 43f7a2f39403..ba2e3e9d1f73 100644
--- a/arch/arm64/kernel/mte.c
+++ b/arch/arm64/kernel/mte.c
@@ -315,8 +315,8 @@ void mte_cpu_setup(void)
* CnP is not a boot feature so MTE gets enabled before CnP, but let's
* make sure that is the case.
*/
- BUG_ON(read_sysreg(ttbr0_el1) & TTBR_CNP_BIT);
- BUG_ON(read_sysreg(ttbr1_el1) & TTBR_CNP_BIT);
+ BUG_ON(read_sysreg(ttbr0_el1) & TTBRx_EL1_CnP);
+ BUG_ON(read_sysreg(ttbr1_el1) & TTBRx_EL1_CnP);
/* Normal Tagged memory type at the corresponding MAIR index */
sysreg_clear_set(mair_el1,
diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c
index 718c495832d0..0f4a28b87469 100644
--- a/arch/arm64/mm/context.c
+++ b/arch/arm64/mm/context.c
@@ -354,7 +354,7 @@ void cpu_do_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm)
/* Skip CNP for the reserved ASID */
if (system_supports_cnp() && asid)
- ttbr0 |= TTBR_CNP_BIT;
+ ttbr0 |= TTBRx_EL1_CnP;
/* SW PAN needs a copy of the ASID in TTBR0 for entry */
if (IS_ENABLED(CONFIG_ARM64_SW_TTBR0_PAN))
diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
index b8d37eb037fc..e80bb623ef53 100644
--- a/arch/arm64/mm/mmu.c
+++ b/arch/arm64/mm/mmu.c
@@ -2084,7 +2084,7 @@ void __cpu_replace_ttbr1(pgd_t *pgdp, bool cnp)
phys_addr_t ttbr1 = phys_to_ttbr(virt_to_phys(pgdp));
if (cnp)
- ttbr1 |= TTBR_CNP_BIT;
+ ttbr1 |= TTBRx_EL1_CnP;
replace_phys = (void *)__pa_symbol(idmap_cpu_replace_ttbr1);
--
2.30.2
next prev parent reply other threads:[~2025-11-03 5:26 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-03 5:26 [PATCH 0/6] arm64/mm: TTBRx_EL1 related changes Anshuman Khandual
2025-11-03 5:26 ` [PATCH 1/6] arm64/mm: Directly use TTBRx_EL1_ASID_MASK Anshuman Khandual
2025-11-03 5:26 ` Anshuman Khandual [this message]
2025-11-03 5:26 ` [PATCH 3/6] arm64/mm: Represent TTBR_BADDR_MASK_52 with TTBRx_EL1_BADDR_MASK Anshuman Khandual
2025-11-03 5:26 ` [PATCH 4/6] arm64/mm: Ensure correct 48 bit PA gets into TTBRx_EL1 Anshuman Khandual
2025-11-04 15:17 ` Mark Rutland
2025-11-05 3:35 ` Anshuman Khandual
2025-11-03 5:26 ` [PATCH 5/6] arm64/mm: Describe 52 PA folding " Anshuman Khandual
2025-11-03 5:26 ` [PATCH 6/6] arm64/mm: Describe TTBR1_BADDR_4852_OFFSET Anshuman Khandual
2025-11-13 9:18 ` [PATCH 0/6] arm64/mm: TTBRx_EL1 related changes Anshuman Khandual
2025-11-14 9:55 ` Mark Rutland
2025-11-19 1:07 ` Anshuman Khandual
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