From: Leo Yan <leo.yan@arm.com>
To: Yingchao Deng <yingchao.deng@oss.qualcomm.com>,
Mike Leach <mike.leach@linaro.org>,
James Clark <james.clark@linaro.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Tingwei Zhang <tingwei.zhang@oss.qualcomm.com>,
quic_yingdeng@quicinc.com, coresight@lists.linaro.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
Jinlong Mao <jinlong.mao@oss.qualcomm.com>,
Mao Jinlong <quic_jinlmao@quicinc.com>
Subject: Re: [PATCH v6 2/2] coresight: cti: Add Qualcomm extended CTI support
Date: Thu, 4 Dec 2025 08:38:02 +0000 [thread overview]
Message-ID: <20251204083802.GI724103@e132581.arm.com> (raw)
In-Reply-To: <20251203182944.GG724103@e132581.arm.com>
On Wed, Dec 03, 2025 at 06:29:44PM +0000, Coresight ML wrote:
[...]
> > +/* Read registers with power check only (no enable check). */
> > +static ssize_t coresight_cti_reg_show(struct device *dev,
> > + struct device_attribute *attr, char *buf)
> > +{
> > + struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > + struct cs_off_attribute *cti_attr = container_of(attr, struct cs_off_attribute, attr);
> > + u32 idx, val = 0;
> > +
> > + pm_runtime_get_sync(dev->parent);
> > + raw_spin_lock(&drvdata->spinlock);
> > + idx = drvdata->config.ext_reg_sel;
> > + if (drvdata->config.hw_powered) {
> > + switch (cti_attr->off) {
> > + case INDEX_CTITRIGINSTATUS:
> > + case INDEX_CTITRIGOUTSTATUS:
> > + case INDEX_ITTRIGINACK:
> > + case INDEX_ITTRIGOUT:
> > + case INDEX_ITTRIGOUTACK:
> > + case INDEX_ITTRIGIN:
I read again and now I understand why you need "config.ext_reg_sel"
as an index for these expending registers.
I think you should extend attrs for the new adding registers:
static struct attribute *coresight_cti_regs_attrs[] = {
...
coresight_cti_reg(triginstatus, CTITRIGINSTATUS),
/* Qcom CTI only for triginstatus1/2/3 */
coresight_cti_reg(triginstatus1, CTITRIGINSTATUS + 0x4),
coresight_cti_reg(triginstatus2, CTITRIGINSTATUS + 0x8),
coresight_cti_reg(triginstatus3, CTITRIGINSTATUS + 0xc),
...
}
Then, you can add a is_visible() in coresight_cti_regs_group:
static umode_t coresight_cti_regs_is_visible(struct kobject *kobj,
struct attribute *attr, int n)
{
struct device *dev = container_of(kobj, struct device, kobj);
struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent);
/* Mute QCOM CTI registers for standard CTI module */
if (!drvdata->is_qcom_cti) {
if (attr == &triginstatus1.attr ||
attr == &triginstatus2.attr ||
attr == &triginstatus3.attr)
return 0;
}
return attr->mode;
}
static const struct attribute_group coresight_cti_regs_group = {
.attrs = coresight_cti_regs_attrs,
.name = "regs",
.is_visible = coresight_cti_regs_is_visible,
};
Thanks,
Leo
next prev parent reply other threads:[~2025-12-04 8:38 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-02 6:42 [PATCH v6 0/2] Add Qualcomm extended CTI support Yingchao Deng
2025-12-02 6:42 ` [PATCH v6 1/2] coresight: cti: Convert trigger usage fields to dynamic bitmaps and arrays Yingchao Deng
2025-12-04 9:54 ` Mike Leach
2025-12-02 6:42 ` [PATCH v6 2/2] coresight: cti: Add Qualcomm extended CTI support Yingchao Deng
2025-12-03 18:29 ` Leo Yan
2025-12-04 8:38 ` Leo Yan [this message]
2025-12-04 9:04 ` Mike Leach
2025-12-04 10:02 ` Leo Yan
2025-12-04 9:07 ` Mike Leach
2025-12-04 10:31 ` Leo Yan
2025-12-04 16:17 ` Mike Leach
2025-12-05 10:04 ` Leo Yan
2025-12-08 14:47 ` Mike Leach
2025-12-09 8:16 ` Yingchao Deng
2025-12-09 9:40 ` Jie Gan
2025-12-09 11:03 ` Jie Gan
2025-12-09 12:42 ` Yingchao Deng (Consultant)
2025-12-09 12:19 ` Leo Yan
2025-12-09 12:51 ` Yingchao Deng (Consultant)
2025-12-09 14:24 ` Leo Yan
2025-12-09 13:59 ` Leo Yan
2025-12-04 9:15 ` Mike Leach
2025-12-04 10:47 ` Leo Yan
2025-12-04 15:07 ` Mike Leach
2025-12-05 10:27 ` Leo Yan
2025-12-08 14:25 ` Mike Leach
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