From: Leo Yan <leo.yan@arm.com>
To: Mike Leach <mike.leach@linaro.org>
Cc: Yingchao Deng <yingchao.deng@oss.qualcomm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
James Clark <james.clark@linaro.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Tingwei Zhang <tingwei.zhang@oss.qualcomm.com>,
quic_yingdeng@quicinc.com, coresight@lists.linaro.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
Jinlong Mao <jinlong.mao@oss.qualcomm.com>,
Mao Jinlong <quic_jinlmao@quicinc.com>
Subject: Re: [PATCH v6 2/2] coresight: cti: Add Qualcomm extended CTI support
Date: Tue, 9 Dec 2025 13:59:07 +0000 [thread overview]
Message-ID: <20251209135907.GU724103@e132581.arm.com> (raw)
In-Reply-To: <CAJ9a7Vg9Efi-5eecfiUF82_Qq8Jg9imN5q1-VKYZoPVUxNpjhA@mail.gmail.com>
Hi Mike,
On Mon, Dec 08, 2025 at 02:47:21PM +0000, Mike Leach wrote:
[...]
> > I tested locally and did not see the GCC complaint for this approach.
> > And this is a global structure with about 16KiB (~4K items x
>
> Which is precisely the issue - why use 16k bytes of space when a pair
> of indexed tables will use 21 x 32bit locations per table -> 168 bytes
> - 100x smaller!
>
> This space matters little to high end server systems but is much more
> important in smaller embedded systems.
For the concern of performance and footprint, my approach can
avoid any conversion for standard registers, we end up need to
convert registers for non-standard registers anyway.
I understand your concern for using an array for conversion, this is
cost 16KiB memory but this can benefit a bit performance. It is a
trade-off between memory and speed. As said, we can use a static
function for register conversion, the side effect is this might cause
more time.
Given the CTI MMIO register access, I don't think an extra branch
instruction (checking the flag) would cause significant panelty,
given the flag is set once at init and never changed afterwards.
> Moreover the table + inline helper is more efficient at extracting the
> correct offset value. The helper is a simple de-reference - whereas
> the helper functions you suggest require the code to make the
> comparison at every register access.
> The "if qcom ..." may be contained in one place in the source code,
> but is called and executed for every access.
>
> Why add inefficiencies, either in footprint or execution?
This is about how we design a driver that supports both a standard IP
and non-standard implementations.
Because the standard IP is well defined, its register layout should be
the default; it keeps the code simple and makes future CTI extensions
easier. For non-standard IPs, we only apply the register translations
needed.
TBH, the optimization topic is a bit over design for me now. The CTI
module is configured once and remains untouched until it is disabled,
so it is not a hot path.
Thanks,
Leo
next prev parent reply other threads:[~2025-12-09 13:59 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-02 6:42 [PATCH v6 0/2] Add Qualcomm extended CTI support Yingchao Deng
2025-12-02 6:42 ` [PATCH v6 1/2] coresight: cti: Convert trigger usage fields to dynamic bitmaps and arrays Yingchao Deng
2025-12-04 9:54 ` Mike Leach
2025-12-02 6:42 ` [PATCH v6 2/2] coresight: cti: Add Qualcomm extended CTI support Yingchao Deng
2025-12-03 18:29 ` Leo Yan
2025-12-04 8:38 ` Leo Yan
2025-12-04 9:04 ` Mike Leach
2025-12-04 10:02 ` Leo Yan
2025-12-04 9:07 ` Mike Leach
2025-12-04 10:31 ` Leo Yan
2025-12-04 16:17 ` Mike Leach
2025-12-05 10:04 ` Leo Yan
2025-12-08 14:47 ` Mike Leach
2025-12-09 8:16 ` Yingchao Deng
2025-12-09 9:40 ` Jie Gan
2025-12-09 11:03 ` Jie Gan
2025-12-09 12:42 ` Yingchao Deng (Consultant)
2025-12-09 12:19 ` Leo Yan
2025-12-09 12:51 ` Yingchao Deng (Consultant)
2025-12-09 14:24 ` Leo Yan
2025-12-09 13:59 ` Leo Yan [this message]
2025-12-04 9:15 ` Mike Leach
2025-12-04 10:47 ` Leo Yan
2025-12-04 15:07 ` Mike Leach
2025-12-05 10:27 ` Leo Yan
2025-12-08 14:25 ` Mike Leach
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