From: "Rob Herring (Arm)" <robh@kernel.org>
To: soc@kernel.org, Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH] arm64: dts: cavium: thunder-88xx: Add missing PL011 "uartclk"
Date: Tue, 16 Dec 2025 12:01:37 -0600 [thread overview]
Message-ID: <20251216180136.2794105-2-robh@kernel.org> (raw)
The PL011 IP has 2 clock inputs for UART core/baud and APB bus. The
Thunder2 SoC is missing the core "uartclk". In this case, the Linux
driver uses single clock for both clock inputs. Let's assume that's how
the h/w is wired and make the DT reflect that.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
---
SoC maintainers, Please take this directly.
arch/arm64/boot/dts/cavium/thunder-88xx.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi
index cc860a80af51..70430cb2b053 100644
--- a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi
+++ b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi
@@ -401,16 +401,16 @@ uaa0: serial@87e024000000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x87e0 0x24000000 0x0 0x1000>;
interrupts = <1 21 4>;
- clocks = <&refclk50mhz>;
- clock-names = "apb_pclk";
+ clocks = <&refclk50mhz>, <&refclk50mhz>;
+ clock-names = "uartclk", "apb_pclk";
};
uaa1: serial@87e025000000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x87e0 0x25000000 0x0 0x1000>;
interrupts = <1 22 4>;
- clocks = <&refclk50mhz>;
- clock-names = "apb_pclk";
+ clocks = <&refclk50mhz>, <&refclk50mhz>;
+ clock-names = "uartclk", "apb_pclk";
};
};
};
--
2.51.0
next reply other threads:[~2025-12-16 18:01 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-16 18:01 Rob Herring (Arm) [this message]
2025-12-22 10:05 ` [PATCH] arm64: dts: cavium: thunder-88xx: Add missing PL011 "uartclk" Krzysztof Kozlowski
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