From: Jason Gunthorpe <jgg@ziepe.ca>
To: Dawei Li <dawei.li@linux.dev>
Cc: will@kernel.org, robin.murphy@arm.com, joro@8bytes.org,
linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev,
linux-kernel@vger.kernel.org, set_pte_at@outlook.com,
stable@vger.kernel.org
Subject: Re: [PATCH] iommu/arm-smmu-v3: Maintain valid access attributes for non-coherent SMMU
Date: Sun, 4 Jan 2026 20:02:29 -0400 [thread overview]
Message-ID: <20260105000229.GC125261@ziepe.ca> (raw)
In-Reply-To: <20260104133532.GA173992@wendao-VirtualBox>
> > /* DMA for "CMDQ MSI" which targets q->base_dma allocated by arm_smmu_init_one_queue() */
> >
> > > @@ -1612,11 +1624,18 @@ void arm_smmu_make_cdtable_ste(struct arm_smmu_ste *target,
> > > (cd_table->cdtab_dma & STRTAB_STE_0_S1CTXPTR_MASK) |
> > > FIELD_PREP(STRTAB_STE_0_S1CDMAX, cd_table->s1cdmax));
> > >
> > > + if (smmu_coherent(smmu)) {
> > > + val = FIELD_PREP(STRTAB_STE_1_S1CIR, STRTAB_STE_1_S1C_CACHE_WBRA) |
> > > + FIELD_PREP(STRTAB_STE_1_S1COR, STRTAB_STE_1_S1C_CACHE_WBRA) |
> > > + FIELD_PREP(STRTAB_STE_1_S1CSH, ARM_SMMU_SH_ISH);
> > > + } else {
> > > + val = FIELD_PREP(STRTAB_STE_1_S1CIR, STRTAB_STE_1_S1C_CACHE_NC) |
> > > + FIELD_PREP(STRTAB_STE_1_S1COR, STRTAB_STE_1_S1C_CACHE_NC) |
> > > + FIELD_PREP(STRTAB_STE_1_S1CSH, ARM_SMMU_SH_OSH);
> > > + }
> >
> > This one is "CD fetch" allocated by arm_smmu_alloc_cd_ptr()
> >
> > etc
> >
> > And note that the above will need this hunk too:
> >
> > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c
> > @@ -432,6 +432,14 @@ size_t arm_smmu_get_viommu_size(struct device *dev,
> > !(smmu->features & ARM_SMMU_FEAT_S2FWB))
> > return 0;
> >
> > + /*
> > + * When running non-coherent we can't suppot S2FWB since it will also
> > + * force a coherent CD fetch, aside from the question of what
> > + * S2FWB/CANWBS even does with non-coherent SMMUs.
> > + */
> > + if (!smmu_coherent(smmu))
> > + return 0;
>
> I was wondering why S2FWB can affect CD fetching before reading 13.8.
Yeah, that table is super useful
> + if (!fwb) {
> + val = FIELD_PREP(STRTAB_STE_1_S1CIR, STRTAB_STE_1_S1C_CACHE_NC) |
> + FIELD_PREP(STRTAB_STE_1_S1COR, STRTAB_STE_1_S1C_CACHE_NC) |
> + FIELD_PREP(STRTAB_STE_1_S1CSH, ARM_SMMU_SH_OSH);
> + } else {
> + dev_warn(&smmu->dev, "Inconsitency between COHACC & S2FWB\n");
> + /* FIX ME */
> + return;
I prefer we block it as I showed instead of printing a warning, cache
inconsistencies in virtualization can become security problems.
Though it is probably good to add a comment here about s2fwb also
Jason
next prev parent reply other threads:[~2026-01-05 0:02 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-29 0:23 [PATCH] iommu/arm-smmu-v3: Maintain valid access attributes for non-coherent SMMU Dawei Li
2026-01-02 18:41 ` Jason Gunthorpe
2026-01-04 13:35 ` Dawei Li
2026-01-05 0:02 ` Jason Gunthorpe [this message]
2026-01-05 13:33 ` Robin Murphy
2026-01-05 14:53 ` Jason Gunthorpe
2026-01-05 16:02 ` Robin Murphy
2026-01-05 18:54 ` Jason Gunthorpe
2026-01-20 12:14 ` Will Deacon
2026-01-20 13:11 ` Jason Gunthorpe
2026-01-05 15:46 ` Dawei Li
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