[PATCH v3] dt-bindings: timer: Add SiFive CLINT2

[PATCH v3] dt-bindings: timer: Add SiFive CLINT2

[Nick Hu]

Add compatible string and property for the SiFive CLINT v2. The SiFive
CLINT v2 is incompatible with the SiFive CLINT v0 due to differences
in their control methods.

Signed-off-by: Nick Hu <nick.hu@sifive.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
---
- v3 changes:
  - Add the reason for the incompatibility between sifive,clint2 and
    sifive,clint0.
- v2 changes:
  - Don't allow sifive,clint2 by itself. Add '-{}' to the first entry
  - Mark the sifive,fine-ctr-bits as the required property when
    the compatible includes the sifive,clint2

 .../bindings/timer/sifive,clint.yaml          | 22 +++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
index 76d83aea4e2b..34684cda8b15 100644
--- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
+++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
@@ -36,6 +36,12 @@ properties:
               - starfive,jh7110-clint   # StarFive JH7110
               - starfive,jh8100-clint   # StarFive JH8100
           - const: sifive,clint0        # SiFive CLINT v0 IP block
+      - items:
+          - {}
+          - const: sifive,clint2        # SiFive CLINT v2 IP block
+        description:
+          SiFive CLINT v2 is the HRT that supports the Zicntr. The control of sifive,clint2
+          differs from that of sifive,clint0, making them incompatible.
       - items:
           - enum:
               - allwinner,sun20i-d1-clint
@@ -62,6 +68,22 @@ properties:
     minItems: 1
     maxItems: 4095
 
+  sifive,fine-ctr-bits:
+    maximum: 15
+    description: The width in bits of the fine counter.
+
+if:
+  properties:
+    compatible:
+      contains:
+        const: sifive,clint2
+then:
+  required:
+    - sifive,fine-ctr-bits
+else:
+  properties:
+    sifive,fine-ctr-bits: false
+
 additionalProperties: false
 
 required:
-- 
2.17.1

Re: [PATCH v3] dt-bindings: timer: Add SiFive CLINT2

[Conor Dooley]

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On Fri, Mar 21, 2025 at 04:35:06PM +0800, Nick Hu wrote:
> Add compatible string and property for the SiFive CLINT v2. The SiFive
> CLINT v2 is incompatible with the SiFive CLINT v0 due to differences
> in their control methods.
> 
> Signed-off-by: Nick Hu <nick.hu@sifive.com>
> Reviewed-by: Samuel Holland <samuel.holland@sifive.com>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

> ---
> - v3 changes:
>   - Add the reason for the incompatibility between sifive,clint2 and
>     sifive,clint0.
> - v2 changes:
>   - Don't allow sifive,clint2 by itself. Add '-{}' to the first entry
>   - Mark the sifive,fine-ctr-bits as the required property when
>     the compatible includes the sifive,clint2
> 
>  .../bindings/timer/sifive,clint.yaml          | 22 +++++++++++++++++++
>  1 file changed, 22 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> index 76d83aea4e2b..34684cda8b15 100644
> --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> @@ -36,6 +36,12 @@ properties:
>                - starfive,jh7110-clint   # StarFive JH7110
>                - starfive,jh8100-clint   # StarFive JH8100
>            - const: sifive,clint0        # SiFive CLINT v0 IP block
> +      - items:
> +          - {}
> +          - const: sifive,clint2        # SiFive CLINT v2 IP block
> +        description:
> +          SiFive CLINT v2 is the HRT that supports the Zicntr. The control of sifive,clint2
> +          differs from that of sifive,clint0, making them incompatible.
>        - items:
>            - enum:
>                - allwinner,sun20i-d1-clint
> @@ -62,6 +68,22 @@ properties:
>      minItems: 1
>      maxItems: 4095
>  
> +  sifive,fine-ctr-bits:
> +    maximum: 15
> +    description: The width in bits of the fine counter.
> +
> +if:
> +  properties:
> +    compatible:
> +      contains:
> +        const: sifive,clint2
> +then:
> +  required:
> +    - sifive,fine-ctr-bits
> +else:
> +  properties:
> +    sifive,fine-ctr-bits: false
> +
>  additionalProperties: false
>  
>  required:
> -- 
> 2.17.1
> 

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[tip: timers/clocksource] dt-bindings: timer: Add SiFive CLINT2

[tip-bot2 for Nick Hu]

The following commit has been merged into the timers/clocksource branch of tip:

Commit-ID:     0f920690a82cc99ae08cab08bee2e5685b62fd04
Gitweb:        https://git.kernel.org/tip/0f920690a82cc99ae08cab08bee2e5685b62fd04
Author:        Nick Hu <nick.hu@sifive.com>
AuthorDate:    Fri, 21 Mar 2025 16:35:06 +08:00
Committer:     Daniel Lezcano <daniel.lezcano@linaro.org>
CommitterDate: Sun, 23 Mar 2025 10:55:43 +01:00

dt-bindings: timer: Add SiFive CLINT2

Add compatible string and property for the SiFive CLINT v2. The SiFive
CLINT v2 is incompatible with the SiFive CLINT v0 due to differences
in their control methods.

Signed-off-by: Nick Hu <nick.hu@sifive.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250321083507.25298-1-nick.hu@sifive.com
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
 Documentation/devicetree/bindings/timer/sifive,clint.yaml | 22 +++++++-
 1 file changed, 22 insertions(+)

diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
index 73edde5..653e2e0 100644
--- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
+++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
@@ -37,6 +37,12 @@ properties:
               - starfive,jh8100-clint   # StarFive JH8100
           - const: sifive,clint0        # SiFive CLINT v0 IP block
       - items:
+          - {}
+          - const: sifive,clint2        # SiFive CLINT v2 IP block
+        description:
+          SiFive CLINT v2 is the HRT that supports the Zicntr. The control of sifive,clint2
+          differs from that of sifive,clint0, making them incompatible.
+      - items:
           - enum:
               - allwinner,sun20i-d1-clint
               - sophgo,cv1800b-clint
@@ -62,6 +68,22 @@ properties:
     minItems: 1
     maxItems: 4095
 
+  sifive,fine-ctr-bits:
+    maximum: 15
+    description: The width in bits of the fine counter.
+
+if:
+  properties:
+    compatible:
+      contains:
+        const: sifive,clint2
+then:
+  required:
+    - sifive,fine-ctr-bits
+else:
+  properties:
+    sifive,fine-ctr-bits: false
+
 additionalProperties: false
 
 required:

Re: [PATCH v3] dt-bindings: timer: Add SiFive CLINT2

[patchwork-bot+linux-riscv]

Hello:

This patch was applied to riscv/linux.git (fixes)
by Daniel Lezcano <daniel.lezcano@linaro.org>:

On Fri, 21 Mar 2025 16:35:06 +0800 you wrote:
> Add compatible string and property for the SiFive CLINT v2. The SiFive
> CLINT v2 is incompatible with the SiFive CLINT v0 due to differences
> in their control methods.
> 
> Signed-off-by: Nick Hu <nick.hu@sifive.com>
> Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
> 
> [...]

Here is the summary with links:
  - [v3] dt-bindings: timer: Add SiFive CLINT2
    https://git.kernel.org/riscv/c/0f920690a82c

You are awesome, thank you!
-- 
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html

Re: [PATCH v3] dt-bindings: timer: Add SiFive CLINT2

[Charles Perry]

On Fri, Mar 21, 2025 at 04:35:06PM +0800, Nick Hu wrote:
> Add compatible string and property for the SiFive CLINT v2. The SiFive
> CLINT v2 is incompatible with the SiFive CLINT v0 due to differences
> in their control methods.

Hello Nick,

Can you help me understand what is this different control method? I've
found that both OpenSBI [1] and U-Boot [2] use the same match data in their
clint driver which would indicate that they are compatible.

Also, do you know if there's an easy way to tell if a sifive clint is a v0
or v2?

Thanks,
Charles

[1]: https://elixir.bootlin.com/opensbi/v1.8.1/source/lib/utils/timer/fdt_timer_mtimer.c#L163
[2]: https://elixir.bootlin.com/u-boot/v2026.01/source/drivers/timer/riscv_aclint_timer.c#L86

> 
> Signed-off-by: Nick Hu <nick.hu@sifive.com>
> Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
> ---
> - v3 changes:
>   - Add the reason for the incompatibility between sifive,clint2 and
>     sifive,clint0.
> - v2 changes:
>   - Don't allow sifive,clint2 by itself. Add '-{}' to the first entry
>   - Mark the sifive,fine-ctr-bits as the required property when
>     the compatible includes the sifive,clint2
> 
>  .../bindings/timer/sifive,clint.yaml          | 22 +++++++++++++++++++
>  1 file changed, 22 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> index 76d83aea4e2b..34684cda8b15 100644
> --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> @@ -36,6 +36,12 @@ properties:
>                - starfive,jh7110-clint   # StarFive JH7110
>                - starfive,jh8100-clint   # StarFive JH8100
>            - const: sifive,clint0        # SiFive CLINT v0 IP block
> +      - items:
> +          - {}
> +          - const: sifive,clint2        # SiFive CLINT v2 IP block
> +        description:
> +          SiFive CLINT v2 is the HRT that supports the Zicntr. The control of sifive,clint2
> +          differs from that of sifive,clint0, making them incompatible.
>        - items:
>            - enum:
>                - allwinner,sun20i-d1-clint
> @@ -62,6 +68,22 @@ properties:
>      minItems: 1
>      maxItems: 4095
>  
> +  sifive,fine-ctr-bits:
> +    maximum: 15
> +    description: The width in bits of the fine counter.
> +
> +if:
> +  properties:
> +    compatible:
> +      contains:
> +        const: sifive,clint2
> +then:
> +  required:
> +    - sifive,fine-ctr-bits
> +else:
> +  properties:
> +    sifive,fine-ctr-bits: false
> +
>  additionalProperties: false
>  
>  required:
> -- 
> 2.17.1
> 
> 

Re: [PATCH v3] dt-bindings: timer: Add SiFive CLINT2

[Conor Dooley]

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On Thu, Mar 26, 2026 at 01:55:38PM -0700, Charles Perry wrote:
> On Fri, Mar 21, 2025 at 04:35:06PM +0800, Nick Hu wrote:
> > Add compatible string and property for the SiFive CLINT v2. The SiFive
> > CLINT v2 is incompatible with the SiFive CLINT v0 due to differences
> > in their control methods.
> 
> Hello Nick,
> 
> Can you help me understand what is this different control method? I've
> found that both OpenSBI [1] and U-Boot [2] use the same match data in their
> clint driver which would indicate that they are compatible.

Hmm, good point. I didn't see that the drivers were not doing anything
different. I guess really the clintv2 should fall back to the clintv0,
and the difference in hardware should be elaborated on.

I think I also dropped the ball on sifive,fine-ctr-bits, and that should
be removed and the counter width determined from the compatible.
There's no users for that yet I think, and there's no valid users of the
clintv2 compatible /at all/ so maybe it can just get culled.

> 
> Also, do you know if there's an easy way to tell if a sifive clint is a v0
> or v2?
> 
> Thanks,
> Charles
> 
> [1]: https://elixir.bootlin.com/opensbi/v1.8.1/source/lib/utils/timer/fdt_timer_mtimer.c#L163
> [2]: https://elixir.bootlin.com/u-boot/v2026.01/source/drivers/timer/riscv_aclint_timer.c#L86
> 
> > 
> > Signed-off-by: Nick Hu <nick.hu@sifive.com>
> > Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
> > ---
> > - v3 changes:
> >   - Add the reason for the incompatibility between sifive,clint2 and
> >     sifive,clint0.
> > - v2 changes:
> >   - Don't allow sifive,clint2 by itself. Add '-{}' to the first entry
> >   - Mark the sifive,fine-ctr-bits as the required property when
> >     the compatible includes the sifive,clint2
> > 
> >  .../bindings/timer/sifive,clint.yaml          | 22 +++++++++++++++++++
> >  1 file changed, 22 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> > index 76d83aea4e2b..34684cda8b15 100644
> > --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> > +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> > @@ -36,6 +36,12 @@ properties:
> >                - starfive,jh7110-clint   # StarFive JH7110
> >                - starfive,jh8100-clint   # StarFive JH8100
> >            - const: sifive,clint0        # SiFive CLINT v0 IP block
> > +      - items:
> > +          - {}
> > +          - const: sifive,clint2        # SiFive CLINT v2 IP block
> > +        description:
> > +          SiFive CLINT v2 is the HRT that supports the Zicntr. The control of sifive,clint2
> > +          differs from that of sifive,clint0, making them incompatible.
> >        - items:
> >            - enum:
> >                - allwinner,sun20i-d1-clint
> > @@ -62,6 +68,22 @@ properties:
> >      minItems: 1
> >      maxItems: 4095
> >  
> > +  sifive,fine-ctr-bits:
> > +    maximum: 15
> > +    description: The width in bits of the fine counter.
> > +
> > +if:
> > +  properties:
> > +    compatible:
> > +      contains:
> > +        const: sifive,clint2
> > +then:
> > +  required:
> > +    - sifive,fine-ctr-bits
> > +else:
> > +  properties:
> > +    sifive,fine-ctr-bits: false
> > +
> >  additionalProperties: false
> >  
> >  required:
> > -- 
> > 2.17.1
> > 
> > 

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Re: [PATCH v3] dt-bindings: timer: Add SiFive CLINT2

[Nick Hu]

On Tue, Mar 31, 2026 at 12:16 AM Conor Dooley <conor@kernel.org> wrote:
>
> On Thu, Mar 26, 2026 at 01:55:38PM -0700, Charles Perry wrote:
> > On Fri, Mar 21, 2025 at 04:35:06PM +0800, Nick Hu wrote:
> > > Add compatible string and property for the SiFive CLINT v2. The SiFive
> > > CLINT v2 is incompatible with the SiFive CLINT v0 due to differences
> > > in their control methods.
> >
> > Hello Nick,
> >
> > Can you help me understand what is this different control method? I've
> > found that both OpenSBI [1] and U-Boot [2] use the same match data in their
> > clint driver which would indicate that they are compatible.
>
> Hmm, good point. I didn't see that the drivers were not doing anything
> different. I guess really the clintv2 should fall back to the clintv0,
> and the difference in hardware should be elaborated on.
>
> I think I also dropped the ball on sifive,fine-ctr-bits, and that should
> be removed and the counter width determined from the compatible.
> There's no users for that yet I think, and there's no valid users of the
> clintv2 compatible /at all/ so maybe it can just get culled.
>
Thanks for pointing that out, I'll send a patch to remove the
sifive,fine-ctr-bits property.


> >
> > Also, do you know if there's an easy way to tell if a sifive clint is a v0
> > or v2?
> >
> > Thanks,
> > Charles
> >
> > [1]: https://elixir.bootlin.com/opensbi/v1.8.1/source/lib/utils/timer/fdt_timer_mtimer.c#L163
> > [2]: https://elixir.bootlin.com/u-boot/v2026.01/source/drivers/timer/riscv_aclint_timer.c#L86
> >
> > >
> > > Signed-off-by: Nick Hu <nick.hu@sifive.com>
> > > Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
> > > ---
> > > - v3 changes:
> > >   - Add the reason for the incompatibility between sifive,clint2 and
> > >     sifive,clint0.
> > > - v2 changes:
> > >   - Don't allow sifive,clint2 by itself. Add '-{}' to the first entry
> > >   - Mark the sifive,fine-ctr-bits as the required property when
> > >     the compatible includes the sifive,clint2
> > >
> > >  .../bindings/timer/sifive,clint.yaml          | 22 +++++++++++++++++++
> > >  1 file changed, 22 insertions(+)
> > >
> > > diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> > > index 76d83aea4e2b..34684cda8b15 100644
> > > --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> > > +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> > > @@ -36,6 +36,12 @@ properties:
> > >                - starfive,jh7110-clint   # StarFive JH7110
> > >                - starfive,jh8100-clint   # StarFive JH8100
> > >            - const: sifive,clint0        # SiFive CLINT v0 IP block
> > > +      - items:
> > > +          - {}
> > > +          - const: sifive,clint2        # SiFive CLINT v2 IP block
> > > +        description:
> > > +          SiFive CLINT v2 is the HRT that supports the Zicntr. The control of sifive,clint2
> > > +          differs from that of sifive,clint0, making them incompatible.
> > >        - items:
> > >            - enum:
> > >                - allwinner,sun20i-d1-clint
> > > @@ -62,6 +68,22 @@ properties:
> > >      minItems: 1
> > >      maxItems: 4095
> > >
> > > +  sifive,fine-ctr-bits:
> > > +    maximum: 15
> > > +    description: The width in bits of the fine counter.
> > > +
> > > +if:
> > > +  properties:
> > > +    compatible:
> > > +      contains:
> > > +        const: sifive,clint2
> > > +then:
> > > +  required:
> > > +    - sifive,fine-ctr-bits
> > > +else:
> > > +  properties:
> > > +    sifive,fine-ctr-bits: false
> > > +
> > >  additionalProperties: false
> > >
> > >  required:
> > > --
> > > 2.17.1
> > >
> > >

Re: [PATCH v3] dt-bindings: timer: Add SiFive CLINT2

[Nick Hu]

On Fri, Mar 27, 2026 at 4:56 AM Charles Perry
<charles.perry@microchip.com> wrote:
>
> On Fri, Mar 21, 2025 at 04:35:06PM +0800, Nick Hu wrote:
> > Add compatible string and property for the SiFive CLINT v2. The SiFive
> > CLINT v2 is incompatible with the SiFive CLINT v0 due to differences
> > in their control methods.
>
> Hello Nick,
>
> Can you help me understand what is this different control method? I've
> found that both OpenSBI [1] and U-Boot [2] use the same match data in their
> clint driver which would indicate that they are compatible.
>
Sorry for the late reply.
Unlike v0, v2 requires a write to the mtime register to kick the timer.

> Also, do you know if there's an easy way to tell if a sifive clint is a v0
> or v2?
>
sifive,clint2 introduces additional MMIO registers

> Thanks,
> Charles
>
> [1]: https://elixir.bootlin.com/opensbi/v1.8.1/source/lib/utils/timer/fdt_timer_mtimer.c#L163
> [2]: https://elixir.bootlin.com/u-boot/v2026.01/source/drivers/timer/riscv_aclint_timer.c#L86
>
> >
> > Signed-off-by: Nick Hu <nick.hu@sifive.com>
> > Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
> > ---
> > - v3 changes:
> >   - Add the reason for the incompatibility between sifive,clint2 and
> >     sifive,clint0.
> > - v2 changes:
> >   - Don't allow sifive,clint2 by itself. Add '-{}' to the first entry
> >   - Mark the sifive,fine-ctr-bits as the required property when
> >     the compatible includes the sifive,clint2
> >
> >  .../bindings/timer/sifive,clint.yaml          | 22 +++++++++++++++++++
> >  1 file changed, 22 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> > index 76d83aea4e2b..34684cda8b15 100644
> > --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> > +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> > @@ -36,6 +36,12 @@ properties:
> >                - starfive,jh7110-clint   # StarFive JH7110
> >                - starfive,jh8100-clint   # StarFive JH8100
> >            - const: sifive,clint0        # SiFive CLINT v0 IP block
> > +      - items:
> > +          - {}
> > +          - const: sifive,clint2        # SiFive CLINT v2 IP block
> > +        description:
> > +          SiFive CLINT v2 is the HRT that supports the Zicntr. The control of sifive,clint2
> > +          differs from that of sifive,clint0, making them incompatible.
> >        - items:
> >            - enum:
> >                - allwinner,sun20i-d1-clint
> > @@ -62,6 +68,22 @@ properties:
> >      minItems: 1
> >      maxItems: 4095
> >
> > +  sifive,fine-ctr-bits:
> > +    maximum: 15
> > +    description: The width in bits of the fine counter.
> > +
> > +if:
> > +  properties:
> > +    compatible:
> > +      contains:
> > +        const: sifive,clint2
> > +then:
> > +  required:
> > +    - sifive,fine-ctr-bits
> > +else:
> > +  properties:
> > +    sifive,fine-ctr-bits: false
> > +
> >  additionalProperties: false
> >
> >  required:
> > --
> > 2.17.1
> >
> >

Re: [PATCH v3] dt-bindings: timer: Add SiFive CLINT2

[Charles Perry]

On Wed, Apr 08, 2026 at 02:15:19PM +0800, Nick Hu wrote:
> On Fri, Mar 27, 2026 at 4:56 AM Charles Perry
> <charles.perry@microchip.com> wrote:
> >
> > On Fri, Mar 21, 2025 at 04:35:06PM +0800, Nick Hu wrote:
> > > Add compatible string and property for the SiFive CLINT v2. The SiFive
> > > CLINT v2 is incompatible with the SiFive CLINT v0 due to differences
> > > in their control methods.
> >
> > Hello Nick,
> >
> > Can you help me understand what is this different control method? I've
> > found that both OpenSBI [1] and U-Boot [2] use the same match data in their
> > clint driver which would indicate that they are compatible.
> >
> Sorry for the late reply.

Hello Nick, no worries.

> Unlike v0, v2 requires a write to the mtime register to kick the timer.

A kick once at the beginning or every time a machine timer interrupt fires?

> 
> > Also, do you know if there's an easy way to tell if a sifive clint is a v0
> > or v2?
> >
> sifive,clint2 introduces additional MMIO registers

Is that the high resolution timers (HRT) mentionned in the description?

And last question, would you happen to know if sifive made a clint v1 that
does NOT require the mtime kick but does have the HRT?

I'm trying to figure out what should be the compatible for PIC64-HPSC.
Some code from a repository called "FSFM" used "sifive,clint1" for the
compatible. I'm wondering if I should add the clint v1 to this file.

Thanks,
Charles

Re: [PATCH v3] dt-bindings: timer: Add SiFive CLINT2

[Nick Hu]

On Wed, Apr 8, 2026 at 10:41 PM Charles Perry
<charles.perry@microchip.com> wrote:
>
> On Wed, Apr 08, 2026 at 02:15:19PM +0800, Nick Hu wrote:
> > On Fri, Mar 27, 2026 at 4:56 AM Charles Perry
> > <charles.perry@microchip.com> wrote:
> > >
> > > On Fri, Mar 21, 2025 at 04:35:06PM +0800, Nick Hu wrote:
> > > > Add compatible string and property for the SiFive CLINT v2. The SiFive
> > > > CLINT v2 is incompatible with the SiFive CLINT v0 due to differences
> > > > in their control methods.
> > >
> > > Hello Nick,
> > >
> > > Can you help me understand what is this different control method? I've
> > > found that both OpenSBI [1] and U-Boot [2] use the same match data in their
> > > clint driver which would indicate that they are compatible.
> > >
> > Sorry for the late reply.
>
> Hello Nick, no worries.
>
> > Unlike v0, v2 requires a write to the mtime register to kick the timer.
>
> A kick once at the beginning or every time a machine timer interrupt fires?
>
A kick once at the beginning

> >
> > > Also, do you know if there's an easy way to tell if a sifive clint is a v0
> > > or v2?
> > >
> > sifive,clint2 introduces additional MMIO registers
>
> Is that the high resolution timers (HRT) mentionned in the description?
>
> And last question, would you happen to know if sifive made a clint v1 that
> does NOT require the mtime kick but does have the HRT?
>
Yes, that's correct.

> I'm trying to figure out what should be the compatible for PIC64-HPSC.
> Some code from a repository called "FSFM" used "sifive,clint1" for the
> compatible. I'm wondering if I should add the clint v1 to this file.
>
> Thanks,
> Charles
>

Re: [PATCH v3] dt-bindings: timer: Add SiFive CLINT2

[Charles Perry]

On Thu, Apr 09, 2026 at 01:37:46PM +0800, Nick Hu wrote:
> On Wed, Apr 8, 2026 at 10:41 PM Charles Perry
> <charles.perry@microchip.com> wrote:
> >
> > On Wed, Apr 08, 2026 at 02:15:19PM +0800, Nick Hu wrote:
> > > On Fri, Mar 27, 2026 at 4:56 AM Charles Perry
> > > <charles.perry@microchip.com> wrote:
> > > >
> > > > On Fri, Mar 21, 2025 at 04:35:06PM +0800, Nick Hu wrote:
> > > > > Add compatible string and property for the SiFive CLINT v2. The SiFive
> > > > > CLINT v2 is incompatible with the SiFive CLINT v0 due to differences
> > > > > in their control methods.
> > > >
> > > > Hello Nick,
> > > >
> > > > Can you help me understand what is this different control method? I've
> > > > found that both OpenSBI [1] and U-Boot [2] use the same match data in their
> > > > clint driver which would indicate that they are compatible.
> > > >
> > > Sorry for the late reply.
> >
> > Hello Nick, no worries.
> >
> > > Unlike v0, v2 requires a write to the mtime register to kick the timer.
> >
> > A kick once at the beginning or every time a machine timer interrupt fires?
> >
> A kick once at the beginning

That would explain what I observed in U-Boot and OpenSBI. The kick might be
in some arch specific code or a prior boot stage.

> 
> > >
> > > > Also, do you know if there's an easy way to tell if a sifive clint is a v0
> > > > or v2?
> > > >
> > > sifive,clint2 introduces additional MMIO registers
> >
> > Is that the high resolution timers (HRT) mentionned in the description?
> >
> > And last question, would you happen to know if sifive made a clint v1 that
> > does NOT require the mtime kick but does have the HRT?
> >
> Yes, that's correct.

Ok.

Thanks,
Charles

> 
> > I'm trying to figure out what should be the compatible for PIC64-HPSC.
> > Some code from a repository called "FSFM" used "sifive,clint1" for the
> > compatible. I'm wondering if I should add the clint v1 to this file.
> >
> > Thanks,
> > Charles
> >