From: Nirmoy Das <nirmoyd@nvidia.com>
To: <ankita@nvidia.com>
Cc: <alex@shazbot.org>, <bhelgaas@google.com>, <jgg@ziepe.ca>,
<kevin.tian@intel.com>, <kvm@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <linux-pci@vger.kernel.org>,
<skolothumtho@nvidia.com>, <yishaih@nvidia.com>,
Nirmoy Das <nirmoyd@nvidia.com>
Subject: Re: [PATCH v3 1/1] vfio/nvgrace-gpu: Add Blackwell-Next GPU readiness check via CXL DVSEC
Date: Mon, 20 Apr 2026 06:20:08 -0700 [thread overview]
Message-ID: <20260420132008.521631-1-nirmoyd@nvidia.com> (raw)
In-Reply-To: <20260416014504.63067-1-ankita@nvidia.com>
On Thu, 16 Apr 2026 01:45:04 +0000, Ankit Agrawal <ankita@nvidia.com> wrote:
> Add a CXL DVSEC-based readiness check for Blackwell-Next GPUs alongside
> the existing legacy BAR0 polling path. On probe and after reset, the
> driver reads the CXL Device DVSEC capability to determine whether the
> GPU memory is valid. This is checked by polling on the Memory_Active bit
> based on the Memory_Active_Timeout. Also check if MEM_INFO_VALID is set
> within 1 second per CXL spec 4.0 Tables 8-13. If not, return error.
>
> A static inline wrapper dispatches to the appropriate readiness check
> based on whether the CXL DVSEC capability is present.
>
> Add PCI_DVSEC_CXL_MEM_ACTIVE_TIMEOUT to pci_regs.h for the timeout
> field encoding.
>
> Signed-off-by: Ankit Agrawal <ankita@nvidia.com>
Tested-and-Acked-by: Nirmoy Das <nirmoyd@nvidia.com>
next prev parent reply other threads:[~2026-04-20 13:21 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-16 1:45 [PATCH v3 1/1] vfio/nvgrace-gpu: Add Blackwell-Next GPU readiness check via CXL DVSEC Ankit Agrawal
2026-04-17 7:16 ` Tian, Kevin
2026-04-20 13:20 ` Nirmoy Das [this message]
2026-04-20 20:09 ` kernel test robot
2026-04-21 2:37 ` kernel test robot
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