Re: [PATCH v3 1/1] vfio/nvgrace-gpu: Add Blackwell-Next GPU readiness check via CXL DVSEC

[kernel test robot <lkp@intel.com>]

Hi Ankit,

kernel test robot noticed the following build errors:

[auto build test ERROR on awilliam-vfio/next]
[also build test ERROR on awilliam-vfio/for-linus pci/next pci/for-linus linus/master v7.0 next-20260420]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Ankit-Agrawal/vfio-nvgrace-gpu-Add-Blackwell-Next-GPU-readiness-check-via-CXL-DVSEC/20260419-053131
base:   https://github.com/awilliam/linux-vfio.git next
patch link:    https://lore.kernel.org/r/20260416014504.63067-1-ankita%40nvidia.com
patch subject: [PATCH v3 1/1] vfio/nvgrace-gpu: Add Blackwell-Next GPU readiness check via CXL DVSEC
config: alpha-allyesconfig (https://download.01.org/0day-ci/archive/20260421/202604211223.HLb8onLi-lkp@intel.com/config)
compiler: alpha-linux-gcc (GCC) 15.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260421/202604211223.HLb8onLi-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202604211223.HLb8onLi-lkp@intel.com/

All errors (new ones prefixed by >>):

   drivers/vfio/pci/nvgrace-gpu/main.c: In function 'nvgrace_gpu_wait_device_ready_cxl':
>> drivers/vfio/pci/nvgrace-gpu/main.c:296:30: error: implicit declaration of function 'FIELD_GET' [-Wimplicit-function-declaration]
     296 |         mem_active_timeout = FIELD_GET(PCI_DVSEC_CXL_MEM_ACTIVE_TIMEOUT,
         |                              ^~~~~~~~~


vim +/FIELD_GET +296 drivers/vfio/pci/nvgrace-gpu/main.c

   280	
   281	static int nvgrace_gpu_wait_device_ready_cxl(struct nvgrace_gpu_pci_core_device *nvdev)
   282	{
   283		struct pci_dev *pdev = nvdev->core_device.pdev;
   284		int cxl_dvsec = nvdev->cxl_dvsec;
   285		unsigned long mem_info_valid_deadline;
   286		unsigned long timeout;
   287		u32 dvsec_memory_status;
   288		u8 mem_active_timeout;
   289	
   290		pci_read_config_dword(pdev, cxl_dvsec + PCI_DVSEC_CXL_RANGE_SIZE_LOW(0),
   291				      &dvsec_memory_status);
   292	
   293		if (cxl_dvsec_mem_is_active(dvsec_memory_status))
   294			return 0;
   295	
 > 296		mem_active_timeout = FIELD_GET(PCI_DVSEC_CXL_MEM_ACTIVE_TIMEOUT,
   297					       dvsec_memory_status);
   298	
   299		timeout = jiffies +
   300			  msecs_to_jiffies(cxl_mem_active_timeout_ms(mem_active_timeout));
   301	
   302		mem_info_valid_deadline = jiffies + msecs_to_jiffies(POLL_QUANTUM_MS);
   303	
   304		do {
   305			pci_read_config_dword(pdev,
   306					      cxl_dvsec + PCI_DVSEC_CXL_RANGE_SIZE_LOW(0),
   307					      &dvsec_memory_status);
   308	
   309			if (cxl_dvsec_mem_is_active(dvsec_memory_status))
   310				return 0;
   311	
   312			/* Bail early if MEM_INFO_VALID is not set within 1 second */
   313			if (!(dvsec_memory_status & PCI_DVSEC_CXL_MEM_INFO_VALID) &&
   314			    time_after(jiffies, mem_info_valid_deadline))
   315				return -ETIME;
   316	
   317			msleep(POLL_QUANTUM_MS);
   318		} while (!time_after(jiffies, timeout));
   319	
   320		return -ETIME;
   321	}
   322	

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