* [PATCH v2 01/13] media: iris: Fix VM count passed to firmware
2026-04-23 13:29 [PATCH v2 00/13] media: iris: Add support for glymur platform Vishnu Reddy
@ 2026-04-23 13:29 ` Vishnu Reddy
2026-04-23 13:29 ` [PATCH v2 02/13] drivers: base: Add generic dma context bus Vishnu Reddy
` (11 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Vishnu Reddy @ 2026-04-23 13:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vikash Garodia, Dikshita Agarwal,
Abhinav Kumar, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Joerg Roedel, Will Deacon,
Robin Murphy, Bjorn Andersson, Konrad Dybcio, Stefan Schmidt,
Hans Verkuil, Greg Kroah-Hartman, Rafael J. Wysocki,
Danilo Krummrich, Thierry Reding, Mikko Perttunen, David Airlie,
Simona Vetter, Jonathan Hunter
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel, iommu,
driver-core, dri-devel, linux-tegra, Vishnu Reddy, stable
On Glymur, firmware interprets the value written to CPU_CS_SCIACMDARG3 as
the number of virtual machines (VMs) and internally adds 1 to it. Writing
1 causes firmware to treat it as 2 VMs. Since only one VM is required,
remove this write to leave the register at its reset value of 0. This does
not affect other platforms as only Glymur firmware uses this register,
earlier platform firmwares ignore it.
Fixes: abf5bac63f68a ("media: iris: implement the boot sequence of the firmware")
Cc: stable@vger.kernel.org
Reviewed-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
---
drivers/media/platform/qcom/iris/iris_vpu_common.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c
index 548e5f1727fd..bfd1e762c38e 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_common.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c
@@ -78,7 +78,6 @@ int iris_vpu_boot_firmware(struct iris_core *core)
iris_vpu_setup_ucregion_memory_map(core);
writel(ctrl_init, core->reg_base + CTRL_INIT);
- writel(0x1, core->reg_base + CPU_CS_SCIACMDARG3);
while (!ctrl_status && count < max_tries) {
ctrl_status = readl(core->reg_base + CTRL_STATUS);
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v2 02/13] drivers: base: Add generic dma context bus
2026-04-23 13:29 [PATCH v2 00/13] media: iris: Add support for glymur platform Vishnu Reddy
2026-04-23 13:29 ` [PATCH v2 01/13] media: iris: Fix VM count passed to firmware Vishnu Reddy
@ 2026-04-23 13:29 ` Vishnu Reddy
2026-04-23 13:37 ` Greg Kroah-Hartman
2026-04-23 13:29 ` [PATCH v2 03/13] gpu: host1x: Migrate to " Vishnu Reddy
` (10 subsequent siblings)
12 siblings, 1 reply; 17+ messages in thread
From: Vishnu Reddy @ 2026-04-23 13:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vikash Garodia, Dikshita Agarwal,
Abhinav Kumar, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Joerg Roedel, Will Deacon,
Robin Murphy, Bjorn Andersson, Konrad Dybcio, Stefan Schmidt,
Hans Verkuil, Greg Kroah-Hartman, Rafael J. Wysocki,
Danilo Krummrich, Thierry Reding, Mikko Perttunen, David Airlie,
Simona Vetter, Jonathan Hunter
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel, iommu,
driver-core, dri-devel, linux-tegra, Vishnu Reddy, Ekansh Gupta,
Dmitry Baryshkov
From: Ekansh Gupta <ekansh.gupta@oss.qualcomm.com>
When a driver needs to create virtual device at runtime and map it to
an IOMMU context for memory isolation, there is no common bus available
for this purpose. Each driver ends up implementing its own bus type,
leading to duplicated logic across multiple drivers.
host1x driver implemented its own bus type to attach an IOMMU context to
a dynamically created device. The Iris VPU driver now has the same
requirement. Rather than duplicating the same bus logic again, a shared
bus type is introduced under drivers/base that multiple drivers can use
directly.
The bus takes care of creating a device and attaching the IOMMU context
to it based on the client inputs.
Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Ekansh Gupta <ekansh.gupta@oss.qualcomm.com>
Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
---
drivers/base/Kconfig | 3 ++
drivers/base/Makefile | 1 +
drivers/base/dma_context_bus.c | 77 +++++++++++++++++++++++++++++++++++++++++
include/linux/dma_context_bus.h | 26 ++++++++++++++
4 files changed, 107 insertions(+)
diff --git a/drivers/base/Kconfig b/drivers/base/Kconfig
index f7d385cbd3ba..499ea92dd88f 100644
--- a/drivers/base/Kconfig
+++ b/drivers/base/Kconfig
@@ -4,6 +4,9 @@ menu "Generic Driver Options"
config AUXILIARY_BUS
bool
+config DMA_CONTEXT_BUS
+ bool
+
config UEVENT_HELPER
bool "Support for uevent helper"
help
diff --git a/drivers/base/Makefile b/drivers/base/Makefile
index 8074a10183dc..348e69695e55 100644
--- a/drivers/base/Makefile
+++ b/drivers/base/Makefile
@@ -8,6 +8,7 @@ obj-y := component.o core.o bus.o dd.o syscore.o \
topology.o container.o property.o cacheinfo.o \
swnode.o faux.o
obj-$(CONFIG_AUXILIARY_BUS) += auxiliary.o
+obj-$(CONFIG_DMA_CONTEXT_BUS) += dma_context_bus.o
obj-$(CONFIG_DEVTMPFS) += devtmpfs.o
obj-y += power/
obj-$(CONFIG_ISA_BUS_API) += isa.o
diff --git a/drivers/base/dma_context_bus.c b/drivers/base/dma_context_bus.c
new file mode 100644
index 000000000000..c2ac189ce08d
--- /dev/null
+++ b/drivers/base/dma_context_bus.c
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <linux/dma_context_bus.h>
+#include <linux/of_device.h>
+
+static atomic_t dma_context_bus_device_id = ATOMIC_INIT(0);
+
+static int dma_context_bus_device_configure(struct device *dev)
+{
+ const u32 *iommu_fid = dev_get_drvdata(dev);
+ struct device_node *of_node = dev->of_node;
+
+ if (!of_node)
+ of_node = dev->parent->of_node;
+
+ return of_dma_configure_id(dev, of_node, true, iommu_fid);
+}
+
+const struct bus_type dma_context_bus_type = {
+ .name = "dma-context-bus",
+ .dma_configure = dma_context_bus_device_configure,
+};
+EXPORT_SYMBOL_GPL(dma_context_bus_type);
+
+static void release_dma_context_bus_device(struct device *dev)
+{
+ kfree(dev);
+}
+
+struct device *create_dma_context_bus_device(struct device *parent_device,
+ struct device_node *of_node,
+ u64 dma_mask, const u32 *iommu_fid)
+{
+ struct device *dev;
+ int dev_id, ret;
+
+ dev = kzalloc_obj(*dev);
+ if (!dev)
+ return ERR_PTR(-ENOMEM);
+
+ dev->release = release_dma_context_bus_device;
+ dev->bus = &dma_context_bus_type;
+ dev->parent = parent_device;
+ dev->coherent_dma_mask = dma_mask;
+ dev->dma_mask = &dev->coherent_dma_mask;
+ dev->of_node = of_node;
+
+ dev_id = atomic_inc_return(&dma_context_bus_device_id);
+ dev_set_name(dev, "dma-context-bus-%d", dev_id);
+ dev_set_drvdata(dev, (void *)iommu_fid);
+
+ ret = device_register(dev);
+ if (ret) {
+ put_device(dev);
+ return ERR_PTR(ret);
+ }
+
+ return dev;
+}
+EXPORT_SYMBOL_GPL(create_dma_context_bus_device);
+
+static int __init dma_context_bus_init(void)
+{
+ int err;
+
+ err = bus_register(&dma_context_bus_type);
+ if (err) {
+ pr_err("dma-context-bus registration failed: %d\n", err);
+ return err;
+ }
+
+ return 0;
+}
+postcore_initcall(dma_context_bus_init);
diff --git a/include/linux/dma_context_bus.h b/include/linux/dma_context_bus.h
new file mode 100644
index 000000000000..3d89594fbce4
--- /dev/null
+++ b/include/linux/dma_context_bus.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _LINUX_DMA_CONTEXT_BUS_H
+#define _LINUX_DMA_CONTEXT_BUS_H
+
+#include <linux/device.h>
+
+#ifdef CONFIG_DMA_CONTEXT_BUS
+extern const struct bus_type dma_context_bus_type;
+
+struct device *create_dma_context_bus_device(struct device *parent_device,
+ struct device_node *of_node,
+ u64 dma_mask, const u32 *iommu_f_id);
+#else
+static inline struct device *create_dma_context_bus_device(struct device *parent_device,
+ struct device_node *of_node,
+ u64 dma_mask, const u32 *iommu_f_id)
+{
+ return NULL;
+}
+#endif
+
+#endif /* _LINUX_DMA_CONTEXT_BUS_H */
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH v2 02/13] drivers: base: Add generic dma context bus
2026-04-23 13:29 ` [PATCH v2 02/13] drivers: base: Add generic dma context bus Vishnu Reddy
@ 2026-04-23 13:37 ` Greg Kroah-Hartman
0 siblings, 0 replies; 17+ messages in thread
From: Greg Kroah-Hartman @ 2026-04-23 13:37 UTC (permalink / raw)
To: Vishnu Reddy
Cc: Bryan O'Donoghue, Vikash Garodia, Dikshita Agarwal,
Abhinav Kumar, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Joerg Roedel, Will Deacon,
Robin Murphy, Bjorn Andersson, Konrad Dybcio, Stefan Schmidt,
Hans Verkuil, Rafael J. Wysocki, Danilo Krummrich, Thierry Reding,
Mikko Perttunen, David Airlie, Simona Vetter, Jonathan Hunter,
linux-media, linux-arm-msm, devicetree, linux-kernel, iommu,
driver-core, dri-devel, linux-tegra, Ekansh Gupta,
Dmitry Baryshkov
On Thu, Apr 23, 2026 at 06:59:31PM +0530, Vishnu Reddy wrote:
> From: Ekansh Gupta <ekansh.gupta@oss.qualcomm.com>
>
> When a driver needs to create virtual device at runtime and map it to
> an IOMMU context for memory isolation, there is no common bus available
> for this purpose. Each driver ends up implementing its own bus type,
> leading to duplicated logic across multiple drivers.
>
> host1x driver implemented its own bus type to attach an IOMMU context to
> a dynamically created device. The Iris VPU driver now has the same
> requirement. Rather than duplicating the same bus logic again, a shared
> bus type is introduced under drivers/base that multiple drivers can use
> directly.
>
> The bus takes care of creating a device and attaching the IOMMU context
> to it based on the client inputs.
>
> Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> Signed-off-by: Ekansh Gupta <ekansh.gupta@oss.qualcomm.com>
> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
> Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
> ---
> drivers/base/Kconfig | 3 ++
> drivers/base/Makefile | 1 +
> drivers/base/dma_context_bus.c | 77 +++++++++++++++++++++++++++++++++++++++++
> include/linux/dma_context_bus.h | 26 ++++++++++++++
> 4 files changed, 107 insertions(+)
as you can not have a device on multiple busses at the same time, this
makes no sense to me at all. "dma context" is a bus-specific thing, so
please add it to the bus that you are wanting it for. It can't be a
generic bus as that just doesn't work.
Or what am I missing here?
And why is DMA somehow "special" here from any other hardware attribute?
thanks,
greg k-h
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v2 03/13] gpu: host1x: Migrate to generic dma context bus
2026-04-23 13:29 [PATCH v2 00/13] media: iris: Add support for glymur platform Vishnu Reddy
2026-04-23 13:29 ` [PATCH v2 01/13] media: iris: Fix VM count passed to firmware Vishnu Reddy
2026-04-23 13:29 ` [PATCH v2 02/13] drivers: base: Add generic dma context bus Vishnu Reddy
@ 2026-04-23 13:29 ` Vishnu Reddy
2026-04-23 13:40 ` Greg Kroah-Hartman
2026-04-23 13:29 ` [PATCH v2 04/13] dt-bindings: media: qcom,glymur-iris: Add glymur video codec Vishnu Reddy
` (9 subsequent siblings)
12 siblings, 1 reply; 17+ messages in thread
From: Vishnu Reddy @ 2026-04-23 13:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vikash Garodia, Dikshita Agarwal,
Abhinav Kumar, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Joerg Roedel, Will Deacon,
Robin Murphy, Bjorn Andersson, Konrad Dybcio, Stefan Schmidt,
Hans Verkuil, Greg Kroah-Hartman, Rafael J. Wysocki,
Danilo Krummrich, Thierry Reding, Mikko Perttunen, David Airlie,
Simona Vetter, Jonathan Hunter
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel, iommu,
driver-core, dri-devel, linux-tegra, Vishnu Reddy, Ekansh Gupta
From: Ekansh Gupta <ekansh.gupta@oss.qualcomm.com>
The host1x driver creates context bank devices to map IOMMU contexts
for memory isolation. Previously, this required a host1x-specific bus
type with its own device setup and IOMMU configuration logic.
A generic "dma-context-bus" is now available in the driver core that
handles this for any driver. Replace the host1x-specific bus with this
shared generic bus. This removes the private bus registration, device
setup, and of_dma_configure_id() from host1x, as the generic bus handles
all of this internally.
The IOMMU subsystem is also updated to reference the generic bus instead
of the host1x-specific one.
Signed-off-by: Ekansh Gupta <ekansh.gupta@oss.qualcomm.com>
Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
---
drivers/gpu/drm/tegra/uapi.c | 2 +-
drivers/gpu/host1x/Kconfig | 5 +---
drivers/gpu/host1x/Makefile | 1 -
drivers/gpu/host1x/context.c | 47 ++++++++++++--------------------------
drivers/gpu/host1x/context.h | 3 +--
drivers/gpu/host1x/context_bus.c | 26 ---------------------
drivers/iommu/iommu.c | 6 ++---
include/linux/host1x.h | 2 +-
include/linux/host1x_context_bus.h | 15 ------------
9 files changed, 21 insertions(+), 86 deletions(-)
diff --git a/drivers/gpu/drm/tegra/uapi.c b/drivers/gpu/drm/tegra/uapi.c
index c0ac6b45f2d7..9547725a6c3c 100644
--- a/drivers/gpu/drm/tegra/uapi.c
+++ b/drivers/gpu/drm/tegra/uapi.c
@@ -215,7 +215,7 @@ int tegra_drm_ioctl_channel_map(struct drm_device *drm, void *data, struct drm_f
kref_init(&mapping->ref);
if (context->memory_context)
- mapping_dev = &context->memory_context->dev;
+ mapping_dev = context->memory_context->dev;
else
mapping_dev = context->client->base.dev;
diff --git a/drivers/gpu/host1x/Kconfig b/drivers/gpu/host1x/Kconfig
index e6c78ae2003a..0539ff057a51 100644
--- a/drivers/gpu/host1x/Kconfig
+++ b/drivers/gpu/host1x/Kconfig
@@ -1,13 +1,10 @@
# SPDX-License-Identifier: GPL-2.0-only
-config TEGRA_HOST1X_CONTEXT_BUS
- bool
-
config TEGRA_HOST1X
tristate "NVIDIA Tegra host1x driver"
depends on ARCH_TEGRA || COMPILE_TEST
select DMA_SHARED_BUFFER
- select TEGRA_HOST1X_CONTEXT_BUS
+ select DMA_CONTEXT_BUS
select IOMMU_IOVA
help
Driver for the NVIDIA Tegra host1x hardware.
diff --git a/drivers/gpu/host1x/Makefile b/drivers/gpu/host1x/Makefile
index fead483af0b4..2ccd9a5f1c65 100644
--- a/drivers/gpu/host1x/Makefile
+++ b/drivers/gpu/host1x/Makefile
@@ -23,4 +23,3 @@ host1x-$(CONFIG_IOMMU_API) += \
context.o
obj-$(CONFIG_TEGRA_HOST1X) += host1x.o
-obj-$(CONFIG_TEGRA_HOST1X_CONTEXT_BUS) += context_bus.o
diff --git a/drivers/gpu/host1x/context.c b/drivers/gpu/host1x/context.c
index d50d41c20561..ab7b156ab002 100644
--- a/drivers/gpu/host1x/context.c
+++ b/drivers/gpu/host1x/context.c
@@ -13,16 +13,12 @@
#include "context.h"
#include "dev.h"
-static void host1x_memory_context_release(struct device *dev)
-{
- /* context device is freed in host1x_memory_context_list_free() */
-}
-
int host1x_memory_context_list_init(struct host1x *host1x)
{
struct host1x_memory_context_list *cdl = &host1x->context_list;
struct device_node *node = host1x->dev->of_node;
struct host1x_memory_context *ctx;
+ struct device *dev;
unsigned int i;
int err;
@@ -44,42 +40,27 @@ int host1x_memory_context_list_init(struct host1x *host1x)
ctx->host = host1x;
- device_initialize(&ctx->dev);
-
/*
* Due to an issue with T194 NVENC, only 38 bits can be used.
* Anyway, 256GiB of IOVA ought to be enough for anyone.
*/
ctx->dma_mask = DMA_BIT_MASK(38);
- ctx->dev.dma_mask = &ctx->dma_mask;
- ctx->dev.coherent_dma_mask = ctx->dma_mask;
- dev_set_name(&ctx->dev, "host1x-ctx.%d", i);
- ctx->dev.bus = &host1x_context_device_bus_type;
- ctx->dev.parent = host1x->dev;
- ctx->dev.release = host1x_memory_context_release;
-
- ctx->dev.dma_parms = &ctx->dma_parms;
- dma_set_max_seg_size(&ctx->dev, UINT_MAX);
-
- err = device_add(&ctx->dev);
- if (err) {
+
+ dev = create_dma_context_bus_device(host1x->dev, NULL, ctx->dma_mask, &i);
+ if (IS_ERR(dev)) {
+ err = PTR_ERR(dev);
dev_err(host1x->dev, "could not add context device %d: %d\n", i, err);
- put_device(&ctx->dev);
goto unreg_devices;
}
- err = of_dma_configure_id(&ctx->dev, node, true, &i);
- if (err) {
- dev_err(host1x->dev, "IOMMU configuration failed for context device %d: %d\n",
- i, err);
- device_unregister(&ctx->dev);
- goto unreg_devices;
- }
+ ctx->dev = dev;
+ ctx->dev->dma_parms = &ctx->dma_parms;
+ dma_set_max_seg_size(ctx->dev, UINT_MAX);
- if (!tegra_dev_iommu_get_stream_id(&ctx->dev, &ctx->stream_id) ||
- !device_iommu_mapped(&ctx->dev)) {
+ if (!tegra_dev_iommu_get_stream_id(ctx->dev, &ctx->stream_id) ||
+ !device_iommu_mapped(ctx->dev)) {
dev_err(host1x->dev, "Context device %d has no IOMMU!\n", i);
- device_unregister(&ctx->dev);
+ device_unregister(ctx->dev);
/*
* This means that if IOMMU is disabled but context devices
@@ -96,7 +77,7 @@ int host1x_memory_context_list_init(struct host1x *host1x)
unreg_devices:
while (i--)
- device_unregister(&cdl->devs[i].dev);
+ device_unregister(cdl->devs[i].dev);
kfree(cdl->devs);
cdl->devs = NULL;
@@ -110,7 +91,7 @@ void host1x_memory_context_list_free(struct host1x_memory_context_list *cdl)
unsigned int i;
for (i = 0; i < cdl->len; i++)
- device_unregister(&cdl->devs[i].dev);
+ device_unregister(cdl->devs[i].dev);
kfree(cdl->devs);
cdl->len = 0;
@@ -132,7 +113,7 @@ struct host1x_memory_context *host1x_memory_context_alloc(struct host1x *host1x,
for (i = 0; i < cdl->len; i++) {
struct host1x_memory_context *cd = &cdl->devs[i];
- if (cd->dev.iommu->iommu_dev != dev->iommu->iommu_dev)
+ if (cd->dev->iommu->iommu_dev != dev->iommu->iommu_dev)
continue;
if (cd->owner == pid) {
diff --git a/drivers/gpu/host1x/context.h b/drivers/gpu/host1x/context.h
index 3e03bc1d3bac..558638c457d6 100644
--- a/drivers/gpu/host1x/context.h
+++ b/drivers/gpu/host1x/context.h
@@ -8,13 +8,12 @@
#ifndef __HOST1X_CONTEXT_H
#define __HOST1X_CONTEXT_H
+#include <linux/dma_context_bus.h>
#include <linux/mutex.h>
#include <linux/refcount.h>
struct host1x;
-extern struct bus_type host1x_context_device_bus_type;
-
struct host1x_memory_context_list {
struct mutex lock;
struct host1x_memory_context *devs;
diff --git a/drivers/gpu/host1x/context_bus.c b/drivers/gpu/host1x/context_bus.c
deleted file mode 100644
index 7cd0e1a5edd1..000000000000
--- a/drivers/gpu/host1x/context_bus.c
+++ /dev/null
@@ -1,26 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (c) 2021, NVIDIA Corporation.
- */
-
-#include <linux/device.h>
-#include <linux/of.h>
-
-const struct bus_type host1x_context_device_bus_type = {
- .name = "host1x-context",
-};
-EXPORT_SYMBOL_GPL(host1x_context_device_bus_type);
-
-static int __init host1x_context_device_bus_init(void)
-{
- int err;
-
- err = bus_register(&host1x_context_device_bus_type);
- if (err < 0) {
- pr_err("bus type registration failed: %d\n", err);
- return err;
- }
-
- return 0;
-}
-postcore_initcall(host1x_context_device_bus_init);
diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c
index 61c12ba78206..5d0fad1402eb 100644
--- a/drivers/iommu/iommu.c
+++ b/drivers/iommu/iommu.c
@@ -16,7 +16,7 @@
#include <linux/export.h>
#include <linux/slab.h>
#include <linux/errno.h>
-#include <linux/host1x_context_bus.h>
+#include <linux/dma_context_bus.h>
#include <linux/iommu.h>
#include <linux/iommufd.h>
#include <linux/idr.h>
@@ -173,8 +173,8 @@ static const struct bus_type * const iommu_buses[] = {
#ifdef CONFIG_FSL_MC_BUS
&fsl_mc_bus_type,
#endif
-#ifdef CONFIG_TEGRA_HOST1X_CONTEXT_BUS
- &host1x_context_device_bus_type,
+#ifdef CONFIG_DMA_CONTEXT_BUS
+ &dma_context_bus_type,
#endif
#ifdef CONFIG_CDX_BUS
&cdx_bus_type,
diff --git a/include/linux/host1x.h b/include/linux/host1x.h
index 1f5f55917d1c..30dbb3a71828 100644
--- a/include/linux/host1x.h
+++ b/include/linux/host1x.h
@@ -462,7 +462,7 @@ struct host1x_memory_context {
struct pid *owner;
struct device_dma_parameters dma_parms;
- struct device dev;
+ struct device *dev;
u64 dma_mask;
u32 stream_id;
};
diff --git a/include/linux/host1x_context_bus.h b/include/linux/host1x_context_bus.h
deleted file mode 100644
index c928cb432680..000000000000
--- a/include/linux/host1x_context_bus.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * Copyright (c) 2021, NVIDIA Corporation. All rights reserved.
- */
-
-#ifndef __LINUX_HOST1X_CONTEXT_BUS_H
-#define __LINUX_HOST1X_CONTEXT_BUS_H
-
-#include <linux/device.h>
-
-#ifdef CONFIG_TEGRA_HOST1X_CONTEXT_BUS
-extern const struct bus_type host1x_context_device_bus_type;
-#endif
-
-#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH v2 03/13] gpu: host1x: Migrate to generic dma context bus
2026-04-23 13:29 ` [PATCH v2 03/13] gpu: host1x: Migrate to " Vishnu Reddy
@ 2026-04-23 13:40 ` Greg Kroah-Hartman
0 siblings, 0 replies; 17+ messages in thread
From: Greg Kroah-Hartman @ 2026-04-23 13:40 UTC (permalink / raw)
To: Vishnu Reddy
Cc: Bryan O'Donoghue, Vikash Garodia, Dikshita Agarwal,
Abhinav Kumar, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Joerg Roedel, Will Deacon,
Robin Murphy, Bjorn Andersson, Konrad Dybcio, Stefan Schmidt,
Hans Verkuil, Rafael J. Wysocki, Danilo Krummrich, Thierry Reding,
Mikko Perttunen, David Airlie, Simona Vetter, Jonathan Hunter,
linux-media, linux-arm-msm, devicetree, linux-kernel, iommu,
driver-core, dri-devel, linux-tegra, Ekansh Gupta
On Thu, Apr 23, 2026 at 06:59:32PM +0530, Vishnu Reddy wrote:
> --- a/include/linux/host1x.h
> +++ b/include/linux/host1x.h
> @@ -462,7 +462,7 @@ struct host1x_memory_context {
> struct pid *owner;
>
> struct device_dma_parameters dma_parms;
> - struct device dev;
> + struct device *dev;
Ah, nice try, but no. You can't use a "generic" device for this type of
thing (i.e. your dma context bus device), as that's not what this device
really is. Add the needed logic to the bus this real device lives on,
don't try to work around it.
thanks,
greg k-h
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v2 04/13] dt-bindings: media: qcom,glymur-iris: Add glymur video codec
2026-04-23 13:29 [PATCH v2 00/13] media: iris: Add support for glymur platform Vishnu Reddy
` (2 preceding siblings ...)
2026-04-23 13:29 ` [PATCH v2 03/13] gpu: host1x: Migrate to " Vishnu Reddy
@ 2026-04-23 13:29 ` Vishnu Reddy
2026-04-23 13:29 ` [PATCH v2 05/13] media: iris: Add context bank hooks for platform specific initialization Vishnu Reddy
` (8 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Vishnu Reddy @ 2026-04-23 13:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vikash Garodia, Dikshita Agarwal,
Abhinav Kumar, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Joerg Roedel, Will Deacon,
Robin Murphy, Bjorn Andersson, Konrad Dybcio, Stefan Schmidt,
Hans Verkuil, Greg Kroah-Hartman, Rafael J. Wysocki,
Danilo Krummrich, Thierry Reding, Mikko Perttunen, David Airlie,
Simona Vetter, Jonathan Hunter
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel, iommu,
driver-core, dri-devel, linux-tegra, Vishnu Reddy
Add device tree binding for the Qualcomm Glymur Iris video codec. Glymur
is a new generation of video IP that introduces a dual-core architecture.
The second core brings its own power domain, clocks, and reset lines,
requiring additional power domains and clocks in the power sequence.
Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
---
.../bindings/media/qcom,glymur-iris.yaml | 220 +++++++++++++++++++++
include/dt-bindings/media/qcom,glymur-iris.h | 11 ++
2 files changed, 231 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/qcom,glymur-iris.yaml b/Documentation/devicetree/bindings/media/qcom,glymur-iris.yaml
new file mode 100644
index 000000000000..0fd8a8db01af
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/qcom,glymur-iris.yaml
@@ -0,0 +1,220 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/qcom,glymur-iris.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Glymur SoC Iris video encoder and decoder
+
+maintainers:
+ - Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
+
+description:
+ The Iris video processing unit on Qualcomm Glymur SoC is a video encode and
+ decode accelerator.
+
+properties:
+ compatible:
+ const: qcom,glymur-iris
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 9
+
+ clock-names:
+ items:
+ - const: iface
+ - const: core
+ - const: vcodec0_core
+ - const: iface1
+ - const: core_freerun
+ - const: vcodec0_core_freerun
+ - const: iface2
+ - const: vcodec1_core
+ - const: vcodec1_core_freerun
+
+ dma-coherent: true
+
+ firmware-name:
+ maxItems: 1
+
+ interconnects:
+ maxItems: 2
+
+ interconnect-names:
+ items:
+ - const: cpu-cfg
+ - const: video-mem
+
+ interrupts:
+ maxItems: 1
+
+ iommus:
+ maxItems: 4
+
+ iommu-map:
+ maxItems: 1
+
+ memory-region:
+ maxItems: 1
+
+ operating-points-v2: true
+ opp-table:
+ type: object
+
+ power-domains:
+ maxItems: 5
+
+ power-domain-names:
+ items:
+ - const: venus
+ - const: vcodec0
+ - const: mxc
+ - const: mmcx
+ - const: vcodec1
+
+ resets:
+ maxItems: 6
+
+ reset-names:
+ items:
+ - const: bus0
+ - const: bus1
+ - const: core
+ - const: vcodec0_core
+ - const: bus2
+ - const: vcodec1_core
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - dma-coherent
+ - interconnects
+ - interconnect-names
+ - interrupts
+ - iommus
+ - memory-region
+ - power-domains
+ - power-domain-names
+ - resets
+ - reset-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/media/qcom,glymur-iris.h>
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+
+ video-codec@aa00000 {
+ compatible = "qcom,glymur-iris";
+ reg = <0x0aa00000 0xf0000>;
+
+ clocks = <&gcc_video_axi0_clk>,
+ <&videocc_mvs0c_clk>,
+ <&videocc_mvs0_clk>,
+ <&gcc_video_axi0c_clk>,
+ <&videocc_mvs0c_freerun_clk>,
+ <&videocc_mvs0_freerun_clk>,
+ <&gcc_video_axi1_clk>,
+ <&videocc_mvs1_clk>,
+ <&videocc_mvs1_freerun_clk>;
+ clock-names = "iface",
+ "core",
+ "vcodec0_core",
+ "iface1",
+ "core_freerun",
+ "vcodec0_core_freerun",
+ "iface2",
+ "vcodec1_core",
+ "vcodec1_core_freerun";
+
+ dma-coherent;
+
+ interconnects = <&hsc_noc_master_appss_proc &config_noc_slave_venus_cfg>,
+ <&mmss_noc_master_video &mc_virt_slave_ebi1>;
+ interconnect-names = "cpu-cfg",
+ "video-mem";
+
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+
+ iommus = <&apps_smmu 0x1940 0x0>,
+ <&apps_smmu 0x1943 0x0>,
+ <&apps_smmu 0x1944 0x0>,
+ <&apps_smmu 0x19e0 0x0>;
+
+ iommu-map = <IOMMU_FID_IRIS_FIRMWARE &apps_smmu 0x19e2 0x1>;
+
+ memory-region = <&video_mem>;
+
+ operating-points-v2 = <&iris_opp_table>;
+
+ power-domains = <&videocc_mvs0c_gdsc>,
+ <&videocc_mvs0_gdsc>,
+ <&rpmhpd RPMHPD_MXC>,
+ <&rpmhpd RPMHPD_MMCX>,
+ <&videocc_mvs1_gdsc>;
+ power-domain-names = "venus",
+ "vcodec0",
+ "mxc",
+ "mmcx",
+ "vcodec1";
+
+ resets = <&gcc_video_axi0_clk_ares>,
+ <&gcc_video_axi0c_clk_ares>,
+ <&videocc_mvs0c_freerun_clk_ares>,
+ <&videocc_mvs0_freerun_clk_ares>,
+ <&gcc_video_axi1_clk_ares>,
+ <&videocc_mvs1_freerun_clk_ares>;
+ reset-names = "bus0",
+ "bus1",
+ "core",
+ "vcodec0_core",
+ "bus2",
+ "vcodec1_core";
+
+ iris_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-240000000 {
+ opp-hz = /bits/ 64 <240000000 240000000 360000000>;
+ required-opps = <&rpmhpd_opp_svs>,
+ <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-338000000 {
+ opp-hz = /bits/ 64 <338000000 338000000 507000000>;
+ required-opps = <&rpmhpd_opp_svs>,
+ <&rpmhpd_opp_svs>;
+ };
+
+ opp-366000000 {
+ opp-hz = /bits/ 64 <366000000 366000000 549000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>,
+ <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-444000000 {
+ opp-hz = /bits/ 64 <444000000 444000000 666000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>,
+ <&rpmhpd_opp_nom>;
+ };
+
+ opp-533333334 {
+ opp-hz = /bits/ 64 <533333334 533333334 800000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>,
+ <&rpmhpd_opp_turbo>;
+ };
+
+ opp-655000000 {
+ opp-hz = /bits/ 64 <655000000 655000000 982000000>;
+ required-opps = <&rpmhpd_opp_nom>,
+ <&rpmhpd_opp_turbo_l1>;
+ };
+ };
+ };
diff --git a/include/dt-bindings/media/qcom,glymur-iris.h b/include/dt-bindings/media/qcom,glymur-iris.h
new file mode 100644
index 000000000000..dcaa2bc21db5
--- /dev/null
+++ b/include/dt-bindings/media/qcom,glymur-iris.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_MEDIA_QCOM_GLYMUR_IRIS_H_
+#define _DT_BINDINGS_MEDIA_QCOM_GLYMUR_IRIS_H_
+
+#define IOMMU_FID_IRIS_FIRMWARE 0
+
+#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v2 05/13] media: iris: Add context bank hooks for platform specific initialization
2026-04-23 13:29 [PATCH v2 00/13] media: iris: Add support for glymur platform Vishnu Reddy
` (3 preceding siblings ...)
2026-04-23 13:29 ` [PATCH v2 04/13] dt-bindings: media: qcom,glymur-iris: Add glymur video codec Vishnu Reddy
@ 2026-04-23 13:29 ` Vishnu Reddy
2026-04-23 13:29 ` [PATCH v2 06/13] media: iris: Enable Secure PAS support with IOMMU managed by Linux Vishnu Reddy
` (7 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Vishnu Reddy @ 2026-04-23 13:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vikash Garodia, Dikshita Agarwal,
Abhinav Kumar, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Joerg Roedel, Will Deacon,
Robin Murphy, Bjorn Andersson, Konrad Dybcio, Stefan Schmidt,
Hans Verkuil, Greg Kroah-Hartman, Rafael J. Wysocki,
Danilo Krummrich, Thierry Reding, Mikko Perttunen, David Airlie,
Simona Vetter, Jonathan Hunter
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel, iommu,
driver-core, dri-devel, linux-tegra, Vishnu Reddy
The Glymur platform requires a dedicated firmware context bank device
which is mapped to the firmware stream ID to load the firmware.
Add init and deinit hooks in the platform data for context bank setup.
These hooks allow platform specific code to initialize and tear down
context banks.
Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
---
.../platform/qcom/iris/iris_platform_common.h | 2 ++
drivers/media/platform/qcom/iris/iris_probe.c | 23 +++++++++++++++++++++-
2 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
index 5a489917580e..55ff6137d9a9 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_common.h
+++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
@@ -219,6 +219,8 @@ struct iris_platform_data {
u32 (*get_vpu_buffer_size)(struct iris_inst *inst, enum iris_buffer_type buffer_type);
const struct vpu_ops *vpu_ops;
void (*set_preset_registers)(struct iris_core *core);
+ int (*init_cb_devs)(struct iris_core *core);
+ void (*deinit_cb_devs)(struct iris_core *core);
const struct icc_info *icc_tbl;
unsigned int icc_tbl_size;
const struct bw_info *bw_tbl_dec;
diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c
index ddaacda523ec..34751912f871 100644
--- a/drivers/media/platform/qcom/iris/iris_probe.c
+++ b/drivers/media/platform/qcom/iris/iris_probe.c
@@ -142,6 +142,20 @@ static int iris_init_resources(struct iris_core *core)
return iris_init_resets(core);
}
+static int iris_init_cb_devs(struct iris_core *core)
+{
+ if (core->iris_platform_data->init_cb_devs)
+ return core->iris_platform_data->init_cb_devs(core);
+
+ return 0;
+}
+
+static void iris_deinit_cb_devs(struct iris_core *core)
+{
+ if (core->iris_platform_data->deinit_cb_devs)
+ core->iris_platform_data->deinit_cb_devs(core);
+}
+
static int iris_register_video_device(struct iris_core *core, enum domain_type type)
{
struct video_device *vdev;
@@ -193,6 +207,7 @@ static void iris_remove(struct platform_device *pdev)
return;
iris_core_deinit(core);
+ iris_deinit_cb_devs(core);
video_unregister_device(core->vdev_dec);
video_unregister_device(core->vdev_enc);
@@ -259,11 +274,15 @@ static int iris_probe(struct platform_device *pdev)
if (ret)
return ret;
+ ret = iris_init_cb_devs(core);
+ if (ret)
+ return ret;
+
iris_session_init_caps(core);
ret = v4l2_device_register(dev, &core->v4l2_dev);
if (ret)
- return ret;
+ goto err_deinit_cb;
ret = iris_register_video_device(core, DECODER);
if (ret)
@@ -298,6 +317,8 @@ static int iris_probe(struct platform_device *pdev)
video_unregister_device(core->vdev_dec);
err_v4l2_unreg:
v4l2_device_unregister(&core->v4l2_dev);
+err_deinit_cb:
+ iris_deinit_cb_devs(core);
return ret;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v2 06/13] media: iris: Enable Secure PAS support with IOMMU managed by Linux
2026-04-23 13:29 [PATCH v2 00/13] media: iris: Add support for glymur platform Vishnu Reddy
` (4 preceding siblings ...)
2026-04-23 13:29 ` [PATCH v2 05/13] media: iris: Add context bank hooks for platform specific initialization Vishnu Reddy
@ 2026-04-23 13:29 ` Vishnu Reddy
2026-04-23 13:29 ` [PATCH v2 07/13] media: iris: Rename clock and power domain macros to use vcodec prefix Vishnu Reddy
` (6 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Vishnu Reddy @ 2026-04-23 13:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vikash Garodia, Dikshita Agarwal,
Abhinav Kumar, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Joerg Roedel, Will Deacon,
Robin Murphy, Bjorn Andersson, Konrad Dybcio, Stefan Schmidt,
Hans Verkuil, Greg Kroah-Hartman, Rafael J. Wysocki,
Danilo Krummrich, Thierry Reding, Mikko Perttunen, David Airlie,
Simona Vetter, Jonathan Hunter
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel, iommu,
driver-core, dri-devel, linux-tegra, Vishnu Reddy, Mukesh Ojha
From: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
Most Qualcomm platforms feature a proprietary hypervisor (such as Gunyah
or QHEE), which typically handles IOMMU configuration. This includes
mapping memory regions and device memory resources for remote processors
by intercepting qcom_scm_pas_auth_and_reset() calls. These mappings are
later removed during teardown. Additionally, SHM bridge setup is required
to enable memory protection for both remoteproc metadata and its memory
regions.
When the hypervisor is absent, the operating system must perform these
configurations instead.
Support for handling IOMMU and SHM setup in the absence of a hypervisor
is now in place. Extend the Iris driver to enable this functionality on
platforms where IOMMU is managed by Linux (i.e., non-Gunyah, non-QHEE).
Additionally, the Iris driver must map the firmware and its required
resources to the firmware SID, which is now specified via iommu-map in
the device tree.
Co-developed-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
---
drivers/media/platform/qcom/iris/iris_core.h | 4 ++
drivers/media/platform/qcom/iris/iris_firmware.c | 72 ++++++++++++++++++++----
2 files changed, 66 insertions(+), 10 deletions(-)
diff --git a/drivers/media/platform/qcom/iris/iris_core.h b/drivers/media/platform/qcom/iris/iris_core.h
index fb194c967ad4..b396c8cf595e 100644
--- a/drivers/media/platform/qcom/iris/iris_core.h
+++ b/drivers/media/platform/qcom/iris/iris_core.h
@@ -34,6 +34,8 @@ enum domain_type {
* struct iris_core - holds core parameters valid for all instances
*
* @dev: reference to device structure
+ * @fw_dev: reference to the context bank device used for firmware load
+ * @pas_ctx: SCM PAS context for authenticated firmware load and shutdown
* @reg_base: IO memory base address
* @irq: iris irq
* @v4l2_dev: a holder for v4l2 device structure
@@ -77,6 +79,8 @@ enum domain_type {
struct iris_core {
struct device *dev;
+ struct device *fw_dev;
+ struct qcom_scm_pas_context *pas_ctx;
void __iomem *reg_base;
int irq;
struct v4l2_device v4l2_dev;
diff --git a/drivers/media/platform/qcom/iris/iris_firmware.c b/drivers/media/platform/qcom/iris/iris_firmware.c
index 5f408024e967..0085dd7ec052 100644
--- a/drivers/media/platform/qcom/iris/iris_firmware.c
+++ b/drivers/media/platform/qcom/iris/iris_firmware.c
@@ -5,6 +5,7 @@
#include <linux/firmware.h>
#include <linux/firmware/qcom/qcom_scm.h>
+#include <linux/iommu.h>
#include <linux/of_address.h>
#include <linux/of_reserved_mem.h>
#include <linux/soc/qcom/mdt_loader.h>
@@ -13,12 +14,15 @@
#include "iris_firmware.h"
#define MAX_FIRMWARE_NAME_SIZE 128
+#define IRIS_FW_START_ADDR 0
static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_name)
{
+ struct device *fw_dev = core->fw_dev ? core->fw_dev : core->dev;
u32 pas_id = core->iris_platform_data->pas_id;
const struct firmware *firmware = NULL;
- struct device *dev = core->dev;
+ struct qcom_scm_pas_context *pas_ctx;
+ struct iommu_domain *domain;
struct resource res;
phys_addr_t mem_phys;
size_t res_size;
@@ -29,14 +33,18 @@ static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_name)
if (strlen(fw_name) >= MAX_FIRMWARE_NAME_SIZE - 4)
return -EINVAL;
- ret = of_reserved_mem_region_to_resource(dev->of_node, 0, &res);
+ ret = of_reserved_mem_region_to_resource(core->dev->of_node, 0, &res);
if (ret)
return ret;
mem_phys = res.start;
res_size = resource_size(&res);
- ret = request_firmware(&firmware, fw_name, dev);
+ pas_ctx = devm_qcom_scm_pas_context_alloc(fw_dev, pas_id, mem_phys, res_size);
+ if (IS_ERR(pas_ctx))
+ return PTR_ERR(pas_ctx);
+
+ ret = request_firmware(&firmware, fw_name, fw_dev);
if (ret)
return ret;
@@ -52,9 +60,27 @@ static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_name)
goto err_release_fw;
}
- ret = qcom_mdt_load(dev, firmware, fw_name,
- pas_id, mem_virt, mem_phys, res_size, NULL);
+ pas_ctx->use_tzmem = !!core->fw_dev;
+ ret = qcom_mdt_pas_load(pas_ctx, firmware, fw_name, mem_virt, NULL);
+ if (ret)
+ goto err_mem_unmap;
+
+ if (pas_ctx->use_tzmem) {
+ domain = iommu_get_domain_for_dev(fw_dev);
+ if (!domain) {
+ ret = -ENODEV;
+ goto err_mem_unmap;
+ }
+
+ ret = iommu_map(domain, IRIS_FW_START_ADDR, mem_phys, res_size,
+ IOMMU_READ | IOMMU_WRITE | IOMMU_PRIV, GFP_KERNEL);
+ if (ret)
+ goto err_mem_unmap;
+ }
+ core->pas_ctx = pas_ctx;
+
+err_mem_unmap:
memunmap(mem_virt);
err_release_fw:
release_firmware(firmware);
@@ -62,6 +88,18 @@ static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_name)
return ret;
}
+static void iris_fw_iommu_unmap(struct iris_core *core)
+{
+ struct iommu_domain *domain;
+
+ if (!core->pas_ctx->use_tzmem)
+ return;
+
+ domain = iommu_get_domain_for_dev(core->fw_dev);
+ if (domain)
+ iommu_unmap(domain, IRIS_FW_START_ADDR, core->pas_ctx->mem_size);
+}
+
int iris_fw_load(struct iris_core *core)
{
const struct tz_cp_config *cp_config;
@@ -79,10 +117,10 @@ int iris_fw_load(struct iris_core *core)
return -ENOMEM;
}
- ret = qcom_scm_pas_auth_and_reset(core->iris_platform_data->pas_id);
+ ret = qcom_scm_pas_prepare_and_auth_reset(core->pas_ctx);
if (ret) {
dev_err(core->dev, "auth and reset failed: %d\n", ret);
- return ret;
+ goto err_unmap;
}
for (i = 0; i < core->iris_platform_data->tz_cp_config_data_size; i++) {
@@ -93,17 +131,31 @@ int iris_fw_load(struct iris_core *core)
cp_config->cp_nonpixel_size);
if (ret) {
dev_err(core->dev, "qcom_scm_mem_protect_video_var failed: %d\n", ret);
- qcom_scm_pas_shutdown(core->iris_platform_data->pas_id);
- return ret;
+ goto err_pas_shutdown;
}
}
+ return 0;
+
+err_pas_shutdown:
+ qcom_scm_pas_shutdown(core->pas_ctx->pas_id);
+err_unmap:
+ iris_fw_iommu_unmap(core);
+
return ret;
}
int iris_fw_unload(struct iris_core *core)
{
- return qcom_scm_pas_shutdown(core->iris_platform_data->pas_id);
+ int ret;
+
+ ret = qcom_scm_pas_shutdown(core->pas_ctx->pas_id);
+ if (ret)
+ return ret;
+
+ iris_fw_iommu_unmap(core);
+
+ return ret;
}
int iris_set_hw_state(struct iris_core *core, bool resume)
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v2 07/13] media: iris: Rename clock and power domain macros to use vcodec prefix
2026-04-23 13:29 [PATCH v2 00/13] media: iris: Add support for glymur platform Vishnu Reddy
` (5 preceding siblings ...)
2026-04-23 13:29 ` [PATCH v2 06/13] media: iris: Enable Secure PAS support with IOMMU managed by Linux Vishnu Reddy
@ 2026-04-23 13:29 ` Vishnu Reddy
2026-04-23 13:29 ` [PATCH v2 08/13] media: iris: Use power domain type to look up pd_devs index Vishnu Reddy
` (5 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Vishnu Reddy @ 2026-04-23 13:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vikash Garodia, Dikshita Agarwal,
Abhinav Kumar, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Joerg Roedel, Will Deacon,
Robin Murphy, Bjorn Andersson, Konrad Dybcio, Stefan Schmidt,
Hans Verkuil, Greg Kroah-Hartman, Rafael J. Wysocki,
Danilo Krummrich, Thierry Reding, Mikko Perttunen, David Airlie,
Simona Vetter, Jonathan Hunter
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel, iommu,
driver-core, dri-devel, linux-tegra, Vishnu Reddy
The current clock and power domain enum names are too generic. Rename
them with a vcodec prefix to make the names more meaningful and to easily
accommodate vcodec1 enums for the secondary core for glymur platform.
No functional changes intended.
Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
---
.../platform/qcom/iris/iris_platform_common.h | 12 ++++----
.../media/platform/qcom/iris/iris_platform_gen1.c | 6 ++--
.../media/platform/qcom/iris/iris_platform_gen2.c | 6 ++--
.../platform/qcom/iris/iris_platform_sc7280.h | 10 +++----
.../platform/qcom/iris/iris_platform_sm8750.h | 12 ++++----
drivers/media/platform/qcom/iris/iris_vpu3x.c | 25 ++++++++--------
drivers/media/platform/qcom/iris/iris_vpu4x.c | 30 ++++++++++---------
drivers/media/platform/qcom/iris/iris_vpu_common.c | 35 +++++++++++-----------
8 files changed, 70 insertions(+), 66 deletions(-)
diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
index 55ff6137d9a9..30e9d4d288c6 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_common.h
+++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
@@ -49,14 +49,14 @@ extern const struct iris_platform_data sm8650_data;
extern const struct iris_platform_data sm8750_data;
enum platform_clk_type {
- IRIS_AXI_CLK, /* AXI0 in case of platforms with multiple AXI clocks */
+ IRIS_AXI_VCODEC_CLK,
IRIS_CTRL_CLK,
IRIS_AHB_CLK,
- IRIS_HW_CLK,
- IRIS_HW_AHB_CLK,
- IRIS_AXI1_CLK,
+ IRIS_VCODEC_CLK,
+ IRIS_VCODEC_AHB_CLK,
+ IRIS_AXI_CTRL_CLK,
IRIS_CTRL_FREERUN_CLK,
- IRIS_HW_FREERUN_CLK,
+ IRIS_VCODEC_FREERUN_CLK,
IRIS_BSE_HW_CLK,
IRIS_VPP0_HW_CLK,
IRIS_VPP1_HW_CLK,
@@ -206,7 +206,7 @@ struct icc_vote_data {
enum platform_pm_domain_type {
IRIS_CTRL_POWER_DOMAIN,
- IRIS_HW_POWER_DOMAIN,
+ IRIS_VCODEC_POWER_DOMAIN,
IRIS_VPP0_HW_POWER_DOMAIN,
IRIS_VPP1_HW_POWER_DOMAIN,
IRIS_APV_HW_POWER_DOMAIN,
diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen1.c b/drivers/media/platform/qcom/iris/iris_platform_gen1.c
index df8e6bf9430e..be6a631f8ede 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_gen1.c
+++ b/drivers/media/platform/qcom/iris/iris_platform_gen1.c
@@ -284,9 +284,9 @@ static const char * const sm8250_pmdomain_table[] = { "venus", "vcodec0" };
static const char * const sm8250_opp_pd_table[] = { "mx" };
static const struct platform_clk_data sm8250_clk_table[] = {
- {IRIS_AXI_CLK, "iface" },
- {IRIS_CTRL_CLK, "core" },
- {IRIS_HW_CLK, "vcodec0_core" },
+ {IRIS_AXI_VCODEC_CLK, "iface" },
+ {IRIS_CTRL_CLK, "core" },
+ {IRIS_VCODEC_CLK, "vcodec0_core" },
};
static const char * const sm8250_opp_clk_table[] = {
diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
index 5da90d47f9c6..47c6b650f0b4 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c
+++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
@@ -780,9 +780,9 @@ static const char * const sm8550_pmdomain_table[] = { "venus", "vcodec0" };
static const char * const sm8550_opp_pd_table[] = { "mxc", "mmcx" };
static const struct platform_clk_data sm8550_clk_table[] = {
- {IRIS_AXI_CLK, "iface" },
- {IRIS_CTRL_CLK, "core" },
- {IRIS_HW_CLK, "vcodec0_core" },
+ {IRIS_AXI_VCODEC_CLK, "iface" },
+ {IRIS_CTRL_CLK, "core" },
+ {IRIS_VCODEC_CLK, "vcodec0_core" },
};
static const char * const sm8550_opp_clk_table[] = {
diff --git a/drivers/media/platform/qcom/iris/iris_platform_sc7280.h b/drivers/media/platform/qcom/iris/iris_platform_sc7280.h
index 0ec8f334df67..6b783e524b81 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_sc7280.h
+++ b/drivers/media/platform/qcom/iris/iris_platform_sc7280.h
@@ -16,11 +16,11 @@ static const struct bw_info sc7280_bw_table_dec[] = {
static const char * const sc7280_opp_pd_table[] = { "cx" };
static const struct platform_clk_data sc7280_clk_table[] = {
- {IRIS_CTRL_CLK, "core" },
- {IRIS_AXI_CLK, "iface" },
- {IRIS_AHB_CLK, "bus" },
- {IRIS_HW_CLK, "vcodec_core" },
- {IRIS_HW_AHB_CLK, "vcodec_bus" },
+ {IRIS_CTRL_CLK, "core" },
+ {IRIS_AXI_VCODEC_CLK, "iface" },
+ {IRIS_AHB_CLK, "bus" },
+ {IRIS_VCODEC_CLK, "vcodec_core" },
+ {IRIS_VCODEC_AHB_CLK, "vcodec_bus" },
};
static const char * const sc7280_opp_clk_table[] = {
diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8750.h b/drivers/media/platform/qcom/iris/iris_platform_sm8750.h
index 719056656a5b..f843f13251c5 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_sm8750.h
+++ b/drivers/media/platform/qcom/iris/iris_platform_sm8750.h
@@ -11,12 +11,12 @@ static const char * const sm8750_clk_reset_table[] = {
};
static const struct platform_clk_data sm8750_clk_table[] = {
- {IRIS_AXI_CLK, "iface" },
- {IRIS_CTRL_CLK, "core" },
- {IRIS_HW_CLK, "vcodec0_core" },
- {IRIS_AXI1_CLK, "iface1" },
- {IRIS_CTRL_FREERUN_CLK, "core_freerun" },
- {IRIS_HW_FREERUN_CLK, "vcodec0_core_freerun" },
+ {IRIS_AXI_VCODEC_CLK, "iface" },
+ {IRIS_CTRL_CLK, "core" },
+ {IRIS_VCODEC_CLK, "vcodec0_core" },
+ {IRIS_AXI_CTRL_CLK, "iface1" },
+ {IRIS_CTRL_FREERUN_CLK, "core_freerun" },
+ {IRIS_VCODEC_FREERUN_CLK, "vcodec0_core_freerun" },
};
#endif
diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c
index fe4423b951b1..1f0a3a47d87f 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu3x.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c
@@ -209,7 +209,7 @@ static int iris_vpu33_power_off_controller(struct iris_core *core)
disable_power:
iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
- iris_disable_unprepare_clock(core, IRIS_AXI_CLK);
+ iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK);
return 0;
}
@@ -218,36 +218,37 @@ static int iris_vpu35_power_on_hw(struct iris_core *core)
{
int ret;
- ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);
+ ret = iris_enable_power_domains(core,
+ core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]);
if (ret)
return ret;
- ret = iris_prepare_enable_clock(core, IRIS_AXI_CLK);
+ ret = iris_prepare_enable_clock(core, IRIS_AXI_VCODEC_CLK);
if (ret)
goto err_disable_power;
- ret = iris_prepare_enable_clock(core, IRIS_HW_FREERUN_CLK);
+ ret = iris_prepare_enable_clock(core, IRIS_VCODEC_FREERUN_CLK);
if (ret)
goto err_disable_axi_clk;
- ret = iris_prepare_enable_clock(core, IRIS_HW_CLK);
+ ret = iris_prepare_enable_clock(core, IRIS_VCODEC_CLK);
if (ret)
goto err_disable_hw_free_clk;
- ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], true);
+ ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN], true);
if (ret)
goto err_disable_hw_clk;
return 0;
err_disable_hw_clk:
- iris_disable_unprepare_clock(core, IRIS_HW_CLK);
+ iris_disable_unprepare_clock(core, IRIS_VCODEC_CLK);
err_disable_hw_free_clk:
- iris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK);
+ iris_disable_unprepare_clock(core, IRIS_VCODEC_FREERUN_CLK);
err_disable_axi_clk:
- iris_disable_unprepare_clock(core, IRIS_AXI_CLK);
+ iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK);
err_disable_power:
- iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);
+ iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]);
return ret;
}
@@ -256,8 +257,8 @@ static void iris_vpu35_power_off_hw(struct iris_core *core)
{
iris_vpu33_power_off_hardware(core);
- iris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK);
- iris_disable_unprepare_clock(core, IRIS_AXI_CLK);
+ iris_disable_unprepare_clock(core, IRIS_VCODEC_FREERUN_CLK);
+ iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK);
}
const struct vpu_ops iris_vpu3_ops = {
diff --git a/drivers/media/platform/qcom/iris/iris_vpu4x.c b/drivers/media/platform/qcom/iris/iris_vpu4x.c
index a8db02ce5c5e..4082d331d2f3 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu4x.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu4x.c
@@ -27,7 +27,8 @@ static int iris_vpu4x_genpd_set_hwmode(struct iris_core *core, bool hw_mode, u32
{
int ret;
- ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], hw_mode);
+ ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN],
+ hw_mode);
if (ret)
return ret;
@@ -63,7 +64,7 @@ static int iris_vpu4x_genpd_set_hwmode(struct iris_core *core, bool hw_mode, u32
dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VPP0_HW_POWER_DOMAIN],
!hw_mode);
restore_hw_domain_mode:
- dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], !hw_mode);
+ dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN], !hw_mode);
return ret;
}
@@ -162,15 +163,15 @@ static int iris_vpu4x_enable_hardware_clocks(struct iris_core *core, u32 efuse_v
{
int ret;
- ret = iris_prepare_enable_clock(core, IRIS_AXI_CLK);
+ ret = iris_prepare_enable_clock(core, IRIS_AXI_VCODEC_CLK);
if (ret)
return ret;
- ret = iris_prepare_enable_clock(core, IRIS_HW_FREERUN_CLK);
+ ret = iris_prepare_enable_clock(core, IRIS_VCODEC_FREERUN_CLK);
if (ret)
goto disable_axi_clock;
- ret = iris_prepare_enable_clock(core, IRIS_HW_CLK);
+ ret = iris_prepare_enable_clock(core, IRIS_VCODEC_CLK);
if (ret)
goto disable_hw_free_run_clock;
@@ -198,11 +199,11 @@ static int iris_vpu4x_enable_hardware_clocks(struct iris_core *core, u32 efuse_v
disable_bse_hw_clock:
iris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK);
disable_hw_clock:
- iris_disable_unprepare_clock(core, IRIS_HW_CLK);
+ iris_disable_unprepare_clock(core, IRIS_VCODEC_CLK);
disable_hw_free_run_clock:
- iris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK);
+ iris_disable_unprepare_clock(core, IRIS_VCODEC_FREERUN_CLK);
disable_axi_clock:
- iris_disable_unprepare_clock(core, IRIS_AXI_CLK);
+ iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK);
return ret;
}
@@ -216,9 +217,9 @@ static void iris_vpu4x_disable_hardware_clocks(struct iris_core *core, u32 efuse
iris_disable_unprepare_clock(core, IRIS_VPP0_HW_CLK);
iris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK);
- iris_disable_unprepare_clock(core, IRIS_HW_CLK);
- iris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK);
- iris_disable_unprepare_clock(core, IRIS_AXI_CLK);
+ iris_disable_unprepare_clock(core, IRIS_VCODEC_CLK);
+ iris_disable_unprepare_clock(core, IRIS_VCODEC_FREERUN_CLK);
+ iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK);
}
static int iris_vpu4x_power_on_hardware(struct iris_core *core)
@@ -226,7 +227,8 @@ static int iris_vpu4x_power_on_hardware(struct iris_core *core)
u32 efuse_value = readl(core->reg_base + WRAPPER_EFUSE_MONITOR);
int ret;
- ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);
+ ret = iris_enable_power_domains(core,
+ core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]);
if (ret)
return ret;
@@ -278,7 +280,7 @@ static int iris_vpu4x_power_on_hardware(struct iris_core *core)
iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs
[IRIS_VPP0_HW_POWER_DOMAIN]);
disable_hw_power_domain:
- iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);
+ iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]);
return ret;
}
@@ -356,7 +358,7 @@ static void iris_vpu4x_power_off_hardware(struct iris_core *core)
iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs
[IRIS_VPP0_HW_POWER_DOMAIN]);
- iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);
+ iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]);
}
const struct vpu_ops iris_vpu4x_ops = {
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c
index bfd1e762c38e..006fd3ffc752 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_common.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c
@@ -213,7 +213,7 @@ int iris_vpu_power_off_controller(struct iris_core *core)
disable_power:
iris_disable_unprepare_clock(core, IRIS_AHB_CLK);
iris_disable_unprepare_clock(core, IRIS_CTRL_CLK);
- iris_disable_unprepare_clock(core, IRIS_AXI_CLK);
+ iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK);
iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
return 0;
@@ -221,10 +221,10 @@ int iris_vpu_power_off_controller(struct iris_core *core)
void iris_vpu_power_off_hw(struct iris_core *core)
{
- dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], false);
- iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);
- iris_disable_unprepare_clock(core, IRIS_HW_AHB_CLK);
- iris_disable_unprepare_clock(core, IRIS_HW_CLK);
+ dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN], false);
+ iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]);
+ iris_disable_unprepare_clock(core, IRIS_VCODEC_AHB_CLK);
+ iris_disable_unprepare_clock(core, IRIS_VCODEC_CLK);
}
void iris_vpu_power_off(struct iris_core *core)
@@ -251,7 +251,7 @@ int iris_vpu_power_on_controller(struct iris_core *core)
if (ret)
goto err_disable_power;
- ret = iris_prepare_enable_clock(core, IRIS_AXI_CLK);
+ ret = iris_prepare_enable_clock(core, IRIS_AXI_VCODEC_CLK);
if (ret)
goto err_disable_power;
@@ -268,7 +268,7 @@ int iris_vpu_power_on_controller(struct iris_core *core)
err_disable_ctrl_clock:
iris_disable_unprepare_clock(core, IRIS_CTRL_CLK);
err_disable_axi_clock:
- iris_disable_unprepare_clock(core, IRIS_AXI_CLK);
+ iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK);
err_disable_power:
iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
@@ -279,30 +279,31 @@ int iris_vpu_power_on_hw(struct iris_core *core)
{
int ret;
- ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);
+ ret = iris_enable_power_domains(core,
+ core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]);
if (ret)
return ret;
- ret = iris_prepare_enable_clock(core, IRIS_HW_CLK);
+ ret = iris_prepare_enable_clock(core, IRIS_VCODEC_CLK);
if (ret)
goto err_disable_power;
- ret = iris_prepare_enable_clock(core, IRIS_HW_AHB_CLK);
+ ret = iris_prepare_enable_clock(core, IRIS_VCODEC_AHB_CLK);
if (ret && ret != -ENOENT)
goto err_disable_hw_clock;
- ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], true);
+ ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN], true);
if (ret)
goto err_disable_hw_ahb_clock;
return 0;
err_disable_hw_ahb_clock:
- iris_disable_unprepare_clock(core, IRIS_HW_AHB_CLK);
+ iris_disable_unprepare_clock(core, IRIS_VCODEC_AHB_CLK);
err_disable_hw_clock:
- iris_disable_unprepare_clock(core, IRIS_HW_CLK);
+ iris_disable_unprepare_clock(core, IRIS_VCODEC_CLK);
err_disable_power:
- iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);
+ iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]);
return ret;
}
@@ -362,7 +363,7 @@ int iris_vpu35_vpu4x_power_off_controller(struct iris_core *core)
disable_power:
iris_disable_unprepare_clock(core, IRIS_CTRL_CLK);
iris_disable_unprepare_clock(core, IRIS_CTRL_FREERUN_CLK);
- iris_disable_unprepare_clock(core, IRIS_AXI1_CLK);
+ iris_disable_unprepare_clock(core, IRIS_AXI_CTRL_CLK);
iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
@@ -379,7 +380,7 @@ int iris_vpu35_vpu4x_power_on_controller(struct iris_core *core)
if (ret)
return ret;
- ret = iris_prepare_enable_clock(core, IRIS_AXI1_CLK);
+ ret = iris_prepare_enable_clock(core, IRIS_AXI_CTRL_CLK);
if (ret)
goto err_disable_power;
@@ -396,7 +397,7 @@ int iris_vpu35_vpu4x_power_on_controller(struct iris_core *core)
err_disable_ctrl_free_clk:
iris_disable_unprepare_clock(core, IRIS_CTRL_FREERUN_CLK);
err_disable_axi1_clk:
- iris_disable_unprepare_clock(core, IRIS_AXI1_CLK);
+ iris_disable_unprepare_clock(core, IRIS_AXI_CTRL_CLK);
err_disable_power:
iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v2 08/13] media: iris: Use power domain type to look up pd_devs index
2026-04-23 13:29 [PATCH v2 00/13] media: iris: Add support for glymur platform Vishnu Reddy
` (6 preceding siblings ...)
2026-04-23 13:29 ` [PATCH v2 07/13] media: iris: Rename clock and power domain macros to use vcodec prefix Vishnu Reddy
@ 2026-04-23 13:29 ` Vishnu Reddy
2026-04-23 13:29 ` [PATCH v2 09/13] media: iris: Add power sequence for Glymur Vishnu Reddy
` (4 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Vishnu Reddy @ 2026-04-23 13:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vikash Garodia, Dikshita Agarwal,
Abhinav Kumar, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Joerg Roedel, Will Deacon,
Robin Murphy, Bjorn Andersson, Konrad Dybcio, Stefan Schmidt,
Hans Verkuil, Greg Kroah-Hartman, Rafael J. Wysocki,
Danilo Krummrich, Thierry Reding, Mikko Perttunen, David Airlie,
Simona Vetter, Jonathan Hunter
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel, iommu,
driver-core, dri-devel, linux-tegra, Vishnu Reddy
The pmdomain_tbl was a array of strings holding only the power domain
names. Callers had to pass a pd_devs[] pointer indexed directly by the
platform_pm_domain_type enum value to iris_enable_power_domains() and
iris_disable_power_domains().
A future platform may need to introduce a new enum value that aliases
an existing one (e.g. IRIS_VCODEC1_POWER_DOMAIN aliasing the
IRIS_VPP0_HW_POWER_DOMAIN on Glymur), which would break the assumption
that enum values map 1:1 to pd_devs[] indices.
To fix this, replace the string array with a new struct platform_pd_data
that pairs each power domain name with its platform_pm_domain_type. Add
a helper iris_get_pd_index_by_type() that walks this table and returns
the correct pd_devs[] index for a given type.
Update iris_enable_power_domains() and iris_disable_power_domains()
to accept a platform_pm_domain_type instead of a struct device pointer.
They now call the helper internally to resolve the index, removing the
need for callers to do the index lookup themselves.
This prepares the driver for adding new platforms where power domain enum
values cannot be used directly as pd_devs[] indices.
Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
---
.../platform/qcom/iris/iris_platform_common.h | 9 +++-
.../media/platform/qcom/iris/iris_platform_gen1.c | 18 +++++---
.../media/platform/qcom/iris/iris_platform_gen2.c | 24 ++++++----
drivers/media/platform/qcom/iris/iris_probe.c | 4 +-
drivers/media/platform/qcom/iris/iris_resources.c | 44 +++++++++++++++++-
drivers/media/platform/qcom/iris/iris_resources.h | 6 ++-
drivers/media/platform/qcom/iris/iris_vpu3x.c | 9 ++--
drivers/media/platform/qcom/iris/iris_vpu4x.c | 52 ++++++++--------------
drivers/media/platform/qcom/iris/iris_vpu_common.c | 23 +++++-----
9 files changed, 117 insertions(+), 72 deletions(-)
diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
index 30e9d4d288c6..7d59e6364e9d 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_common.h
+++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
@@ -212,6 +212,12 @@ enum platform_pm_domain_type {
IRIS_APV_HW_POWER_DOMAIN,
};
+struct platform_pd_data {
+ enum platform_pm_domain_type *pd_types;
+ const char **pd_names;
+ u32 pd_count;
+};
+
struct iris_platform_data {
void (*init_hfi_command_ops)(struct iris_core *core);
void (*init_hfi_response_ops)(struct iris_core *core);
@@ -225,8 +231,7 @@ struct iris_platform_data {
unsigned int icc_tbl_size;
const struct bw_info *bw_tbl_dec;
unsigned int bw_tbl_dec_size;
- const char * const *pmdomain_tbl;
- unsigned int pmdomain_tbl_size;
+ const struct platform_pd_data *pmdomain_tbl;
const char * const *opp_pd_tbl;
unsigned int opp_pd_tbl_size;
const struct platform_clk_data *clk_tbl;
diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen1.c b/drivers/media/platform/qcom/iris/iris_platform_gen1.c
index be6a631f8ede..0ec73783bc10 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_gen1.c
+++ b/drivers/media/platform/qcom/iris/iris_platform_gen1.c
@@ -279,7 +279,17 @@ static const struct bw_info sm8250_bw_table_dec[] = {
{ ((1920 * 1080) / 256) * 30, 416000 },
};
-static const char * const sm8250_pmdomain_table[] = { "venus", "vcodec0" };
+static const struct platform_pd_data sm8250_pmdomain_table = {
+ .pd_types = (enum platform_pm_domain_type []) {
+ IRIS_CTRL_POWER_DOMAIN,
+ IRIS_VCODEC_POWER_DOMAIN,
+ },
+ .pd_names = (const char *[]) {
+ "venus",
+ "vcodec0",
+ },
+ .pd_count = 2,
+};
static const char * const sm8250_opp_pd_table[] = { "mx" };
@@ -350,8 +360,7 @@ const struct iris_platform_data sm8250_data = {
.clk_rst_tbl_size = ARRAY_SIZE(sm8250_clk_reset_table),
.bw_tbl_dec = sm8250_bw_table_dec,
.bw_tbl_dec_size = ARRAY_SIZE(sm8250_bw_table_dec),
- .pmdomain_tbl = sm8250_pmdomain_table,
- .pmdomain_tbl_size = ARRAY_SIZE(sm8250_pmdomain_table),
+ .pmdomain_tbl = &sm8250_pmdomain_table,
.opp_pd_tbl = sm8250_opp_pd_table,
.opp_pd_tbl_size = ARRAY_SIZE(sm8250_opp_pd_table),
.clk_tbl = sm8250_clk_table,
@@ -403,8 +412,7 @@ const struct iris_platform_data sc7280_data = {
.icc_tbl_size = ARRAY_SIZE(sm8250_icc_table),
.bw_tbl_dec = sc7280_bw_table_dec,
.bw_tbl_dec_size = ARRAY_SIZE(sc7280_bw_table_dec),
- .pmdomain_tbl = sm8250_pmdomain_table,
- .pmdomain_tbl_size = ARRAY_SIZE(sm8250_pmdomain_table),
+ .pmdomain_tbl = &sm8250_pmdomain_table,
.opp_pd_tbl = sc7280_opp_pd_table,
.opp_pd_tbl_size = ARRAY_SIZE(sc7280_opp_pd_table),
.clk_tbl = sc7280_clk_table,
diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
index 47c6b650f0b4..5862c89a4971 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c
+++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
@@ -775,7 +775,17 @@ static const struct bw_info sm8550_bw_table_dec[] = {
{ ((1920 * 1080) / 256) * 30, 294000 },
};
-static const char * const sm8550_pmdomain_table[] = { "venus", "vcodec0" };
+static const struct platform_pd_data sm8550_pmdomain_table = {
+ .pd_types = (enum platform_pm_domain_type []) {
+ IRIS_CTRL_POWER_DOMAIN,
+ IRIS_VCODEC_POWER_DOMAIN,
+ },
+ .pd_names = (const char *[]) {
+ "venus",
+ "vcodec0",
+ },
+ .pd_count = 2,
+};
static const char * const sm8550_opp_pd_table[] = { "mxc", "mmcx" };
@@ -934,8 +944,7 @@ const struct iris_platform_data sm8550_data = {
.clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table),
.bw_tbl_dec = sm8550_bw_table_dec,
.bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec),
- .pmdomain_tbl = sm8550_pmdomain_table,
- .pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table),
+ .pmdomain_tbl = &sm8550_pmdomain_table,
.opp_pd_tbl = sm8550_opp_pd_table,
.opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
.clk_tbl = sm8550_clk_table,
@@ -1039,8 +1048,7 @@ const struct iris_platform_data sm8650_data = {
.controller_rst_tbl_size = ARRAY_SIZE(sm8650_controller_reset_table),
.bw_tbl_dec = sm8550_bw_table_dec,
.bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec),
- .pmdomain_tbl = sm8550_pmdomain_table,
- .pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table),
+ .pmdomain_tbl = &sm8550_pmdomain_table,
.opp_pd_tbl = sm8550_opp_pd_table,
.opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
.clk_tbl = sm8550_clk_table,
@@ -1135,8 +1143,7 @@ const struct iris_platform_data sm8750_data = {
.clk_rst_tbl_size = ARRAY_SIZE(sm8750_clk_reset_table),
.bw_tbl_dec = sm8550_bw_table_dec,
.bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec),
- .pmdomain_tbl = sm8550_pmdomain_table,
- .pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table),
+ .pmdomain_tbl = &sm8550_pmdomain_table,
.opp_pd_tbl = sm8550_opp_pd_table,
.opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
.clk_tbl = sm8750_clk_table,
@@ -1235,8 +1242,7 @@ const struct iris_platform_data qcs8300_data = {
.clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table),
.bw_tbl_dec = sm8550_bw_table_dec,
.bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec),
- .pmdomain_tbl = sm8550_pmdomain_table,
- .pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table),
+ .pmdomain_tbl = &sm8550_pmdomain_table,
.opp_pd_tbl = sm8550_opp_pd_table,
.opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
.clk_tbl = sm8550_clk_table,
diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c
index 34751912f871..34c981be9bc1 100644
--- a/drivers/media/platform/qcom/iris/iris_probe.c
+++ b/drivers/media/platform/qcom/iris/iris_probe.c
@@ -43,8 +43,8 @@ static int iris_init_power_domains(struct iris_core *core)
int ret;
struct dev_pm_domain_attach_data iris_pd_data = {
- .pd_names = core->iris_platform_data->pmdomain_tbl,
- .num_pd_names = core->iris_platform_data->pmdomain_tbl_size,
+ .pd_names = core->iris_platform_data->pmdomain_tbl->pd_names,
+ .num_pd_names = core->iris_platform_data->pmdomain_tbl->pd_count,
.pd_flags = PD_FLAG_NO_DEV_LINK,
};
diff --git a/drivers/media/platform/qcom/iris/iris_resources.c b/drivers/media/platform/qcom/iris/iris_resources.c
index 773f6548370a..ae27488579d7 100644
--- a/drivers/media/platform/qcom/iris/iris_resources.c
+++ b/drivers/media/platform/qcom/iris/iris_resources.c
@@ -70,10 +70,43 @@ int iris_opp_set_rate(struct device *dev, unsigned long freq)
return dev_pm_opp_set_opp(dev, opp);
}
-int iris_enable_power_domains(struct iris_core *core, struct device *pd_dev)
+static int iris_get_pd_index_by_type(struct iris_core *core, enum platform_pm_domain_type pd_type)
{
+ const struct platform_pd_data *pd_tbl;
+ u32 pd_count, i;
+
+ pd_tbl = core->iris_platform_data->pmdomain_tbl;
+ pd_count = core->iris_platform_data->pmdomain_tbl->pd_count;
+
+ for (i = 0; i < pd_count; i++) {
+ if (pd_tbl->pd_types[i] == pd_type)
+ return i;
+ }
+
+ return -EINVAL;
+}
+
+int iris_genpd_set_hwmode(struct iris_core *core, enum platform_pm_domain_type pd_type, bool hwmode)
+{
+ int pd_index = iris_get_pd_index_by_type(core, pd_type);
+
+ if (pd_index < 0)
+ return pd_index;
+
+ return dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[pd_index], hwmode);
+}
+
+int iris_enable_power_domains(struct iris_core *core, enum platform_pm_domain_type pd_type)
+{
+ int pd_index = iris_get_pd_index_by_type(core, pd_type);
+ struct device *pd_dev;
int ret;
+ if (pd_index < 0)
+ return pd_index;
+
+ pd_dev = core->pmdomain_tbl->pd_devs[pd_index];
+
ret = iris_opp_set_rate(core->dev, ULONG_MAX);
if (ret)
return ret;
@@ -85,10 +118,17 @@ int iris_enable_power_domains(struct iris_core *core, struct device *pd_dev)
return ret;
}
-int iris_disable_power_domains(struct iris_core *core, struct device *pd_dev)
+int iris_disable_power_domains(struct iris_core *core, enum platform_pm_domain_type pd_type)
{
+ int pd_index = iris_get_pd_index_by_type(core, pd_type);
+ struct device *pd_dev;
int ret;
+ if (pd_index < 0)
+ return pd_index;
+
+ pd_dev = core->pmdomain_tbl->pd_devs[pd_index];
+
ret = iris_opp_set_rate(core->dev, 0);
if (ret)
return ret;
diff --git a/drivers/media/platform/qcom/iris/iris_resources.h b/drivers/media/platform/qcom/iris/iris_resources.h
index 6bfbd2dc6db0..d5692e4694b1 100644
--- a/drivers/media/platform/qcom/iris/iris_resources.h
+++ b/drivers/media/platform/qcom/iris/iris_resources.h
@@ -9,11 +9,13 @@
struct iris_core;
int iris_opp_set_rate(struct device *dev, unsigned long freq);
-int iris_enable_power_domains(struct iris_core *core, struct device *pd_dev);
-int iris_disable_power_domains(struct iris_core *core, struct device *pd_dev);
+int iris_enable_power_domains(struct iris_core *core, enum platform_pm_domain_type pd_type);
+int iris_disable_power_domains(struct iris_core *core, enum platform_pm_domain_type pd_type);
int iris_unset_icc_bw(struct iris_core *core);
int iris_set_icc_bw(struct iris_core *core, unsigned long icc_bw);
int iris_disable_unprepare_clock(struct iris_core *core, enum platform_clk_type clk_type);
int iris_prepare_enable_clock(struct iris_core *core, enum platform_clk_type clk_type);
+int iris_genpd_set_hwmode(struct iris_core *core, enum platform_pm_domain_type pd_type,
+ bool hwmode);
#endif
diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c
index 1f0a3a47d87f..a9f43dbfc695 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu3x.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c
@@ -208,7 +208,7 @@ static int iris_vpu33_power_off_controller(struct iris_core *core)
iris_disable_unprepare_clock(core, IRIS_CTRL_CLK);
disable_power:
- iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
+ iris_disable_power_domains(core, IRIS_CTRL_POWER_DOMAIN);
iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK);
return 0;
@@ -218,8 +218,7 @@ static int iris_vpu35_power_on_hw(struct iris_core *core)
{
int ret;
- ret = iris_enable_power_domains(core,
- core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]);
+ ret = iris_enable_power_domains(core, IRIS_VCODEC_POWER_DOMAIN);
if (ret)
return ret;
@@ -235,7 +234,7 @@ static int iris_vpu35_power_on_hw(struct iris_core *core)
if (ret)
goto err_disable_hw_free_clk;
- ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN], true);
+ ret = iris_genpd_set_hwmode(core, IRIS_VCODEC_POWER_DOMAIN, true);
if (ret)
goto err_disable_hw_clk;
@@ -248,7 +247,7 @@ static int iris_vpu35_power_on_hw(struct iris_core *core)
err_disable_axi_clk:
iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK);
err_disable_power:
- iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]);
+ iris_disable_power_domains(core, IRIS_VCODEC_POWER_DOMAIN);
return ret;
}
diff --git a/drivers/media/platform/qcom/iris/iris_vpu4x.c b/drivers/media/platform/qcom/iris/iris_vpu4x.c
index 4082d331d2f3..7b8922d8aec7 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu4x.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu4x.c
@@ -27,28 +27,24 @@ static int iris_vpu4x_genpd_set_hwmode(struct iris_core *core, bool hw_mode, u32
{
int ret;
- ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN],
- hw_mode);
+ ret = iris_genpd_set_hwmode(core, IRIS_VCODEC_POWER_DOMAIN, hw_mode);
if (ret)
return ret;
if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT)) {
- ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs
- [IRIS_VPP0_HW_POWER_DOMAIN], hw_mode);
+ ret = iris_genpd_set_hwmode(core, IRIS_VPP0_HW_POWER_DOMAIN, hw_mode);
if (ret)
goto restore_hw_domain_mode;
}
if (!(efuse_value & DISABLE_VIDEO_VPP1_BIT)) {
- ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs
- [IRIS_VPP1_HW_POWER_DOMAIN], hw_mode);
+ ret = iris_genpd_set_hwmode(core, IRIS_VPP1_HW_POWER_DOMAIN, hw_mode);
if (ret)
goto restore_vpp0_domain_mode;
}
if (!(efuse_value & DISABLE_VIDEO_APV_BIT)) {
- ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs
- [IRIS_APV_HW_POWER_DOMAIN], hw_mode);
+ ret = iris_genpd_set_hwmode(core, IRIS_APV_HW_POWER_DOMAIN, hw_mode);
if (ret)
goto restore_vpp1_domain_mode;
}
@@ -57,14 +53,12 @@ static int iris_vpu4x_genpd_set_hwmode(struct iris_core *core, bool hw_mode, u32
restore_vpp1_domain_mode:
if (!(efuse_value & DISABLE_VIDEO_VPP1_BIT))
- dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VPP1_HW_POWER_DOMAIN],
- !hw_mode);
+ iris_genpd_set_hwmode(core, IRIS_VPP1_HW_POWER_DOMAIN, !hw_mode);
restore_vpp0_domain_mode:
if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT))
- dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VPP0_HW_POWER_DOMAIN],
- !hw_mode);
+ iris_genpd_set_hwmode(core, IRIS_VPP0_HW_POWER_DOMAIN, !hw_mode);
restore_hw_domain_mode:
- dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN], !hw_mode);
+ iris_genpd_set_hwmode(core, IRIS_VCODEC_POWER_DOMAIN, !hw_mode);
return ret;
}
@@ -73,8 +67,7 @@ static int iris_vpu4x_power_on_apv(struct iris_core *core)
{
int ret;
- ret = iris_enable_power_domains(core,
- core->pmdomain_tbl->pd_devs[IRIS_APV_HW_POWER_DOMAIN]);
+ ret = iris_enable_power_domains(core, IRIS_APV_HW_POWER_DOMAIN);
if (ret)
return ret;
@@ -85,7 +78,7 @@ static int iris_vpu4x_power_on_apv(struct iris_core *core)
return 0;
disable_apv_hw_power_domain:
- iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_APV_HW_POWER_DOMAIN]);
+ iris_disable_power_domains(core, IRIS_APV_HW_POWER_DOMAIN);
return ret;
}
@@ -140,7 +133,7 @@ static void iris_vpu4x_power_off_apv(struct iris_core *core)
disable_clocks_and_power:
iris_disable_unprepare_clock(core, IRIS_APV_HW_CLK);
- iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_APV_HW_POWER_DOMAIN]);
+ iris_disable_power_domains(core, IRIS_APV_HW_POWER_DOMAIN);
}
static void iris_vpu4x_ahb_sync_reset_apv(struct iris_core *core)
@@ -227,21 +220,18 @@ static int iris_vpu4x_power_on_hardware(struct iris_core *core)
u32 efuse_value = readl(core->reg_base + WRAPPER_EFUSE_MONITOR);
int ret;
- ret = iris_enable_power_domains(core,
- core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]);
+ ret = iris_enable_power_domains(core, IRIS_VCODEC_POWER_DOMAIN);
if (ret)
return ret;
if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT)) {
- ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs
- [IRIS_VPP0_HW_POWER_DOMAIN]);
+ ret = iris_enable_power_domains(core, IRIS_VPP0_HW_POWER_DOMAIN);
if (ret)
goto disable_hw_power_domain;
}
if (!(efuse_value & DISABLE_VIDEO_VPP1_BIT)) {
- ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs
- [IRIS_VPP1_HW_POWER_DOMAIN]);
+ ret = iris_enable_power_domains(core, IRIS_VPP1_HW_POWER_DOMAIN);
if (ret)
goto disable_vpp0_power_domain;
}
@@ -273,14 +263,12 @@ static int iris_vpu4x_power_on_hardware(struct iris_core *core)
iris_vpu4x_disable_hardware_clocks(core, efuse_value);
disable_vpp1_power_domain:
if (!(efuse_value & DISABLE_VIDEO_VPP1_BIT))
- iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs
- [IRIS_VPP1_HW_POWER_DOMAIN]);
+ iris_disable_power_domains(core, IRIS_VPP1_HW_POWER_DOMAIN);
disable_vpp0_power_domain:
if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT))
- iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs
- [IRIS_VPP0_HW_POWER_DOMAIN]);
+ iris_disable_power_domains(core, IRIS_VPP0_HW_POWER_DOMAIN);
disable_hw_power_domain:
- iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]);
+ iris_disable_power_domains(core, IRIS_VCODEC_POWER_DOMAIN);
return ret;
}
@@ -351,14 +339,12 @@ static void iris_vpu4x_power_off_hardware(struct iris_core *core)
iris_vpu4x_disable_hardware_clocks(core, efuse_value);
if (!(efuse_value & DISABLE_VIDEO_VPP1_BIT))
- iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs
- [IRIS_VPP1_HW_POWER_DOMAIN]);
+ iris_disable_power_domains(core, IRIS_VPP1_HW_POWER_DOMAIN);
if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT))
- iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs
- [IRIS_VPP0_HW_POWER_DOMAIN]);
+ iris_disable_power_domains(core, IRIS_VPP0_HW_POWER_DOMAIN);
- iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]);
+ iris_disable_power_domains(core, IRIS_VCODEC_POWER_DOMAIN);
}
const struct vpu_ops iris_vpu4x_ops = {
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c
index 006fd3ffc752..74b4dccd6a66 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_common.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c
@@ -214,15 +214,15 @@ int iris_vpu_power_off_controller(struct iris_core *core)
iris_disable_unprepare_clock(core, IRIS_AHB_CLK);
iris_disable_unprepare_clock(core, IRIS_CTRL_CLK);
iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK);
- iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
+ iris_disable_power_domains(core, IRIS_CTRL_POWER_DOMAIN);
return 0;
}
void iris_vpu_power_off_hw(struct iris_core *core)
{
- dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN], false);
- iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]);
+ iris_genpd_set_hwmode(core, IRIS_VCODEC_POWER_DOMAIN, false);
+ iris_disable_power_domains(core, IRIS_VCODEC_POWER_DOMAIN);
iris_disable_unprepare_clock(core, IRIS_VCODEC_AHB_CLK);
iris_disable_unprepare_clock(core, IRIS_VCODEC_CLK);
}
@@ -243,7 +243,7 @@ int iris_vpu_power_on_controller(struct iris_core *core)
u32 rst_tbl_size = core->iris_platform_data->clk_rst_tbl_size;
int ret;
- ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
+ ret = iris_enable_power_domains(core, IRIS_CTRL_POWER_DOMAIN);
if (ret)
return ret;
@@ -270,7 +270,7 @@ int iris_vpu_power_on_controller(struct iris_core *core)
err_disable_axi_clock:
iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK);
err_disable_power:
- iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
+ iris_disable_power_domains(core, IRIS_CTRL_POWER_DOMAIN);
return ret;
}
@@ -279,8 +279,7 @@ int iris_vpu_power_on_hw(struct iris_core *core)
{
int ret;
- ret = iris_enable_power_domains(core,
- core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]);
+ ret = iris_enable_power_domains(core, IRIS_VCODEC_POWER_DOMAIN);
if (ret)
return ret;
@@ -292,7 +291,7 @@ int iris_vpu_power_on_hw(struct iris_core *core)
if (ret && ret != -ENOENT)
goto err_disable_hw_clock;
- ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN], true);
+ ret = iris_genpd_set_hwmode(core, IRIS_VCODEC_POWER_DOMAIN, true);
if (ret)
goto err_disable_hw_ahb_clock;
@@ -303,7 +302,7 @@ int iris_vpu_power_on_hw(struct iris_core *core)
err_disable_hw_clock:
iris_disable_unprepare_clock(core, IRIS_VCODEC_CLK);
err_disable_power:
- iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]);
+ iris_disable_power_domains(core, IRIS_VCODEC_POWER_DOMAIN);
return ret;
}
@@ -365,7 +364,7 @@ int iris_vpu35_vpu4x_power_off_controller(struct iris_core *core)
iris_disable_unprepare_clock(core, IRIS_CTRL_FREERUN_CLK);
iris_disable_unprepare_clock(core, IRIS_AXI_CTRL_CLK);
- iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
+ iris_disable_power_domains(core, IRIS_CTRL_POWER_DOMAIN);
reset_control_bulk_reset(clk_rst_tbl_size, core->resets);
@@ -376,7 +375,7 @@ int iris_vpu35_vpu4x_power_on_controller(struct iris_core *core)
{
int ret;
- ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
+ ret = iris_enable_power_domains(core, IRIS_CTRL_POWER_DOMAIN);
if (ret)
return ret;
@@ -399,7 +398,7 @@ int iris_vpu35_vpu4x_power_on_controller(struct iris_core *core)
err_disable_axi1_clk:
iris_disable_unprepare_clock(core, IRIS_AXI_CTRL_CLK);
err_disable_power:
- iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
+ iris_disable_power_domains(core, IRIS_CTRL_POWER_DOMAIN);
return ret;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v2 09/13] media: iris: Add power sequence for Glymur
2026-04-23 13:29 [PATCH v2 00/13] media: iris: Add support for glymur platform Vishnu Reddy
` (7 preceding siblings ...)
2026-04-23 13:29 ` [PATCH v2 08/13] media: iris: Use power domain type to look up pd_devs index Vishnu Reddy
@ 2026-04-23 13:29 ` Vishnu Reddy
2026-04-23 13:29 ` [PATCH v2 10/13] media: iris: Add support to select core for dual core platforms Vishnu Reddy
` (3 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Vishnu Reddy @ 2026-04-23 13:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vikash Garodia, Dikshita Agarwal,
Abhinav Kumar, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Joerg Roedel, Will Deacon,
Robin Murphy, Bjorn Andersson, Konrad Dybcio, Stefan Schmidt,
Hans Verkuil, Greg Kroah-Hartman, Rafael J. Wysocki,
Danilo Krummrich, Thierry Reding, Mikko Perttunen, David Airlie,
Simona Vetter, Jonathan Hunter
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel, iommu,
driver-core, dri-devel, linux-tegra, Vishnu Reddy
Glymur has a secondary video codec core (vcodec1), equivalent to the
primary core (vcodec0), but with independent power domains, clocks,
and reset lines. Reuse the existing code wherever possible and add
power sequence for vcodec1.
Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
---
.../platform/qcom/iris/iris_platform_common.h | 4 +
drivers/media/platform/qcom/iris/iris_vpu3x.c | 122 +++++++++++++++++++++
drivers/media/platform/qcom/iris/iris_vpu_common.h | 1 +
.../platform/qcom/iris/iris_vpu_register_defines.h | 7 ++
4 files changed, 134 insertions(+)
diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
index 7d59e6364e9d..8995136ad29e 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_common.h
+++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
@@ -61,6 +61,9 @@ enum platform_clk_type {
IRIS_VPP0_HW_CLK,
IRIS_VPP1_HW_CLK,
IRIS_APV_HW_CLK,
+ IRIS_AXI_VCODEC1_CLK,
+ IRIS_VCODEC1_CLK,
+ IRIS_VCODEC1_FREERUN_CLK,
};
struct platform_clk_data {
@@ -210,6 +213,7 @@ enum platform_pm_domain_type {
IRIS_VPP0_HW_POWER_DOMAIN,
IRIS_VPP1_HW_POWER_DOMAIN,
IRIS_APV_HW_POWER_DOMAIN,
+ IRIS_VCODEC1_POWER_DOMAIN,
};
struct platform_pd_data {
diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c
index a9f43dbfc695..bd70d1c0ea76 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu3x.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c
@@ -27,6 +27,16 @@ static bool iris_vpu3x_hw_power_collapsed(struct iris_core *core)
return pwr_status ? false : true;
}
+static bool iris_vpu36_hw1_power_collapsed(struct iris_core *core)
+{
+ u32 value, pwr_status;
+
+ value = readl(core->reg_base + WRAPPER_CORE_POWER_STATUS);
+ pwr_status = value & BIT(4);
+
+ return !pwr_status;
+}
+
static void iris_vpu3_power_off_hardware(struct iris_core *core)
{
u32 reg_val = 0, value, i;
@@ -260,6 +270,110 @@ static void iris_vpu35_power_off_hw(struct iris_core *core)
iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK);
}
+static int iris_vpu36_power_on_hw1(struct iris_core *core)
+{
+ int ret;
+
+ ret = iris_enable_power_domains(core, IRIS_VCODEC1_POWER_DOMAIN);
+ if (ret)
+ return ret;
+
+ ret = iris_prepare_enable_clock(core, IRIS_AXI_VCODEC1_CLK);
+ if (ret)
+ goto err_disable_hw1_power;
+
+ ret = iris_prepare_enable_clock(core, IRIS_VCODEC1_FREERUN_CLK);
+ if (ret)
+ goto err_disable_axi1_clk;
+
+ ret = iris_prepare_enable_clock(core, IRIS_VCODEC1_CLK);
+ if (ret)
+ goto err_disable_hw1_free_clk;
+
+ ret = iris_genpd_set_hwmode(core, IRIS_VCODEC1_POWER_DOMAIN, true);
+ if (ret)
+ goto err_disable_hw1_clk;
+
+ return 0;
+
+err_disable_hw1_clk:
+ iris_disable_unprepare_clock(core, IRIS_VCODEC1_CLK);
+err_disable_hw1_free_clk:
+ iris_disable_unprepare_clock(core, IRIS_VCODEC1_FREERUN_CLK);
+err_disable_axi1_clk:
+ iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC1_CLK);
+err_disable_hw1_power:
+ iris_disable_power_domains(core, IRIS_VCODEC1_POWER_DOMAIN);
+
+ return ret;
+}
+
+static int iris_vpu36_power_on_hw(struct iris_core *core)
+{
+ int ret;
+
+ ret = iris_vpu35_power_on_hw(core);
+ if (ret)
+ return ret;
+
+ ret = iris_vpu36_power_on_hw1(core);
+ if (ret)
+ goto err_power_off_hw;
+
+ return 0;
+
+err_power_off_hw:
+ iris_vpu35_power_off_hw(core);
+
+ return ret;
+}
+
+static void iris_vpu36_power_off_hw1(struct iris_core *core)
+{
+ u32 value, i;
+ int ret;
+
+ if (iris_vpu36_hw1_power_collapsed(core))
+ goto disable_power;
+
+ value = readl(core->reg_base + WRAPPER_CORE_CLOCK_CONFIG);
+ if (value)
+ writel(CORE_CLK_RUN, core->reg_base + WRAPPER_CORE_CLOCK_CONFIG);
+
+ for (i = 0; i < core->iris_platform_data->num_vpp_pipe; i++) {
+ ret = readl_poll_timeout(core->reg_base + VCODEC1_SS_IDLE_STATUSN + 4 * i,
+ value, value & DMA_NOC_IDLE, 2000, 20000);
+ if (ret)
+ goto disable_power;
+ }
+
+ writel(REQ_VCODEC1_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL);
+ ret = readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATUS,
+ value, value & NOC_LPI_VCODEC1_STATUS_DONE, 2000, 20000);
+ if (ret)
+ goto disable_power;
+
+ writel(0, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL);
+
+ writel(VCODEC1_BRIDGE_SW_RESET | VCODEC1_BRIDGE_HW_RESET_DISABLE, core->reg_base +
+ CPU_CS_AHB_BRIDGE_SYNC_RESET);
+ writel(VCODEC1_BRIDGE_HW_RESET_DISABLE, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET);
+ writel(0x0, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET);
+
+disable_power:
+ iris_genpd_set_hwmode(core, IRIS_VCODEC1_POWER_DOMAIN, false);
+ iris_disable_unprepare_clock(core, IRIS_VCODEC1_CLK);
+ iris_disable_unprepare_clock(core, IRIS_VCODEC1_FREERUN_CLK);
+ iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC1_CLK);
+ iris_disable_power_domains(core, IRIS_VCODEC1_POWER_DOMAIN);
+}
+
+static void iris_vpu36_power_off_hw(struct iris_core *core)
+{
+ iris_vpu35_power_off_hw(core);
+ iris_vpu36_power_off_hw1(core);
+}
+
const struct vpu_ops iris_vpu3_ops = {
.power_off_hw = iris_vpu3_power_off_hardware,
.power_on_hw = iris_vpu_power_on_hw,
@@ -284,3 +398,11 @@ const struct vpu_ops iris_vpu35_ops = {
.program_bootup_registers = iris_vpu35_vpu4x_program_bootup_registers,
.calc_freq = iris_vpu3x_vpu4x_calculate_frequency,
};
+
+const struct vpu_ops iris_vpu36_ops = {
+ .power_off_hw = iris_vpu36_power_off_hw,
+ .power_on_hw = iris_vpu36_power_on_hw,
+ .power_off_controller = iris_vpu35_vpu4x_power_off_controller,
+ .power_on_controller = iris_vpu35_vpu4x_power_on_controller,
+ .calc_freq = iris_vpu3x_vpu4x_calculate_frequency,
+};
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/media/platform/qcom/iris/iris_vpu_common.h
index f6dffc613b82..99e75fb4b10d 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_common.h
+++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h
@@ -12,6 +12,7 @@ extern const struct vpu_ops iris_vpu2_ops;
extern const struct vpu_ops iris_vpu3_ops;
extern const struct vpu_ops iris_vpu33_ops;
extern const struct vpu_ops iris_vpu35_ops;
+extern const struct vpu_ops iris_vpu36_ops;
extern const struct vpu_ops iris_vpu4x_ops;
struct vpu_ops {
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
index 72168b9ffa73..37f234484f1b 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
+++ b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
@@ -7,6 +7,7 @@
#define __IRIS_VPU_REGISTER_DEFINES_H__
#define VCODEC_BASE_OFFS 0x00000000
+#define VCODEC1_BASE_OFFS 0x00040000
#define AON_MVP_NOC_RESET 0x0001F000
#define CPU_BASE_OFFS 0x000A0000
#define WRAPPER_BASE_OFFS 0x000B0000
@@ -14,6 +15,8 @@
#define AON_BASE_OFFS 0x000E0000
#define VCODEC_SS_IDLE_STATUSN (VCODEC_BASE_OFFS + 0x70)
+#define VCODEC1_SS_IDLE_STATUSN (VCODEC1_BASE_OFFS + 0x70)
+#define DMA_NOC_IDLE BIT(22)
#define AON_WRAPPER_MVP_NOC_RESET_REQ (AON_MVP_NOC_RESET + 0x000)
#define VIDEO_NOC_RESET_REQ (BIT(0) | BIT(1))
@@ -35,6 +38,8 @@
#define CPU_CS_AHB_BRIDGE_SYNC_RESET (CPU_CS_BASE_OFFS + 0x160)
#define CORE_BRIDGE_SW_RESET BIT(0)
#define CORE_BRIDGE_HW_RESET_DISABLE BIT(1)
+#define VCODEC1_BRIDGE_SW_RESET BIT(2)
+#define VCODEC1_BRIDGE_HW_RESET_DISABLE BIT(3)
#define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168)
#define MSK_SIGNAL_FROM_TENSILICA BIT(0)
@@ -52,11 +57,13 @@
#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58)
#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C)
#define REQ_POWER_DOWN_PREP BIT(0)
+#define REQ_VCODEC1_POWER_DOWN_PREP BIT(1)
#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60)
#define NOC_LPI_STATUS_DONE BIT(0) /* Indicates the NOC handshake is complete */
#define NOC_LPI_STATUS_DENY BIT(1) /* Indicates the NOC handshake is denied */
#define NOC_LPI_STATUS_ACTIVE BIT(2) /* Indicates the NOC is active */
+#define NOC_LPI_VCODEC1_STATUS_DONE BIT(8)
#define WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0 (WRAPPER_BASE_OFFS + 0x78)
#define WRAPPER_CORE_POWER_STATUS (WRAPPER_BASE_OFFS + 0x80)
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v2 10/13] media: iris: Add support to select core for dual core platforms
2026-04-23 13:29 [PATCH v2 00/13] media: iris: Add support for glymur platform Vishnu Reddy
` (8 preceding siblings ...)
2026-04-23 13:29 ` [PATCH v2 09/13] media: iris: Add power sequence for Glymur Vishnu Reddy
@ 2026-04-23 13:29 ` Vishnu Reddy
2026-04-23 13:29 ` [PATCH v2 11/13] media: iris: Select DMA_CONTEXT_BUS to create firmware device Vishnu Reddy
` (2 subsequent siblings)
12 siblings, 0 replies; 17+ messages in thread
From: Vishnu Reddy @ 2026-04-23 13:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vikash Garodia, Dikshita Agarwal,
Abhinav Kumar, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Joerg Roedel, Will Deacon,
Robin Murphy, Bjorn Andersson, Konrad Dybcio, Stefan Schmidt,
Hans Verkuil, Greg Kroah-Hartman, Rafael J. Wysocki,
Danilo Krummrich, Thierry Reding, Mikko Perttunen, David Airlie,
Simona Vetter, Jonathan Hunter
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel, iommu,
driver-core, dri-devel, linux-tegra, Vishnu Reddy
On platforms with dual vcodec cores, select the hardware core for a
session based on current load. Assign the session to vcodec0 if its
MBPF/MBPS capacity allows it, otherwise assign to vcodec1. Communicate
the selected core to firmware using the new HFI_PROP_CORE_ID property.
Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
---
drivers/media/platform/qcom/iris/iris_common.c | 10 +++
drivers/media/platform/qcom/iris/iris_common.h | 1 +
drivers/media/platform/qcom/iris/iris_core.h | 5 ++
drivers/media/platform/qcom/iris/iris_hfi_common.h | 1 +
.../platform/qcom/iris/iris_hfi_gen2_command.c | 19 +++++
.../platform/qcom/iris/iris_hfi_gen2_defines.h | 1 +
drivers/media/platform/qcom/iris/iris_instance.h | 2 +
.../platform/qcom/iris/iris_platform_common.h | 1 +
drivers/media/platform/qcom/iris/iris_power.c | 11 ++-
drivers/media/platform/qcom/iris/iris_utils.c | 87 +++++++++++++++++-----
drivers/media/platform/qcom/iris/iris_vb2.c | 4 +
drivers/media/platform/qcom/iris/iris_vidc.c | 6 +-
12 files changed, 123 insertions(+), 25 deletions(-)
diff --git a/drivers/media/platform/qcom/iris/iris_common.c b/drivers/media/platform/qcom/iris/iris_common.c
index 7f1c7fe144f7..3b3fc482e194 100644
--- a/drivers/media/platform/qcom/iris/iris_common.c
+++ b/drivers/media/platform/qcom/iris/iris_common.c
@@ -46,6 +46,16 @@ void iris_set_ts_metadata(struct iris_inst *inst, struct vb2_v4l2_buffer *vbuf)
inst->metadata_idx++;
}
+int iris_set_core_id(struct iris_inst *inst)
+{
+ const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops;
+
+ if (!inst->core->iris_platform_data->dual_core)
+ return 0;
+
+ return hfi_ops->session_set_core_id(inst, inst->core_id);
+}
+
int iris_process_streamon_input(struct iris_inst *inst)
{
const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops;
diff --git a/drivers/media/platform/qcom/iris/iris_common.h b/drivers/media/platform/qcom/iris/iris_common.h
index b2a27b781c9a..34e32c60f768 100644
--- a/drivers/media/platform/qcom/iris/iris_common.h
+++ b/drivers/media/platform/qcom/iris/iris_common.h
@@ -11,6 +11,7 @@ struct iris_buffer;
int iris_vb2_buffer_to_driver(struct vb2_buffer *vb2, struct iris_buffer *buf);
void iris_set_ts_metadata(struct iris_inst *inst, struct vb2_v4l2_buffer *vbuf);
+int iris_set_core_id(struct iris_inst *inst);
int iris_process_streamon_input(struct iris_inst *inst);
int iris_process_streamon_output(struct iris_inst *inst);
int iris_session_streamoff(struct iris_inst *inst, u32 plane);
diff --git a/drivers/media/platform/qcom/iris/iris_core.h b/drivers/media/platform/qcom/iris/iris_core.h
index b396c8cf595e..54a8649841e4 100644
--- a/drivers/media/platform/qcom/iris/iris_core.h
+++ b/drivers/media/platform/qcom/iris/iris_core.h
@@ -30,6 +30,11 @@ enum domain_type {
DECODER = BIT(1),
};
+enum iris_vcodec_core_id {
+ IRIS_VCODEC0 = 1,
+ IRIS_VCODEC1,
+};
+
/**
* struct iris_core - holds core parameters valid for all instances
*
diff --git a/drivers/media/platform/qcom/iris/iris_hfi_common.h b/drivers/media/platform/qcom/iris/iris_hfi_common.h
index 3edb5ae582b4..fbaf852a6b99 100644
--- a/drivers/media/platform/qcom/iris/iris_hfi_common.h
+++ b/drivers/media/platform/qcom/iris/iris_hfi_common.h
@@ -124,6 +124,7 @@ struct iris_hfi_command_ops {
int (*session_drain)(struct iris_inst *inst, u32 plane);
int (*session_resume_drain)(struct iris_inst *inst, u32 plane);
int (*session_close)(struct iris_inst *inst);
+ int (*session_set_core_id)(struct iris_inst *inst, u32 core_id);
};
struct iris_hfi_response_ops {
diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
index 30bfd90d423b..9d9fae587297 100644
--- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
+++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c
@@ -1300,6 +1300,24 @@ static int iris_hfi_gen2_session_release_buffer(struct iris_inst *inst, struct i
inst_hfi_gen2->packet->size);
}
+static int iris_hfi_gen2_set_core_id(struct iris_inst *inst, u32 core_id)
+{
+ struct iris_inst_hfi_gen2 *inst_hfi_gen2 = to_iris_inst_hfi_gen2(inst);
+ u32 payload = core_id;
+
+ iris_hfi_gen2_packet_session_command(inst,
+ HFI_PROP_CORE_ID,
+ HFI_HOST_FLAGS_NONE,
+ HFI_PORT_NONE,
+ inst->session_id,
+ HFI_PAYLOAD_U32,
+ &payload,
+ sizeof(u32));
+
+ return iris_hfi_queue_cmd_write(inst->core, inst_hfi_gen2->packet,
+ inst_hfi_gen2->packet->size);
+}
+
static const struct iris_hfi_command_ops iris_hfi_gen2_command_ops = {
.sys_init = iris_hfi_gen2_sys_init,
.sys_image_version = iris_hfi_gen2_sys_image_version,
@@ -1317,6 +1335,7 @@ static const struct iris_hfi_command_ops iris_hfi_gen2_command_ops = {
.session_drain = iris_hfi_gen2_session_drain,
.session_resume_drain = iris_hfi_gen2_session_resume_drain,
.session_close = iris_hfi_gen2_session_close,
+ .session_set_core_id = iris_hfi_gen2_set_core_id,
};
void iris_hfi_gen2_command_ops_init(struct iris_core *core)
diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h b/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h
index cecf771c55dd..600e9dc07669 100644
--- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h
+++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h
@@ -56,6 +56,7 @@
#define HFI_PROP_BUFFER_HOST_MAX_COUNT 0x03000123
#define HFI_PROP_BUFFER_FW_MIN_OUTPUT_COUNT 0x03000124
#define HFI_PROP_PIC_ORDER_CNT_TYPE 0x03000128
+#define HFI_PROP_CORE_ID 0x030001a9
enum hfi_rate_control {
HFI_RC_VBR_CFR = 0x00000000,
diff --git a/drivers/media/platform/qcom/iris/iris_instance.h b/drivers/media/platform/qcom/iris/iris_instance.h
index 16965150f427..dd341ca5be57 100644
--- a/drivers/media/platform/qcom/iris/iris_instance.h
+++ b/drivers/media/platform/qcom/iris/iris_instance.h
@@ -37,6 +37,7 @@ struct iris_fmt {
*
* @list: used for attach an instance to the core
* @core: pointer to core structure
+ * @core_id: specifies the hardware core on which the session runs
* @session_id: id of current video session
* @ctx_q_lock: lock to serialize queues related ioctls
* @lock: lock to seralise forward and reverse threads
@@ -79,6 +80,7 @@ struct iris_fmt {
struct iris_inst {
struct list_head list;
struct iris_core *core;
+ u32 core_id;
u32 session_id;
struct mutex ctx_q_lock;/* lock to serialize queues related ioctls */
struct mutex lock; /* lock to serialize forward and reverse threads */
diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
index 8995136ad29e..502d7099085c 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_common.h
+++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
@@ -258,6 +258,7 @@ struct iris_platform_data {
const struct tz_cp_config *tz_cp_config_data;
u32 tz_cp_config_data_size;
u32 core_arch;
+ bool dual_core;
u32 hw_response_timeout;
struct ubwc_config_data *ubwc_config;
u32 num_vpp_pipe;
diff --git a/drivers/media/platform/qcom/iris/iris_power.c b/drivers/media/platform/qcom/iris/iris_power.c
index 91aa21d4070e..0e116c63f529 100644
--- a/drivers/media/platform/qcom/iris/iris_power.c
+++ b/drivers/media/platform/qcom/iris/iris_power.c
@@ -77,9 +77,9 @@ static int iris_vote_interconnects(struct iris_inst *inst)
static int iris_set_clocks(struct iris_inst *inst)
{
+ u64 vcodec0_freq = 0, vcodec1_freq = 0;
struct iris_core *core = inst->core;
struct iris_inst *instance;
- u64 freq = 0;
int ret;
mutex_lock(&core->lock);
@@ -87,11 +87,14 @@ static int iris_set_clocks(struct iris_inst *inst)
if (!instance->max_input_data_size)
continue;
- freq += instance->power.min_freq;
+ if (instance->core_id == IRIS_VCODEC0)
+ vcodec0_freq += instance->power.min_freq;
+ else if (instance->core_id == IRIS_VCODEC1)
+ vcodec1_freq += instance->power.min_freq;
}
- core->power.clk_freq = freq;
- ret = iris_opp_set_rate(core->dev, freq);
+ core->power.clk_freq = vcodec0_freq > vcodec1_freq ? vcodec0_freq : vcodec1_freq;
+ ret = iris_opp_set_rate(core->dev, core->power.clk_freq);
mutex_unlock(&core->lock);
return ret;
diff --git a/drivers/media/platform/qcom/iris/iris_utils.c b/drivers/media/platform/qcom/iris/iris_utils.c
index cfc5b576ec56..1be4cfd7d9af 100644
--- a/drivers/media/platform/qcom/iris/iris_utils.c
+++ b/drivers/media/platform/qcom/iris/iris_utils.c
@@ -90,40 +90,87 @@ struct iris_inst *iris_get_instance(struct iris_core *core, u32 session_id)
return NULL;
}
-int iris_check_core_mbpf(struct iris_inst *inst)
+static u32 iris_get_mbps(struct iris_inst *inst)
{
- struct iris_core *core = inst->core;
- struct iris_inst *instance;
- u32 total_mbpf = 0;
+ u32 fps = max(inst->frame_rate, inst->operating_rate);
+
+ return iris_get_mbpf(inst) * fps;
+}
+
+static void iris_get_core_load(struct iris_core *core, u32 *core_load, u32 *core_session, bool mbpf)
+{
+ bool dual_core = core->iris_platform_data->dual_core;
+ struct iris_inst *inst;
+ u32 load;
+
+ core_load[0] = 0;
+ core_load[1] = 0;
+ core_session[0] = 0;
+ core_session[1] = 0;
mutex_lock(&core->lock);
- list_for_each_entry(instance, &core->instances, list)
- total_mbpf += iris_get_mbpf(instance);
+ list_for_each_entry(inst, &core->instances, list) {
+ if (mbpf)
+ load = iris_get_mbpf(inst);
+ else
+ load = iris_get_mbps(inst);
+
+ if (inst->core_id == IRIS_VCODEC0) {
+ core_load[0] += load;
+ core_session[0]++;
+ } else if (dual_core && inst->core_id == IRIS_VCODEC1) {
+ core_load[1] += load;
+ core_session[1]++;
+ }
+ }
mutex_unlock(&core->lock);
+}
+
+static int iris_select_core_id(struct iris_inst *inst, u32 *core_load, u32 *core_session,
+ u32 max_load, u32 new_load)
+{
+ u32 max_session = inst->core->iris_platform_data->max_session_count;
+ bool dual_core = inst->core->iris_platform_data->dual_core;
+ u32 core_index;
+
+ core_index = (core_load[0] > core_load[1] && dual_core) ? 1 : 0;
+
+ if (core_session[core_index] >= max_session)
+ core_index = core_index == 0 && dual_core ? 1 : 0;
- if (total_mbpf > core->iris_platform_data->max_core_mbpf)
+ if (core_session[core_index] >= max_session)
+ return -ENOMEM;
+
+ if (core_load[core_index] + new_load <= max_load)
+ inst->core_id = core_index == 0 ? IRIS_VCODEC0 : IRIS_VCODEC1;
+ else
return -ENOMEM;
return 0;
}
-int iris_check_core_mbps(struct iris_inst *inst)
+int iris_check_core_mbpf(struct iris_inst *inst)
{
- struct iris_core *core = inst->core;
- struct iris_inst *instance;
- u32 total_mbps = 0, fps = 0;
+ u32 max_core_mbpf = inst->core->iris_platform_data->max_core_mbpf;
+ u32 core_mbpf[2], core_session[2], new_mbpf;
- mutex_lock(&core->lock);
- list_for_each_entry(instance, &core->instances, list) {
- fps = max(instance->frame_rate, instance->operating_rate);
- total_mbps += iris_get_mbpf(instance) * fps;
- }
- mutex_unlock(&core->lock);
+ inst->core_id = 0;
+ iris_get_core_load(inst->core, core_mbpf, core_session, true);
+ new_mbpf = iris_get_mbpf(inst);
- if (total_mbps > core->iris_platform_data->max_core_mbps)
- return -ENOMEM;
+ return iris_select_core_id(inst, core_mbpf, core_session, max_core_mbpf, new_mbpf);
+}
- return 0;
+int iris_check_core_mbps(struct iris_inst *inst)
+{
+ u32 max_core_mbps = inst->core->iris_platform_data->max_core_mbps;
+ u32 core_mbps[2] = {0, 0}, core_session[2], new_mbps;
+
+ inst->core_id = 0;
+ iris_get_core_load(inst->core, core_mbps, core_session, false);
+ new_mbps = iris_get_mbps(inst);
+
+ return iris_select_core_id(inst, core_mbps, core_session, max_core_mbps, new_mbps);
}
bool is_rotation_90_or_270(struct iris_inst *inst)
diff --git a/drivers/media/platform/qcom/iris/iris_vb2.c b/drivers/media/platform/qcom/iris/iris_vb2.c
index bf0b8400996e..5a05f7d65501 100644
--- a/drivers/media/platform/qcom/iris/iris_vb2.c
+++ b/drivers/media/platform/qcom/iris/iris_vb2.c
@@ -176,6 +176,10 @@ int iris_vb2_start_streaming(struct vb2_queue *q, unsigned int count)
if (ret)
goto error;
+ ret = iris_set_core_id(inst);
+ if (ret)
+ goto error;
+
if (V4L2_TYPE_IS_OUTPUT(q->type)) {
if (inst->domain == DECODER)
ret = iris_vdec_streamon_input(inst);
diff --git a/drivers/media/platform/qcom/iris/iris_vidc.c b/drivers/media/platform/qcom/iris/iris_vidc.c
index bd38d84c9cc7..eb167cede4c0 100644
--- a/drivers/media/platform/qcom/iris/iris_vidc.c
+++ b/drivers/media/platform/qcom/iris/iris_vidc.c
@@ -41,16 +41,20 @@ static void iris_v4l2_fh_deinit(struct iris_inst *inst, struct file *filp)
static void iris_add_session(struct iris_inst *inst)
{
+ u32 max_session_count = inst->core->iris_platform_data->max_session_count;
struct iris_core *core = inst->core;
struct iris_inst *iter;
u32 count = 0;
+ if (inst->core->iris_platform_data->dual_core)
+ max_session_count *= 2;
+
mutex_lock(&core->lock);
list_for_each_entry(iter, &core->instances, list)
count++;
- if (count < core->iris_platform_data->max_session_count)
+ if (count < max_session_count)
list_add_tail(&inst->list, &core->instances);
mutex_unlock(&core->lock);
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v2 11/13] media: iris: Select DMA_CONTEXT_BUS to create firmware device
2026-04-23 13:29 [PATCH v2 00/13] media: iris: Add support for glymur platform Vishnu Reddy
` (9 preceding siblings ...)
2026-04-23 13:29 ` [PATCH v2 10/13] media: iris: Add support to select core for dual core platforms Vishnu Reddy
@ 2026-04-23 13:29 ` Vishnu Reddy
2026-04-23 13:38 ` Greg Kroah-Hartman
2026-04-23 13:29 ` [PATCH v2 12/13] media: iris: Add platform data for glymur Vishnu Reddy
2026-04-23 13:29 ` [PATCH v2 13/13] arm64: dts: qcom: glymur: Add iris video node Vishnu Reddy
12 siblings, 1 reply; 17+ messages in thread
From: Vishnu Reddy @ 2026-04-23 13:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vikash Garodia, Dikshita Agarwal,
Abhinav Kumar, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Joerg Roedel, Will Deacon,
Robin Murphy, Bjorn Andersson, Konrad Dybcio, Stefan Schmidt,
Hans Verkuil, Greg Kroah-Hartman, Rafael J. Wysocki,
Danilo Krummrich, Thierry Reding, Mikko Perttunen, David Airlie,
Simona Vetter, Jonathan Hunter
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel, iommu,
driver-core, dri-devel, linux-tegra, Vishnu Reddy
Iris need a firmware device to enable secure PAS (peripheral
authentication service) support in case of non-Gunyah. This device
requires its own IOMMU context for memory isolation. The generic
dma-context-bus provides the infrastructure to create the device and
configure its firmware stream ID.
Select DMA_CONTEXT_BUS to ensure this bus is available when
VIDEO_QCOM_IRIS is enabled.
Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
---
drivers/media/platform/qcom/iris/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/media/platform/qcom/iris/Kconfig b/drivers/media/platform/qcom/iris/Kconfig
index 3c803a05305a..de1fc4b07ff8 100644
--- a/drivers/media/platform/qcom/iris/Kconfig
+++ b/drivers/media/platform/qcom/iris/Kconfig
@@ -6,6 +6,7 @@ config VIDEO_QCOM_IRIS
select QCOM_MDT_LOADER if ARCH_QCOM
select QCOM_SCM
select VIDEOBUF2_DMA_CONTIG
+ select DMA_CONTEXT_BUS
help
This is a V4L2 driver for Qualcomm iris video accelerator
hardware. It accelerates decoding operations on various
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH v2 11/13] media: iris: Select DMA_CONTEXT_BUS to create firmware device
2026-04-23 13:29 ` [PATCH v2 11/13] media: iris: Select DMA_CONTEXT_BUS to create firmware device Vishnu Reddy
@ 2026-04-23 13:38 ` Greg Kroah-Hartman
0 siblings, 0 replies; 17+ messages in thread
From: Greg Kroah-Hartman @ 2026-04-23 13:38 UTC (permalink / raw)
To: Vishnu Reddy
Cc: Bryan O'Donoghue, Vikash Garodia, Dikshita Agarwal,
Abhinav Kumar, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Joerg Roedel, Will Deacon,
Robin Murphy, Bjorn Andersson, Konrad Dybcio, Stefan Schmidt,
Hans Verkuil, Rafael J. Wysocki, Danilo Krummrich, Thierry Reding,
Mikko Perttunen, David Airlie, Simona Vetter, Jonathan Hunter,
linux-media, linux-arm-msm, devicetree, linux-kernel, iommu,
driver-core, dri-devel, linux-tegra
On Thu, Apr 23, 2026 at 06:59:40PM +0530, Vishnu Reddy wrote:
> Iris need a firmware device to enable secure PAS (peripheral
> authentication service) support in case of non-Gunyah.
As gunyah isn't ever going upstream, why is this an issue here for us at
all?
confused,
greg k-h
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v2 12/13] media: iris: Add platform data for glymur
2026-04-23 13:29 [PATCH v2 00/13] media: iris: Add support for glymur platform Vishnu Reddy
` (10 preceding siblings ...)
2026-04-23 13:29 ` [PATCH v2 11/13] media: iris: Select DMA_CONTEXT_BUS to create firmware device Vishnu Reddy
@ 2026-04-23 13:29 ` Vishnu Reddy
2026-04-23 13:29 ` [PATCH v2 13/13] arm64: dts: qcom: glymur: Add iris video node Vishnu Reddy
12 siblings, 0 replies; 17+ messages in thread
From: Vishnu Reddy @ 2026-04-23 13:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vikash Garodia, Dikshita Agarwal,
Abhinav Kumar, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Joerg Roedel, Will Deacon,
Robin Murphy, Bjorn Andersson, Konrad Dybcio, Stefan Schmidt,
Hans Verkuil, Greg Kroah-Hartman, Rafael J. Wysocki,
Danilo Krummrich, Thierry Reding, Mikko Perttunen, David Airlie,
Simona Vetter, Jonathan Hunter
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel, iommu,
driver-core, dri-devel, linux-tegra, Vishnu Reddy
Add glymur platform data by reusing most of the SM8550 definitions.
Move configuration that differs in a per-SoC platform specific data.
Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
---
drivers/media/platform/qcom/iris/Makefile | 1 +
.../platform/qcom/iris/iris_platform_common.h | 5 ++
.../media/platform/qcom/iris/iris_platform_gen2.c | 99 ++++++++++++++++++++++
.../platform/qcom/iris/iris_platform_glymur.c | 97 +++++++++++++++++++++
.../platform/qcom/iris/iris_platform_glymur.h | 17 ++++
drivers/media/platform/qcom/iris/iris_probe.c | 4 +
6 files changed, 223 insertions(+)
diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/platform/qcom/iris/Makefile
index 2abbd3aeb4af..2a50f3cafc38 100644
--- a/drivers/media/platform/qcom/iris/Makefile
+++ b/drivers/media/platform/qcom/iris/Makefile
@@ -11,6 +11,7 @@ qcom-iris-objs += iris_buffer.o \
iris_hfi_gen2_response.o \
iris_hfi_queue.o \
iris_platform_gen2.o \
+ iris_platform_glymur.o \
iris_power.o \
iris_probe.o \
iris_resources.o \
diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
index 502d7099085c..2003b7186480 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_common.h
+++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
@@ -30,6 +30,10 @@ struct iris_inst;
#define DEFAULT_QP 20
#define BITRATE_DEFAULT 20000000
+#define VIDEO_REGION_SECURE_FW_REGION_ID 0
+#define VIDEO_REGION_VM0_SECURE_NP_ID 1
+#define VIDEO_REGION_VM0_NONSECURE_NP_ID 5
+
enum stage_type {
STAGE_1 = 1,
STAGE_2 = 2,
@@ -41,6 +45,7 @@ enum pipe_type {
PIPE_4 = 4,
};
+extern const struct iris_platform_data glymur_data;
extern const struct iris_platform_data qcs8300_data;
extern const struct iris_platform_data sc7280_data;
extern const struct iris_platform_data sm8250_data;
diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
index 5862c89a4971..d11c9d1ce6b1 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c
+++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
@@ -12,6 +12,7 @@
#include "iris_vpu_buffer.h"
#include "iris_vpu_common.h"
+#include "iris_platform_glymur.h"
#include "iris_platform_qcs8300.h"
#include "iris_platform_sm8650.h"
#include "iris_platform_sm8750.h"
@@ -931,6 +932,104 @@ static const u32 sm8550_enc_op_int_buf_tbl[] = {
BUF_SCRATCH_2,
};
+const struct iris_platform_data glymur_data = {
+ .get_instance = iris_hfi_gen2_get_instance,
+ .init_hfi_command_ops = iris_hfi_gen2_command_ops_init,
+ .init_hfi_response_ops = iris_hfi_gen2_response_ops_init,
+ .get_vpu_buffer_size = iris_vpu_buf_size,
+ .vpu_ops = &iris_vpu36_ops,
+ .set_preset_registers = iris_set_sm8550_preset_registers,
+ .init_cb_devs = iris_glymur_init_cb_devs,
+ .deinit_cb_devs = iris_glymur_deinit_cb_devs,
+ .icc_tbl = sm8550_icc_table,
+ .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table),
+ .clk_rst_tbl = iris_glymur_clk_reset_table,
+ .clk_rst_tbl_size = ARRAY_SIZE(iris_glymur_clk_reset_table),
+ .bw_tbl_dec = sm8550_bw_table_dec,
+ .bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec),
+ .pmdomain_tbl = &iris_glymur_pmdomain_table,
+ .opp_pd_tbl = sm8550_opp_pd_table,
+ .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
+ .clk_tbl = iris_glymur_clk_table,
+ .clk_tbl_size = ARRAY_SIZE(iris_glymur_clk_table),
+ .opp_clk_tbl = iris_glymur_opp_clk_table,
+ /* Upper bound of DMA address range */
+ .dma_mask = 0xffe00000 - 1,
+ .fwname = "qcom/vpu/vpu36_p4_s7.mbn",
+ .pas_id = IRIS_PAS_ID,
+ .dual_core = true,
+ .inst_iris_fmts = platform_fmts_sm8550_dec,
+ .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec),
+ .inst_caps = &platform_inst_cap_sm8550,
+ .inst_fw_caps_dec = inst_fw_cap_sm8550_dec,
+ .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec),
+ .inst_fw_caps_enc = inst_fw_cap_sm8550_enc,
+ .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc),
+ .tz_cp_config_data = iris_glymur_tz_cp_config,
+ .tz_cp_config_data_size = ARRAY_SIZE(iris_glymur_tz_cp_config),
+ .core_arch = VIDEO_ARCH_LX,
+ .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
+ .ubwc_config = &ubwc_config_sm8550,
+ .num_vpp_pipe = 4,
+ .max_session_count = 16,
+ .max_core_mbpf = NUM_MBS_8K * 2,
+ .max_core_mbps = ((8192 * 4320) / 256) * 60,
+ .dec_input_config_params_default =
+ sm8550_vdec_input_config_params_default,
+ .dec_input_config_params_default_size =
+ ARRAY_SIZE(sm8550_vdec_input_config_params_default),
+ .dec_input_config_params_hevc =
+ sm8550_vdec_input_config_param_hevc,
+ .dec_input_config_params_hevc_size =
+ ARRAY_SIZE(sm8550_vdec_input_config_param_hevc),
+ .dec_input_config_params_vp9 =
+ sm8550_vdec_input_config_param_vp9,
+ .dec_input_config_params_vp9_size =
+ ARRAY_SIZE(sm8550_vdec_input_config_param_vp9),
+ .dec_input_config_params_av1 =
+ sm8550_vdec_input_config_param_av1,
+ .dec_input_config_params_av1_size =
+ ARRAY_SIZE(sm8550_vdec_input_config_param_av1),
+ .dec_output_config_params =
+ sm8550_vdec_output_config_params,
+ .dec_output_config_params_size =
+ ARRAY_SIZE(sm8550_vdec_output_config_params),
+
+ .enc_input_config_params =
+ sm8550_venc_input_config_params,
+ .enc_input_config_params_size =
+ ARRAY_SIZE(sm8550_venc_input_config_params),
+ .enc_output_config_params =
+ sm8550_venc_output_config_params,
+ .enc_output_config_params_size =
+ ARRAY_SIZE(sm8550_venc_output_config_params),
+
+ .dec_input_prop = sm8550_vdec_subscribe_input_properties,
+ .dec_input_prop_size = ARRAY_SIZE(sm8550_vdec_subscribe_input_properties),
+ .dec_output_prop_avc = sm8550_vdec_subscribe_output_properties_avc,
+ .dec_output_prop_avc_size =
+ ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc),
+ .dec_output_prop_hevc = sm8550_vdec_subscribe_output_properties_hevc,
+ .dec_output_prop_hevc_size =
+ ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc),
+ .dec_output_prop_vp9 = sm8550_vdec_subscribe_output_properties_vp9,
+ .dec_output_prop_vp9_size =
+ ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9),
+ .dec_output_prop_av1 = sm8550_vdec_subscribe_output_properties_av1,
+ .dec_output_prop_av1_size =
+ ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_av1),
+
+ .dec_ip_int_buf_tbl = sm8550_dec_ip_int_buf_tbl,
+ .dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl),
+ .dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl,
+ .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl),
+
+ .enc_ip_int_buf_tbl = sm8550_enc_ip_int_buf_tbl,
+ .enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_ip_int_buf_tbl),
+ .enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl,
+ .enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl),
+};
+
const struct iris_platform_data sm8550_data = {
.get_instance = iris_hfi_gen2_get_instance,
.init_hfi_command_ops = iris_hfi_gen2_command_ops_init,
diff --git a/drivers/media/platform/qcom/iris/iris_platform_glymur.c b/drivers/media/platform/qcom/iris/iris_platform_glymur.c
new file mode 100644
index 000000000000..59fa752916a4
--- /dev/null
+++ b/drivers/media/platform/qcom/iris/iris_platform_glymur.c
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/media/qcom,glymur-iris.h>
+#include <linux/dma_context_bus.h>
+#include "iris_core.h"
+#include "iris_platform_common.h"
+#include "iris_platform_glymur.h"
+
+const struct platform_clk_data iris_glymur_clk_table[] = {
+ {IRIS_AXI_VCODEC_CLK, "iface" },
+ {IRIS_CTRL_CLK, "core" },
+ {IRIS_VCODEC_CLK, "vcodec0_core" },
+ {IRIS_AXI_CTRL_CLK, "iface1" },
+ {IRIS_CTRL_FREERUN_CLK, "core_freerun" },
+ {IRIS_VCODEC_FREERUN_CLK, "vcodec0_core_freerun" },
+ {IRIS_AXI_VCODEC1_CLK, "iface2" },
+ {IRIS_VCODEC1_CLK, "vcodec1_core" },
+ {IRIS_VCODEC1_FREERUN_CLK, "vcodec1_core_freerun" },
+};
+
+const char * const iris_glymur_clk_reset_table[] = {
+ "bus0",
+ "bus1",
+ "core",
+ "vcodec0_core",
+ "bus2",
+ "vcodec1_core",
+};
+
+const char * const iris_glymur_opp_clk_table[] = {
+ "vcodec0_core",
+ "vcodec1_core",
+ "core",
+ NULL,
+};
+
+const struct platform_pd_data iris_glymur_pmdomain_table = {
+ .pd_types = (enum platform_pm_domain_type []) {
+ IRIS_CTRL_POWER_DOMAIN,
+ IRIS_VCODEC_POWER_DOMAIN,
+ IRIS_VCODEC1_POWER_DOMAIN,
+ },
+ .pd_names = (const char *[]) {
+ "venus",
+ "vcodec0",
+ "vcodec1",
+ },
+ .pd_count = 3,
+};
+
+const struct tz_cp_config iris_glymur_tz_cp_config[] = {
+ {
+ .cp_start = VIDEO_REGION_SECURE_FW_REGION_ID,
+ .cp_size = 0,
+ .cp_nonpixel_start = 0,
+ .cp_nonpixel_size = 0x1000000,
+ },
+ {
+ .cp_start = VIDEO_REGION_VM0_SECURE_NP_ID,
+ .cp_size = 0,
+ .cp_nonpixel_start = 0x1000000,
+ .cp_nonpixel_size = 0x24800000,
+ },
+ {
+ .cp_start = VIDEO_REGION_VM0_NONSECURE_NP_ID,
+ .cp_size = 0,
+ .cp_nonpixel_start = 0x25800000,
+ .cp_nonpixel_size = 0xda600000,
+ },
+};
+
+int iris_glymur_init_cb_devs(struct iris_core *core)
+{
+ u64 dma_mask = core->iris_platform_data->dma_mask;
+ const u32 f_id = IOMMU_FID_IRIS_FIRMWARE;
+ struct device *dev;
+
+ dev = create_dma_context_bus_device(core->dev, NULL, dma_mask, &f_id);
+ if (IS_ERR(dev))
+ return PTR_ERR(dev);
+
+ if (device_iommu_mapped(dev))
+ core->fw_dev = dev;
+ else
+ device_unregister(dev);
+
+ return 0;
+}
+
+void iris_glymur_deinit_cb_devs(struct iris_core *core)
+{
+ if (core->fw_dev)
+ device_unregister(core->fw_dev);
+}
diff --git a/drivers/media/platform/qcom/iris/iris_platform_glymur.h b/drivers/media/platform/qcom/iris/iris_platform_glymur.h
new file mode 100644
index 000000000000..e0d07ccf658c
--- /dev/null
+++ b/drivers/media/platform/qcom/iris/iris_platform_glymur.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef __IRIS_PLATFORM_GLYMUR_H__
+#define __IRIS_PLATFORM_GLYMUR_H__
+
+extern const struct platform_clk_data iris_glymur_clk_table[9];
+extern const char * const iris_glymur_clk_reset_table[6];
+extern const char * const iris_glymur_opp_clk_table[4];
+extern const struct platform_pd_data iris_glymur_pmdomain_table;
+extern const struct tz_cp_config iris_glymur_tz_cp_config[3];
+int iris_glymur_init_cb_devs(struct iris_core *core);
+void iris_glymur_deinit_cb_devs(struct iris_core *core);
+
+#endif /* __IRIS_PLATFORM_GLYMUR_H__ */
diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c
index 34c981be9bc1..78e3627557e9 100644
--- a/drivers/media/platform/qcom/iris/iris_probe.c
+++ b/drivers/media/platform/qcom/iris/iris_probe.c
@@ -369,6 +369,10 @@ static const struct dev_pm_ops iris_pm_ops = {
};
static const struct of_device_id iris_dt_match[] = {
+ {
+ .compatible = "qcom,glymur-iris",
+ .data = &glymur_data,
+ },
{
.compatible = "qcom,qcs8300-iris",
.data = &qcs8300_data,
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v2 13/13] arm64: dts: qcom: glymur: Add iris video node
2026-04-23 13:29 [PATCH v2 00/13] media: iris: Add support for glymur platform Vishnu Reddy
` (11 preceding siblings ...)
2026-04-23 13:29 ` [PATCH v2 12/13] media: iris: Add platform data for glymur Vishnu Reddy
@ 2026-04-23 13:29 ` Vishnu Reddy
12 siblings, 0 replies; 17+ messages in thread
From: Vishnu Reddy @ 2026-04-23 13:29 UTC (permalink / raw)
To: Bryan O'Donoghue, Vikash Garodia, Dikshita Agarwal,
Abhinav Kumar, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Joerg Roedel, Will Deacon,
Robin Murphy, Bjorn Andersson, Konrad Dybcio, Stefan Schmidt,
Hans Verkuil, Greg Kroah-Hartman, Rafael J. Wysocki,
Danilo Krummrich, Thierry Reding, Mikko Perttunen, David Airlie,
Simona Vetter, Jonathan Hunter
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel, iommu,
driver-core, dri-devel, linux-tegra, Vishnu Reddy
Add iris video codec to glymur SoC, which comes with significantly
different powering up sequence than previous platforms, thus different
clocks and resets.
Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/glymur-crd.dts | 4 ++
arch/arm64/boot/dts/qcom/glymur.dtsi | 118 ++++++++++++++++++++++++++++++++
2 files changed, 122 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts
index 35aaf09e4e2b..cbc9856956ff 100644
--- a/arch/arm64/boot/dts/qcom/glymur-crd.dts
+++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts
@@ -255,6 +255,10 @@ &mdss_dp3_phy {
status = "okay";
};
+&iris {
+ status = "okay";
+};
+
&pmh0110_f_e0_gpios {
misc_3p3_reg_en: misc-3p3-reg-en-state {
pins = "gpio6";
diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
index f23cf81ddb77..c47443174f97 100644
--- a/arch/arm64/boot/dts/qcom/glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
@@ -13,6 +13,7 @@
#include <dt-bindings/interconnect/qcom,glymur-rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
+#include <dt-bindings/media/qcom,glymur-iris.h>
#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
#include <dt-bindings/power/qcom-rpmpd.h>
@@ -4163,6 +4164,123 @@ usb_mp: usb@a400000 {
status = "disabled";
};
+ iris: video-codec@aa00000 {
+ compatible = "qcom,glymur-iris";
+ reg = <0x0 0xaa00000 0x0 0xf0000>;
+
+ clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
+ <&videocc VIDEO_CC_MVS0C_CLK>,
+ <&videocc VIDEO_CC_MVS0_CLK>,
+ <&gcc GCC_VIDEO_AXI0C_CLK>,
+ <&videocc VIDEO_CC_MVS0C_FREERUN_CLK>,
+ <&videocc VIDEO_CC_MVS0_FREERUN_CLK>,
+ <&gcc GCC_VIDEO_AXI1_CLK>,
+ <&videocc VIDEO_CC_MVS1_CLK>,
+ <&videocc VIDEO_CC_MVS1_FREERUN_CLK>;
+ clock-names = "iface",
+ "core",
+ "vcodec0_core",
+ "iface1",
+ "core_freerun",
+ "vcodec0_core_freerun",
+ "iface2",
+ "vcodec1_core",
+ "vcodec1_core_freerun";
+
+ dma-coherent;
+
+ interconnects = <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "cpu-cfg",
+ "video-mem";
+
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+
+ iommus = <&apps_smmu 0x1940 0x0>,
+ <&apps_smmu 0x1943 0x0>,
+ <&apps_smmu 0x1944 0x0>,
+ <&apps_smmu 0x19e0 0x0>;
+
+ iommu-map = <IOMMU_FID_IRIS_FIRMWARE &apps_smmu 0x19e2 0x1>;
+
+ memory-region = <&video_mem>;
+
+ operating-points-v2 = <&iris_opp_table>;
+
+ power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>,
+ <&videocc VIDEO_CC_MVS0_GDSC>,
+ <&rpmhpd RPMHPD_MXC>,
+ <&rpmhpd RPMHPD_MMCX>,
+ <&videocc VIDEO_CC_MVS1_GDSC>;
+ power-domain-names = "venus",
+ "vcodec0",
+ "mxc",
+ "mmcx",
+ "vcodec1";
+
+ resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
+ <&gcc GCC_VIDEO_AXI0C_CLK_ARES>,
+ <&videocc VIDEO_CC_MVS0C_FREERUN_CLK_ARES>,
+ <&videocc VIDEO_CC_MVS0_FREERUN_CLK_ARES>,
+ <&gcc GCC_VIDEO_AXI1_CLK_ARES>,
+ <&videocc VIDEO_CC_MVS1_FREERUN_CLK_ARES>;
+ reset-names = "bus0",
+ "bus1",
+ "core",
+ "vcodec0_core",
+ "bus2",
+ "vcodec1_core";
+
+ /*
+ * IRIS firmware is signed by vendors, only
+ * enable on boards where the proper signed firmware
+ * is available.
+ */
+ status = "disabled";
+
+ iris_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-240000000 {
+ opp-hz = /bits/ 64 <240000000 240000000 360000000>;
+ required-opps = <&rpmhpd_opp_svs>,
+ <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-338000000 {
+ opp-hz = /bits/ 64 <338000000 338000000 507000000>;
+ required-opps = <&rpmhpd_opp_svs>,
+ <&rpmhpd_opp_svs>;
+ };
+
+ opp-366000000 {
+ opp-hz = /bits/ 64 <366000000 366000000 549000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>,
+ <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-444000000 {
+ opp-hz = /bits/ 64 <444000000 444000000 666000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>,
+ <&rpmhpd_opp_nom>;
+ };
+
+ opp-533333334 {
+ opp-hz = /bits/ 64 <533333334 533333334 800000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>,
+ <&rpmhpd_opp_turbo>;
+ };
+
+ opp-655000000 {
+ opp-hz = /bits/ 64 <655000000 655000000 982000000>;
+ required-opps = <&rpmhpd_opp_nom>,
+ <&rpmhpd_opp_turbo_l1>;
+ };
+ };
+ };
+
mdss: display-subsystem@ae00000 {
compatible = "qcom,glymur-mdss";
reg = <0x0 0x0ae00000 0x0 0x1000>;
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread