From: Krzysztof Kozlowski <krzk@kernel.org>
To: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Cc: Bjorn Andersson <andersson@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Dmitry Baryshkov <lumag@kernel.org>,
Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>,
Deepti Jaggi <deepti.jaggi@oss.qualcomm.com>,
devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/4] arm64: dts: qcom: Add device tree for Nord SoC series
Date: Tue, 28 Apr 2026 09:24:51 +0200 [thread overview]
Message-ID: <20260428-dangerous-garnet-collie-dacccf@quoll> (raw)
In-Reply-To: <20260427023455.236410-2-shengchao.guo@oss.qualcomm.com>
On Mon, Apr 27, 2026 at 10:34:52AM +0800, Shawn Guo wrote:
> Add base device tree include (nord.dtsi) for the Nord SoC series
> describing the core hardware components:
>
> - 18 Oryon (qcom,oryon-1-5) cores in three clusters, with PSCI-based
> power management and CPU/cluster idle states
> - ARM GICv3 interrupt controller with ITS
> - TLMM GPIO/pinctrl controller
> - 8 TSENS thermal sensors with thermal zones
> - 3 APPS SMMU-500 instances
> - 3 QUPv3 GENI SE QUP blocks
> - PDP SCMI channel and mailbox
> - Watchdog, TRNG and TCSR
> - Reserved memory, CMD-DB and firmware SCM
> - PSCI and architected timers
>
> Co-developed-by: Deepti Jaggi <deepti.jaggi@oss.qualcomm.com>
> Signed-off-by: Deepti Jaggi <deepti.jaggi@oss.qualcomm.com>
> Co-developed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
> Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/nord.dtsi | 4511 ++++++++++++++++++++++++++++
> 1 file changed, 4511 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/nord.dtsi
>
> diff --git a/arch/arm64/boot/dts/qcom/nord.dtsi b/arch/arm64/boot/dts/qcom/nord.dtsi
> new file mode 100644
> index 000000000000..00d189cfed8c
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/nord.dtsi
> @@ -0,0 +1,4511 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> + interrupt-parent = <&intc>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "qcom,oryon-1-5";
I asked you to send this binding WITH the user, because they go via
the same tree. I see the user, but no binding for it in the patchset.
Best regards,
Krzysztof
next prev parent reply other threads:[~2026-04-28 7:24 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-27 2:34 [PATCH 0/4] Add initial device trees for Nord SA8797P Shawn Guo
2026-04-27 2:34 ` [PATCH 1/4] arm64: dts: qcom: Add device tree for Nord SoC series Shawn Guo
2026-04-28 7:24 ` Krzysztof Kozlowski [this message]
2026-04-28 7:28 ` Krzysztof Kozlowski
2026-04-28 13:09 ` Shawn Guo
2026-04-27 2:34 ` [PATCH 2/4] arm64: dts: qcom: Add device tree for Nord SA8797P SoC Shawn Guo
2026-04-27 2:34 ` [PATCH 3/4] dt-bindings: arm: qcom: Document SA8797P Ride board Shawn Guo
2026-04-28 7:23 ` Krzysztof Kozlowski
2026-04-28 13:03 ` Shawn Guo
2026-04-27 2:34 ` [PATCH 4/4] arm64: dts: qcom: Add device tree for " Shawn Guo
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