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From: Narayana Murty N <nnmlinux@linux.ibm.com>
To: linuxppc-dev@lists.ozlabs.org, maddy@linux.ibm.com,
	mpe@ellerman.id.au, npiggin@gmail.com
Cc: christophe.leroy@csgroup.eu, linux-kernel@vger.kernel.org,
	nnmlinux@linux.ibm.com, mahesh@linux.ibm.com,
	vaibhav@linux.ibm.com, sbhat@linux.ibm.com
Subject: [PATCH 1/1] powerpc/pseries/pci: quirks: Add pseries TG3 D3hot delay quirk for EEH stability
Date: Tue, 28 Apr 2026 05:35:29 -0400	[thread overview]
Message-ID: <20260428093529.7618-1-nnmlinux@linux.ibm.com> (raw)

On pseries platforms, binding Broadcom PCIe NIC devices to the vfio-pci
driver frequently triggers an unintended EEH (Extended Error Handling)
isolation event.

This occurs because the device firmware violates PCIe specification
recovery timings when transitioning from the D3hot to D0 power state
during the binding process. The strict pseries PHB catches the
resulting Unsupported Request during the subsequent configuration
space read, assuming a device failure.

Add a pseries-specific PCI fixup quirk for Broadcom devices to
explicitly extend the `d3hot_delay` to 200ms. This forces the PCI
core to sleep long enough for the firmware to safely complete the
D0 transition before attempting config reads, ensuring a clean VFIO
passthrough initialization.

Signed-off-by: Narayana Murty N <nnmlinux@linux.ibm.com>
---
 arch/powerpc/platforms/pseries/pci.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/powerpc/platforms/pseries/pci.c b/arch/powerpc/platforms/pseries/pci.c
index 84e4ffe957a8..5f3cf9a7bdd3 100644
--- a/arch/powerpc/platforms/pseries/pci.c
+++ b/arch/powerpc/platforms/pseries/pci.c
@@ -291,3 +291,24 @@ int pseries_root_bridge_prepare(struct pci_host_bridge *bridge)
 	bus->cur_bus_speed = prop_to_pci_speed(pcie_link_speed_stats[1]);
 	return 0;
 }
+
+/*
+ * Workaround for sluggish PCIe device firmware.
+ *
+ * The device violates the PCIe spec recovery timing when transitioning
+ * from D3hot to D0. On standard architectures this is often ignored, but
+ * the strict PowerPC pseries PHB catches the Unsupported Request during
+ * the subsequent config read and triggers an EEH.
+ *
+ * We inject a longer delay to ensure the device is ready before the PCI
+ * core attempts to access configuration space.
+ */
+static void quirk_pseries_d0_wake_delay(struct pci_dev *dev)
+{
+	dev->d3hot_delay = 200;
+	pci_info(dev, "pseries  Quirk:D3hot->D0 delay %d ms to prevent EEH\n",
+		 dev->d3hot_delay);
+}
+/* Blanket application to ALL Broadcom PCI devices */
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
+			PCI_ANY_ID, quirk_pseries_d0_wake_delay);
-- 
2.51.1


                 reply	other threads:[~2026-04-28 13:07 UTC|newest]

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