Re: [PATCH v5 0/3] PCI: qcom: Program T_POWER_ON value for L1.2 exit timing

Re: [PATCH v5 0/3] PCI: qcom: Program T_POWER_ON value for L1.2 exit timing

[Manivannan Sadhasivam]

On Tue, Apr 28, 2026 at 02:07:14PM +0530, Krishna Chaitanya Chundru wrote:
> The T_POWER_ON indicates the time (in μs) that a Port requires the port
> on the opposite side of Link to wait in L1.2.Exit after sampling CLKREQ#
> asserted before actively driving the interface. This value is used by
> the ASPM driver to compute the LTR_L1.2_THRESHOLD.
> 
> Currently, qcom root port exposes T_POWER_ON value of zero in the L1SS
> capability registers, leading to incorrect LTR_L1.2_THRESHOLD calculations,
> which can result in improper L1.2 exit behavior and can trigger AER's.
> 
> In this series, qcom controller drivers read the devicetree property
> "t-power-on" which got merged recently[1], and use that value to over
> write default/wrong value.
> 
> To convert T_POWER_ON in to T_POWER_ON_SCALE & T_POWER_ON_VALUE created
> a pcie_encode_t_power_on() helper in aspm.c and also created
> dw_pcie_program_t_power_on() helper for other drivers to use these
> helpers.
> 
> Link [1]: https://lore.kernel.org/all/20260205093346.667898-1-krishna.chundru@oss.qualcomm.com/
> 
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>

Series LGTM!

@Bjorn: Could you please ack patch 1 if you are OK with it?

- Mani

> ---
> Changes in v5:
> - Initialize *scale & *value to zero incase of ASPM is disabled pointed
>   by sashiko.
> - Use dwc readl & writel API's instead of direct readl & writel pointed
>   by sashiko
> - couple of nits (Mani).
> - Link to v4: https://lore.kernel.org/r/20260404-t_power_on_fux-v4-0-2891391177f4@oss.qualcomm.com
> 
> Changes in v4:
> - calculate maxv from PCI_L1SS_CTL2_T_PWR_ON_VALUE to PCI_L1SS_CAP_P_PWR_ON_VALUE (Mani).
> - added a todo to move the reading the devicetree from qcom driver to
>   dwc once multi root port parsing support is added (Mani).
> - Link to v3: https://lore.kernel.org/r/20260311-t_power_on_fux-v3-0-9b1f1d09c6f3@oss.qualcomm.com
> 
> Changes in v3:
> - move pcie_encode_t_power_on() include/linux/pci.h to
>   drivers/pci/pci.h (Bjorn).
> - couple of changes in commit text and variable name like t_power_on (Bjorn).
> - remove return 0 from qcom_pcie_configure_ports (Bjorn).
> - used FIELD_MODIFY instead of FIELD_PREP (Bjorn).
> - Link to v2: https://lore.kernel.org/r/20260223-t_power_on_fux-v2-0-20c921262709@oss.qualcomm.com
> 
> Changes in v2:
> - Instead of hard coding the values in the driver, created a devicetree
>   property "t-power-on" to program it (Bjorn & Mani).
> - Link to v1: https://lore.kernel.org/r/20251104-t_power_on_fux-v1-1-eb5916e47fd7@oss.qualcomm.com
> 
> To: Bjorn Helgaas <bhelgaas@google.com>
> To: Jingoo Han <jingoohan1@gmail.com>
> To: Manivannan Sadhasivam <mani@kernel.org>
> To: Lorenzo Pieralisi <lpieralisi@kernel.org>
> To: Krzysztof Wilczyński <kwilczynski@kernel.org>
> To: Rob Herring <robh@kernel.org>
> Cc: linux-pci@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> Cc: linux-arm-msm@vger.kernel.org
> 
> ---
> Krishna Chaitanya Chundru (3):
>       PCI/ASPM: Add helper to encode L1SS T_POWER_ON fields
>       PCI: dwc: Add helper to Program T_POWER_ON
>       PCI: qcom: Program T_POWER_ON
> 
>  drivers/pci/controller/dwc/pcie-designware.c | 28 +++++++++++++++++++
>  drivers/pci/controller/dwc/pcie-designware.h |  1 +
>  drivers/pci/controller/dwc/pcie-qcom.c       | 14 ++++++++++
>  drivers/pci/pci.h                            |  6 +++++
>  drivers/pci/pcie/aspm.c                      | 40 ++++++++++++++++++++++++++++
>  5 files changed, 89 insertions(+)
> ---
> base-commit: 3b3bea6d4b9c162f9e555905d96b8c1da67ecd5b
> change-id: 20251104-t_power_on_fux-70dc68377941
> 
> Best regards,
> --  
> Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
> 

-- 
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Re: [PATCH v5 1/3] PCI/ASPM: Add helper to encode L1SS T_POWER_ON fields

[Manivannan Sadhasivam]

On Wed, Apr 29, 2026 at 08:34:58AM +0530, Krishna Chaitanya Chundru wrote:
> 
> 
> On 4/28/2026 2:57 PM, Ilpo Järvinen wrote:
> > On Tue, 28 Apr 2026, Krishna Chaitanya Chundru wrote:
> >
> >> Add a shared helper to encode the PCIe L1 PM Substates T_POWER_ON
> >> parameter into the T_POWER_ON Scale and T_POWER_ON Value fields.
> >>
> >> This helper can be used by the controller drivers to change the
> >> default/wrong value of T_POWER_ON in L1ss capability register to
> >> avoid incorrect calculation of LTR_L1.2_THRESHOLD value.
> >>
> >> The helper converts a T_POWER_ON time specified in microseconds into
> >> the appropriate scale/value encoding defined by the PCIe spec r7.0,
> >> sec 7.8.3.2. Values that exceed the maximum encodable range are clamped
> >> to the largest representable encoding.
> >>
> >> Tested-by: Shawn Lin <shawn.lin@rock-chips.com>
> >> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
> >> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
> >> ---
> >>  drivers/pci/pci.h       |  6 ++++++
> >>  drivers/pci/pcie/aspm.c | 40 ++++++++++++++++++++++++++++++++++++++++
> >>  2 files changed, 46 insertions(+)
> >>
> >> diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
> >> index 4a14f88e543a..c379befe1ebe 100644
> >> --- a/drivers/pci/pci.h
> >> +++ b/drivers/pci/pci.h
> >> @@ -1110,6 +1110,7 @@ void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked);
> >>  void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
> >>  void pci_configure_ltr(struct pci_dev *pdev);
> >>  void pci_bridge_reconfigure_ltr(struct pci_dev *pdev);
> >> +void pcie_encode_t_power_on(u16 t_power_on_us, u8 *scale, u8 *value);
> >>  #else
> >>  static inline void pcie_aspm_remove_cap(struct pci_dev *pdev, u32 lnkcap) { }
> >>  static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
> >> @@ -1118,6 +1119,11 @@ static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked)
> >>  static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
> >>  static inline void pci_configure_ltr(struct pci_dev *pdev) { }
> >>  static inline void pci_bridge_reconfigure_ltr(struct pci_dev *pdev) { }
> >> +static inline void pcie_encode_t_power_on(u16 t_power_on_us, u8 *scale, u8 *value)
> >> +{
> >> +	*scale = 0;
> >> +	*value = 0;
> >> +}
> >>  #endif
> >>  
> >>  #ifdef CONFIG_PCIE_ECRC
> >> diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
> >> index 925373b98dff..457d469b8d49 100644
> >> --- a/drivers/pci/pcie/aspm.c
> >> +++ b/drivers/pci/pcie/aspm.c
> >> @@ -525,6 +525,46 @@ static u32 calc_l12_pwron(struct pci_dev *pdev, u32 scale, u32 val)
> >>  	return 0;
> >>  }
> >>  
> >> +/**
> >> + * pcie_encode_t_power_on - Encode T_POWER_ON into scale and value fields
> >> + * @t_power_on_us: T_POWER_ON time in microseconds
> >> + * @scale: Encoded T_POWER_ON Scale (0..2)
> >> + * @value: Encoded T_POWER_ON Value
> >> + *
> >> + * T_POWER_ON is encoded as:
> >> + *   T_POWER_ON(us) = scale_unit(us) * value
> >> + *
> >> + * where scale_unit is selected by @scale:
> >> + *   0: 2us
> >> + *   1: 10us
> >> + *   2: 100us
> >> + *
> >> + * If @t_power_on_us exceeds the maximum representable value, the result
> >> + * is clamped to the largest encodable T_POWER_ON.
> >> + *
> >> + * See PCIe r7.0, sec 7.8.3.2.
> >> + */
> >> +void pcie_encode_t_power_on(u16 t_power_on_us, u8 *scale, u8 *value)
> > Hi,
> >
> > I don't know how the type for t_power_on_us was picked but if it was 
> > arbitrary decision, I suggest you just go with 32-bit input.
> The maximum value of the T power ON is 3100us, so we are using u16 here.
> 

FWIW, I made sure dt-binding restricts the max value to 3100us:
https://github.com/devicetree-org/dt-schema/commit/3579443c5d2f5a8bbedd1ad8e6cc634ce0aa02e3

- Mani

-- 
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Re: [PATCH v5 1/3] PCI/ASPM: Add helper to encode L1SS T_POWER_ON fields

[Bjorn Helgaas]

On Tue, Apr 28, 2026 at 02:07:15PM +0530, Krishna Chaitanya Chundru wrote:
> Add a shared helper to encode the PCIe L1 PM Substates T_POWER_ON
> parameter into the T_POWER_ON Scale and T_POWER_ON Value fields.
> 
> This helper can be used by the controller drivers to change the
> default/wrong value of T_POWER_ON in L1ss capability register to
> avoid incorrect calculation of LTR_L1.2_THRESHOLD value.
> 
> The helper converts a T_POWER_ON time specified in microseconds into
> the appropriate scale/value encoding defined by the PCIe spec r7.0,
> sec 7.8.3.2. Values that exceed the maximum encodable range are clamped
> to the largest representable encoding.
> 
> Tested-by: Shawn Lin <shawn.lin@rock-chips.com>
> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>

Acked-by: Bjorn Helgaas <bhelgaas@google.com>

I do agree with Ilpo's suggestion of using u32 for t_power_on_us to
avoid some implicit conversions.  The DT binding restriction is good,
but it's far removed from the code and doesn't necessarily cover all
callers.

I think it's also helpful to include the actual function name in the
subject instead of just "helper" because it can help identify
dependencies when backporting patches that use it.

s/L1ss/L1SS/ for consistency.

> ---
>  drivers/pci/pci.h       |  6 ++++++
>  drivers/pci/pcie/aspm.c | 40 ++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 46 insertions(+)
> 
> diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
> index 4a14f88e543a..c379befe1ebe 100644
> --- a/drivers/pci/pci.h
> +++ b/drivers/pci/pci.h
> @@ -1110,6 +1110,7 @@ void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked);
>  void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
>  void pci_configure_ltr(struct pci_dev *pdev);
>  void pci_bridge_reconfigure_ltr(struct pci_dev *pdev);
> +void pcie_encode_t_power_on(u16 t_power_on_us, u8 *scale, u8 *value);
>  #else
>  static inline void pcie_aspm_remove_cap(struct pci_dev *pdev, u32 lnkcap) { }
>  static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
> @@ -1118,6 +1119,11 @@ static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked)
>  static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
>  static inline void pci_configure_ltr(struct pci_dev *pdev) { }
>  static inline void pci_bridge_reconfigure_ltr(struct pci_dev *pdev) { }
> +static inline void pcie_encode_t_power_on(u16 t_power_on_us, u8 *scale, u8 *value)
> +{
> +	*scale = 0;
> +	*value = 0;
> +}
>  #endif
>  
>  #ifdef CONFIG_PCIE_ECRC
> diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
> index 925373b98dff..457d469b8d49 100644
> --- a/drivers/pci/pcie/aspm.c
> +++ b/drivers/pci/pcie/aspm.c
> @@ -525,6 +525,46 @@ static u32 calc_l12_pwron(struct pci_dev *pdev, u32 scale, u32 val)
>  	return 0;
>  }
>  
> +/**
> + * pcie_encode_t_power_on - Encode T_POWER_ON into scale and value fields
> + * @t_power_on_us: T_POWER_ON time in microseconds
> + * @scale: Encoded T_POWER_ON Scale (0..2)
> + * @value: Encoded T_POWER_ON Value
> + *
> + * T_POWER_ON is encoded as:
> + *   T_POWER_ON(us) = scale_unit(us) * value
> + *
> + * where scale_unit is selected by @scale:
> + *   0: 2us
> + *   1: 10us
> + *   2: 100us
> + *
> + * If @t_power_on_us exceeds the maximum representable value, the result
> + * is clamped to the largest encodable T_POWER_ON.
> + *
> + * See PCIe r7.0, sec 7.8.3.2.
> + */
> +void pcie_encode_t_power_on(u16 t_power_on_us, u8 *scale, u8 *value)
> +{
> +	u8 maxv = FIELD_MAX(PCI_L1SS_CAP_P_PWR_ON_VALUE);
> +
> +	/* T_POWER_ON_Value ("value") is a 5-bit field with max value of 31. */
> +	if (t_power_on_us <= 2 * maxv) {
> +		*scale = 0; /* Value times 2us */
> +		*value = DIV_ROUND_UP(t_power_on_us, 2);
> +	} else if (t_power_on_us <= 10 * maxv) {
> +		*scale = 1; /* Value times 10us */
> +		*value = DIV_ROUND_UP(t_power_on_us, 10);
> +	} else if (t_power_on_us <= 100 * maxv) {
> +		*scale = 2; /* value times 100us */
> +		*value = DIV_ROUND_UP(t_power_on_us, 100);
> +	} else {
> +		*scale = 2;
> +		*value = maxv;
> +	}
> +}
> +EXPORT_SYMBOL(pcie_encode_t_power_on);
> +
>  /*
>   * Encode an LTR_L1.2_THRESHOLD value for the L1 PM Substates Control 1
>   * register.  Ports enter L1.2 when the most recent LTR value is greater
> 
> -- 
> 2.34.1
>