[PATCH] drm/amd/display: avoid 64-bit division

[PATCH] drm/amd/display: avoid 64-bit division

[Arnd Bergmann]

On 32-bit architectures, dividing a 64-bit integer in the kernel
leads to a link error:

ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!

Change the two recently introduced instances to a multiply+shift
operation that is also much cheaper on 32-bit architectures.
We can do that here, since both of them are really 32-bit numbers
that change a few percent.

Fixes: bedbbe6af4be ("drm/amd/display: Move link functions from dc to dc_link")
Fixes: f18bc4e53ad6 ("drm/amd/display: update calculated bounding box logic for NV")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c         | 4 ++--
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index c17db5c144aa..8dbf759eba45 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3072,8 +3072,8 @@ uint32_t dc_link_bandwidth_kbps(
 		 * but the difference is minimal and is in a safe direction,
 		 * which all works well around potential ambiguity of DP 1.4a spec.
 		 */
-		long long fec_link_bw_kbps = link_bw_kbps * 970LL;
-		link_bw_kbps = (uint32_t)(fec_link_bw_kbps / 1000LL);
+		link_bw_kbps = mul_u64_u32_shr(BIT_ULL(32) * 970LL / 1000,
+					       link_bw_kbps, 32);
 	}
 #endif
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index b35327bafbc5..70ac8a95d2db 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -2657,7 +2657,7 @@ static void update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_
 		calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000;
 
 		// FCLK:UCLK ratio is 1.08
-		min_fclk_required_by_uclk = ((unsigned long long)uclk_states[i]) * 1080 / 1000000;
+		min_fclk_required_by_uclk = mul_u64_u32_shr(BIT_ULL(32) * 1080 / 1000000, uclk_states[i], 32);
 
 		calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ?
 				min_dcfclk : min_fclk_required_by_uclk;
-- 
2.20.0

Re: [PATCH] drm/amd/display: avoid 64-bit division

[Arnd Bergmann]

On Tue, Jul 9, 2019 at 6:40 PM Deucher, Alexander
<Alexander.Deucher@amd.com> wrote:
>
> I'll just apply Arnd's patch.  If the display team wants to adjust it later to clarify the
> operation, they should go ahead as a follow up patch.

Thanks!

> From: Abramov, Slava
> Sent: Tuesday, July 9, 2019 12:31 PM
> > Thanks for bisecting this issue.
> >
> > I wonder whether you are going to commit your patch or planning to update it and it's
> > still in your work queue.  We have one of our 32-bit builds failing because of this
> > issue, so that I would like either to fix it or wait to your fix if it has chances to go
> > upstream today.

I was going to update the patch, but had not gotten to that yet.

     Arnd

[PATCH] drm/amd/display: avoid 64-bit division

[Arnd Bergmann]

From: Arnd Bergmann <arnd@arndb.de>

64-bit division is costly on 32-bit targets and should be avoided:

x86_64-linux-ld: drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.o: in function `get_dp_dto_frequency_100hz':
dce_clock_source.c:(.text+0x407): undefined reference to `__udivdi3'
x86_64-linux-ld: drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.o: in function `dcn401_get_dp_dto_frequency_100hz':
dce_clock_source.c:(.text+0x8b8): undefined reference to `__udivdi3'

Replace the open-coded division with a div_u64() call where necessary.
This could be done in a more clever way using mul_u64_u32_shr()
or similar, but since this is called rarely, use the most readable
variant that works.

Fixes: 6f6483dbfacd ("drm/amd/display: Update get_pixel_clk_frequency() for DCN4x DCCG DP DTO")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index 7c293917e6fd..501ab1a3bac2 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -1229,9 +1229,9 @@ static bool get_dp_dto_frequency_100hz(
 			 */
 			modulo_hz = REG_READ(MODULO[inst]);
 			if (modulo_hz) {
-				temp = div_u64((uint64_t)clock_hz * dp_dto_ref_khz * 10, modulo_hz);
-				ASSERT(temp / 100 <= 0xFFFFFFFFUL);
-				*pixel_clk_100hz = (unsigned int)(temp / 100);
+				temp = clock_hz * dp_dto_ref_khz * 10;
+				ASSERT(temp <= INT_MAX * modulo_hz * 100);
+				*pixel_clk_100hz = div_u64(temp, modulo_hz * 100);
 			} else
 				*pixel_clk_100hz = 0;
 		} else {
@@ -1286,12 +1286,12 @@ static bool dcn401_get_dp_dto_frequency_100hz(const struct clock_source *clock_s
 		 */
 		temp = (unsigned long long)dp_dto_integer * modulo_hz + phase_hz;
 
-		if (temp / 100 > 0xFFFFFFFFUL) {
+		if (temp > (UINT_MAX * 100ULL)) {
 			/* pixel rate 100hz should never be this high, if it is, throw an assert and return 0  */
 			BREAK_TO_DEBUGGER();
 			*pixel_clk_100hz = 0;
 		} else {
-			*pixel_clk_100hz = (unsigned int)(temp / 100);
+			*pixel_clk_100hz = div_u64(temp, 100);
 		}
 
 		return true;
-- 
2.39.5

Re: [PATCH] drm/amd/display: avoid 64-bit division

[David Laight]

On Fri, 19 Jun 2026 10:23:00 +0200
Arnd Bergmann <arnd@kernel.org> wrote:

> From: Arnd Bergmann <arnd@arndb.de>
> 
> 64-bit division is costly on 32-bit targets and should be avoided:
> 
> x86_64-linux-ld: drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.o: in function `get_dp_dto_frequency_100hz':
> dce_clock_source.c:(.text+0x407): undefined reference to `__udivdi3'
> x86_64-linux-ld: drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.o: in function `dcn401_get_dp_dto_frequency_100hz':
> dce_clock_source.c:(.text+0x8b8): undefined reference to `__udivdi3'
> 
> Replace the open-coded division with a div_u64() call where necessary.
> This could be done in a more clever way using mul_u64_u32_shr()
> or similar, but since this is called rarely, use the most readable
> variant that works.
> 
> Fixes: 6f6483dbfacd ("drm/amd/display: Update get_pixel_clk_frequency() for DCN4x DCCG DP DTO")
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> ---
>  drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
> index 7c293917e6fd..501ab1a3bac2 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
> @@ -1229,9 +1229,9 @@ static bool get_dp_dto_frequency_100hz(
>  			 */
>  			modulo_hz = REG_READ(MODULO[inst]);
>  			if (modulo_hz) {
> -				temp = div_u64((uint64_t)clock_hz * dp_dto_ref_khz * 10, modulo_hz);
> -				ASSERT(temp / 100 <= 0xFFFFFFFFUL);
> -				*pixel_clk_100hz = (unsigned int)(temp / 100);
> +				temp = clock_hz * dp_dto_ref_khz * 10;
> +				ASSERT(temp <= INT_MAX * modulo_hz * 100);

Doesn't that need something to force the RHS to 64bit?
(or has modulo_hz been changed in a patch I'm not seeing?)

	David

> +				*pixel_clk_100hz = div_u64(temp, modulo_hz * 100);
>  			} else
>  				*pixel_clk_100hz = 0;
>  		} else {
> @@ -1286,12 +1286,12 @@ static bool dcn401_get_dp_dto_frequency_100hz(const struct clock_source *clock_s
>  		 */
>  		temp = (unsigned long long)dp_dto_integer * modulo_hz + phase_hz;
>  
> -		if (temp / 100 > 0xFFFFFFFFUL) {
> +		if (temp > (UINT_MAX * 100ULL)) {
>  			/* pixel rate 100hz should never be this high, if it is, throw an assert and return 0  */
>  			BREAK_TO_DEBUGGER();
>  			*pixel_clk_100hz = 0;
>  		} else {
> -			*pixel_clk_100hz = (unsigned int)(temp / 100);
> +			*pixel_clk_100hz = div_u64(temp, 100);
>  		}
>  
>  		return true;