* [PATCH] Documentation/arch/x86/amd-memory-encryption.rst: Fix typo
@ 2026-07-04 12:55 Cédric Hannotier
2026-07-04 18:14 ` [tip: x86/cleanups] " tip-bot2 for Cédric Hannotier
0 siblings, 1 reply; 2+ messages in thread
From: Cédric Hannotier @ 2026-07-04 12:55 UTC (permalink / raw)
To: Thomas Gleixner, Ingo Molnar, Borislav Petkov, Dave Hansen, x86,
H. Peter Anvin, Jonathan Corbet, Shuah Khan
Cc: Cédric Hannotier, linux-kernel, linux-doc
The MSR address has one 0 too many: 0xc00100010 → 0xc0010010.
Signed-off-by: Cédric Hannotier <hannotiercedric@gmail.com>
---
Documentation/arch/x86/amd-memory-encryption.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/arch/x86/amd-memory-encryption.rst b/Documentation/arch/x86/amd-memory-encryption.rst
index bd840df70..92edb26a5 100644
--- a/Documentation/arch/x86/amd-memory-encryption.rst
+++ b/Documentation/arch/x86/amd-memory-encryption.rst
@@ -53,7 +53,7 @@ CPUID function 0x8000001f reports information related to SME::
system physical addresses, not guest physical
addresses)
-If support for SME is present, MSR 0xc00100010 (MSR_AMD64_SYSCFG) can be used to
+If support for SME is present, MSR 0xc0010010 (MSR_AMD64_SYSCFG) can be used to
determine if SME is enabled and/or to enable memory encryption::
0xc0010010:
--
2.54.0
^ permalink raw reply related [flat|nested] 2+ messages in thread
* [tip: x86/cleanups] Documentation/arch/x86/amd-memory-encryption.rst: Fix typo
2026-07-04 12:55 [PATCH] Documentation/arch/x86/amd-memory-encryption.rst: Fix typo Cédric Hannotier
@ 2026-07-04 18:14 ` tip-bot2 for Cédric Hannotier
0 siblings, 0 replies; 2+ messages in thread
From: tip-bot2 for Cédric Hannotier @ 2026-07-04 18:14 UTC (permalink / raw)
To: linux-tip-commits
Cc: hannotiercedric, Borislav Petkov (AMD), x86, linux-kernel
The following commit has been merged into the x86/cleanups branch of tip:
Commit-ID: db55777feca876dd2a548a232abeb3ddd8986a09
Gitweb: https://git.kernel.org/tip/db55777feca876dd2a548a232abeb3ddd8986a09
Author: Cédric Hannotier <hannotiercedric@gmail.com>
AuthorDate: Sat, 04 Jul 2026 14:55:15 +02:00
Committer: Borislav Petkov (AMD) <bp@alien8.de>
CommitterDate: Sat, 04 Jul 2026 11:09:12 -07:00
Documentation/arch/x86/amd-memory-encryption.rst: Fix typo
The MSR address has one 0 too many: 0xc00100010 → 0xc0010010.
Signed-off-by: Cédric Hannotier <hannotiercedric@gmail.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Link: https://patch.msgid.link/20260704125516.49944-1-hannotiercedric@gmail.com
---
Documentation/arch/x86/amd-memory-encryption.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/arch/x86/amd-memory-encryption.rst b/Documentation/arch/x86/amd-memory-encryption.rst
index bd840df..92edb26 100644
--- a/Documentation/arch/x86/amd-memory-encryption.rst
+++ b/Documentation/arch/x86/amd-memory-encryption.rst
@@ -53,7 +53,7 @@ CPUID function 0x8000001f reports information related to SME::
system physical addresses, not guest physical
addresses)
-If support for SME is present, MSR 0xc00100010 (MSR_AMD64_SYSCFG) can be used to
+If support for SME is present, MSR 0xc0010010 (MSR_AMD64_SYSCFG) can be used to
determine if SME is enabled and/or to enable memory encryption::
0xc0010010:
^ permalink raw reply related [flat|nested] 2+ messages in thread
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