From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
To: <linux-kernel@vger.kernel.org>, <iommu@lists.linux.dev>,
<joro@8bytes.org>, <jgg@nvidia.com>
Cc: <yi.l.liu@intel.com>, <kevin.tian@intel.com>,
<nicolinc@nvidia.com>, <vasant.hegde@amd.com>,
<jon.grimm@amd.com>, <santosh.shukla@amd.com>, <Sairaj.K@amd.com>,
<jay.chen@amd.com>, <wvw@google.com>, <wnliu@google.com>,
<dantuluris@google.com>, <chriscli@google.com>,
<kpsingh@google.com>, <alejandro.j.jimenez@oracle.com>,
<joao.m.martins@oracle.com>,
"Suravee Suthikulpanit" <suravee.suthikulpanit@amd.com>
Subject: [PATCH 22/24] iommu/amd: Add translate-device-id alloc/free with vIOMMU owner
Date: Mon, 27 Jul 2026 13:29:11 +0000 [thread overview]
Message-ID: <20260727132913.22475-23-suravee.suthikulpanit@amd.com> (raw)
In-Reply-To: <20260727132913.22475-1-suravee.suthikulpanit@amd.com>
Extend the per-segment translate-device-id pool to record the owning
struct amd_iommu_viommu in the xarray. Add amd_iommu_trans_devid_alloc()
and amd_iommu_trans_devid_free() to hand out ids from the high end of
the range and return them on teardown.
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
---
drivers/iommu/amd/amd_iommu.h | 4 ++
drivers/iommu/amd/trans_devid.c | 100 ++++++++++++++++++++++++++++++--
2 files changed, 100 insertions(+), 4 deletions(-)
diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h
index 200640ed0ef6..94ad1902ce14 100644
--- a/drivers/iommu/amd/amd_iommu.h
+++ b/drivers/iommu/amd/amd_iommu.h
@@ -225,6 +225,10 @@ void amd_iommu_pci_seg_trans_devid_fini(struct amd_iommu_pci_seg *pci_seg);
int amd_iommu_trans_devid_reserve(struct amd_iommu_pci_seg *pci_seg, u16 id);
int amd_iommu_trans_devid_reserve_pci_aliases(struct amd_iommu *iommu,
struct device *dev);
+int amd_iommu_trans_devid_alloc(struct amd_iommu_pci_seg *pci_seg,
+ struct amd_iommu_viommu *aviommu);
+void amd_iommu_trans_devid_free(struct amd_iommu_pci_seg *pci_seg, u16 id,
+ struct amd_iommu_viommu *aviommu);
#else
static inline void
amd_iommu_pci_seg_trans_devid_init(struct amd_iommu_pci_seg *pci_seg) { }
diff --git a/drivers/iommu/amd/trans_devid.c b/drivers/iommu/amd/trans_devid.c
index a40686a576ec..9d7d93c5dcdb 100644
--- a/drivers/iommu/amd/trans_devid.c
+++ b/drivers/iommu/amd/trans_devid.c
@@ -22,24 +22,55 @@ static inline bool trans_devid_xa_is_reserved(void *entry)
xa_to_value(entry) == TRANS_DEVID_RESERVED;
}
+static inline struct amd_iommu_viommu *trans_devid_xa_owner(void *entry)
+{
+ if (!entry || xa_is_value(entry))
+ return NULL;
+ return entry;
+}
+
static inline void *trans_devid_xa_mk_reserved(void)
{
return xa_mk_value(TRANS_DEVID_RESERVED);
}
-static int trans_devid_xa_install_reserved_locked(struct amd_iommu_pci_seg *pci_seg,
- u16 id)
+static int trans_devid_find_free_locked(struct amd_iommu_pci_seg *pci_seg)
+{
+ int id;
+
+ for (id = U16_MAX; id >= 0; id--) {
+ if (!xa_load(&pci_seg->trans_devid_xa, id))
+ return id;
+ }
+ return -ENOSPC;
+}
+
+static int trans_devid_xa_install_locked(struct amd_iommu_pci_seg *pci_seg,
+ u16 id, void *entry)
{
void *old;
- old = xa_store(&pci_seg->trans_devid_xa, id,
- trans_devid_xa_mk_reserved(), GFP_KERNEL);
+ old = xa_store(&pci_seg->trans_devid_xa, id, entry, GFP_KERNEL);
if (xa_is_err(old))
return xa_err(old);
WARN_ON_ONCE(old);
return 0;
}
+static int trans_devid_xa_install_allocated_locked(struct amd_iommu_pci_seg *pci_seg,
+ u16 id,
+ struct amd_iommu_viommu *aviommu)
+{
+ return trans_devid_xa_install_locked(pci_seg, id, aviommu);
+}
+
+static int trans_devid_xa_install_reserved_locked(struct amd_iommu_pci_seg *pci_seg,
+ u16 id)
+{
+ return trans_devid_xa_install_locked(pci_seg, id,
+ trans_devid_xa_mk_reserved());
+}
+
void amd_iommu_pci_seg_trans_devid_init(struct amd_iommu_pci_seg *pci_seg)
{
mutex_init(&pci_seg->trans_devid_mutex);
@@ -121,3 +152,64 @@ int amd_iommu_trans_devid_reserve_pci_aliases(struct amd_iommu *iommu,
return pci_for_each_dma_alias(pdev, reserve_trans_devid_each_dma_alias,
pci_seg);
}
+
+/**
+ * amd_iommu_trans_devid_alloc - allocate a translate-device-id for @pci_seg
+ *
+ * The trans_devid is allocated from the highest id to the lowest id.
+ * Generally, the PCI devices enumerated from the beginning of the bus range.
+ * Therefore, ids in the high range are likely to not be used.
+ *
+ * Each vIOMMU receives its own translate-device-id from the per-segment pool.
+ * @aviommu is stored in the xarray as the slot owner.
+ *
+ * Return: allocated id on success, negative errno on failure.
+ */
+int amd_iommu_trans_devid_alloc(struct amd_iommu_pci_seg *pci_seg,
+ struct amd_iommu_viommu *aviommu)
+{
+ int id, ret;
+
+ mutex_lock(&pci_seg->trans_devid_mutex);
+ id = trans_devid_find_free_locked(pci_seg);
+ if (id < 0) {
+ ret = id;
+ goto unlock;
+ }
+
+ ret = trans_devid_xa_install_allocated_locked(pci_seg, id, aviommu);
+ if (ret)
+ goto unlock;
+
+ mutex_unlock(&pci_seg->trans_devid_mutex);
+ pr_debug("%s: Allocated trans_devid %#x (seg %#x)\n", __func__, id,
+ pci_seg->id);
+ return id;
+
+unlock:
+ mutex_unlock(&pci_seg->trans_devid_mutex);
+ if (ret == -ENOSPC)
+ pr_err("%s: No free trans_devid found (seg %#x)\n", __func__,
+ pci_seg->id);
+ return ret;
+}
+
+/**
+ * amd_iommu_trans_devid_free - return @id to the per-segment pool
+ *
+ * Caller must hold @aviommu->trans_devid_lock if racing with relocation.
+ */
+void amd_iommu_trans_devid_free(struct amd_iommu_pci_seg *pci_seg, u16 id,
+ struct amd_iommu_viommu *aviommu)
+{
+ void *entry;
+
+ mutex_lock(&pci_seg->trans_devid_mutex);
+ entry = xa_erase(&pci_seg->trans_devid_xa, id);
+ if (WARN_ON_ONCE(!entry || trans_devid_xa_owner(entry) != aviommu))
+ goto out;
+ pr_debug("%s: Freed trans_devid %#x (seg %#x)\n", __func__, id,
+ pci_seg->id);
+out:
+ mutex_unlock(&pci_seg->trans_devid_mutex);
+}
--
2.34.1
next prev parent reply other threads:[~2026-07-27 13:32 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-27 13:28 [PATCH v4 00/24] iommu/amd: Introduce AMD Hardware-accelerated Virtualized IOMMU (vIOMMU) Support Suravee Suthikulpanit
2026-07-27 13:28 ` [PATCH 01/24] iommu/amd: Make amd_iommu_completion_wait() non-static Suravee Suthikulpanit
2026-08-05 17:01 ` Vasant Hegde
2026-07-27 13:28 ` [PATCH 02/24] iommu/amd: Introduce vIOMMU-specific events and event Suravee Suthikulpanit
2026-08-10 7:12 ` Vasant Hegde
2026-07-27 13:28 ` [PATCH 03/24] iommu/amd: Detect and initialize AMD vIOMMU feature Suravee Suthikulpanit
2026-08-10 8:13 ` Vasant Hegde
2026-07-27 13:28 ` [PATCH 04/24] iommu/amd: Introduce IOMMUFD vIOMMU support for AMD Suravee Suthikulpanit
2026-07-27 13:28 ` [PATCH 05/24] iommu/amd: Allocate Guest IDs for IOMMUFD vIOMMU instances Suravee Suthikulpanit
2026-08-10 9:21 ` Vasant Hegde
2026-07-27 13:28 ` [PATCH 06/24] iommu/amd: Map vIOMMU VF and VF Control MMIO BARs Suravee Suthikulpanit
2026-08-10 10:00 ` Vasant Hegde
2026-07-27 13:28 ` [PATCH 07/24] iommu/amd: Add support for AMD vIOMMU VF MMIO region Suravee Suthikulpanit
2026-08-10 10:49 ` Vasant Hegde
2026-07-27 13:28 ` [PATCH 08/24] iommu/amd: Introduce Reset vMMIO Command Suravee Suthikulpanit
2026-07-27 13:28 ` [PATCH 09/24] iommu/amd: Introduce and map vIOMMU private IPA region Suravee Suthikulpanit
2026-07-27 13:28 ` [PATCH 10/24] iommu/amd: Pass iommu to device_flush_dte() Suravee Suthikulpanit
2026-08-10 11:07 ` Vasant Hegde
2026-07-27 13:29 ` [PATCH 11/24] iommu/amd: Export amd_iommu_alloc_dev_data() helper Suravee Suthikulpanit
2026-07-27 13:29 ` [PATCH 12/24] iommu/amd: Pass iommu and devid to amd_iommu_make_clear_dte() Suravee Suthikulpanit
2026-07-27 13:29 ` [PATCH 13/24] iommu/amd: Assign IOMMU Private Address domain to IOMMU Suravee Suthikulpanit
2026-07-27 13:29 ` [PATCH 14/24] iommu/amd: Add per-VM private IPA alloc/map helpers Suravee Suthikulpanit
2026-07-27 13:29 ` [PATCH 15/24] iommu/amd: Add helper functions to manage DevID / DomID mapping tables Suravee Suthikulpanit
2026-07-27 13:29 ` [PATCH 16/24] iommu/amd: Introduce IOMMUFD vDevice support for AMD Suravee Suthikulpanit
2026-07-27 13:29 ` [PATCH 17/24] iommu/amd: Introduce helper function for updating domain ID mapping table Suravee Suthikulpanit
2026-07-27 13:29 ` [PATCH 18/24] iommu/amd: Introduce helper function for updating device " Suravee Suthikulpanit
2026-08-10 15:17 ` Vasant Hegde
2026-07-27 13:29 ` [PATCH 19/24] iommu/amd: Add per-segment translate device ID pool Suravee Suthikulpanit
2026-07-27 13:29 ` [PATCH 20/24] iommu/amd: Reserve translate-device-id for PCI requestor aliases Suravee Suthikulpanit
2026-07-27 13:29 ` [PATCH 21/24] iommu/amd: Add translation DTE and VFctrl TransDevID helpers Suravee Suthikulpanit
2026-07-27 13:29 ` Suravee Suthikulpanit [this message]
2026-07-27 13:29 ` [PATCH 23/24] iommu/amd: Assign per-vIOMMU translate device ID Suravee Suthikulpanit
2026-07-27 13:29 ` [PATCH 24/24] iommu/amd: Relocate vIOMMU translate-device-id on PCI reserve Suravee Suthikulpanit
2026-08-11 7:18 ` [PATCH v4 00/24] iommu/amd: Introduce AMD Hardware-accelerated Virtualized IOMMU (vIOMMU) Support Tian, Kevin
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