Re: [PATCH 2/4] dt-bindings: net: dsa: Add SoC-e switch IP and DSA bindings

[Benedikt Spranger <b.spranger@linutronix.de>]

On Thu, 6 Aug 2026 15:35:36 +0200
Andrew Lunn <andrew@lunn.ch> wrote:

> > The minimal IP core is an unmanaged switch. No need for a DSA driver
> > here. The IP core profides a MDIO bus, therefor a MDIO driver would
> > be good. The version register in combination with some feature
> > register can be determined to get the needed information to
> > configure the DSA driver, or in the minimal case to return -ENODEV.
 
> I think you misunderstood my comment. I expect the MDIO bus is part of
> the licensed core.
OK, I did the second step, but the first was not clear, so lets do some
ASCII art:

                     ---------
               S_AXI |   S   | port_0_gmii
              clk_in |   W   |     ...
               reset |   I   | port_N_gmii
           IP_enable |   T   |
default_op_mode[4:0] |   C   |
         port_0_link |   H   | port_0_phy_rst_n
             ...     |       |     ...
         port_N_link |   I   | port_N_phy_rst_n
          S_AXI_ACLK |   P   |
       S_AXI_ARESETN |       |
                     ---------

The switch is connected through an AXI Stream interface i.e. the memory
interface ==> Device Tree binding needed (Base Register)
Other AXI related signals are hiden and need no device tree
representation.

The switch has one mandatory and 6 optional clocks:
1. System Clock / clk_in (mandatory)
2. AXI4 Lite Clock
3. AXI Stream Clock
4. port_x_ref_rmii_clk
5. PHY RX Clock
6. PHY TX Clock
7. Port_x MDC

Here are all Device Tree bindings optional, since the mandatory clock
can be provided by some not exposed internal clock signal as in our
case and the other clocks are optional.

GMII ports ==> The ports are defined by the DSA bindings.

reset ==> optional GPIO device tree binding

IP_enable ==> optional GPIO device tree binding

default_op_mode ==> optional GPIO device tree bindings

port_x_link and port_x_phy_rst_n are signals to the PHY ==> mdio device
tree binding.

> So when you take your FPGA design, and delete the
> licensed part, that disappears as well. When you delete the licensed
> part, you should have a big hole in the middle of the design, leaving
> just what surrounds the switch. That is that logical? Clock dividers?
See above; hope that helps.

> Logic to map the switch registers to MMIO, so maybe a PCIe device
> core?
The AXI bus may connected to an PCIe bridge for example. In our case it
is connected directly to the SoC ARM core.

> Does any of this surrounding logic need software?
In our case: No.

> If it does, that is probably specific to your design, and needs a
> compatible which covers both the licensed switch core, and the
> surrounding design specific logic.

In our case the clocks are routed to fixed clocks, which have no device
tree representation. reset , IP_enable and default_op_mode are an fixed
levels.

Therefore no need for a detailed compatible string and no optional
device tree properties. Clean and simple *knock on wood*

Regards
    Bene