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From: Petr Tesarik <ptesarik@suse.com>
To: Sandipan Das <sandipan.das@amd.com>
Cc: <linux-perf-users@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>,
	Peter Zijlstra <peterz@infradead.org>,
	Ingo Molnar <mingo@redhat.com>,
	Arnaldo Carvalho de Melo <acme@kernel.org>,
	Namhyung Kim <namhyung@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	"Alexander Shishkin" <alexander.shishkin@linux.intel.com>,
	Jiri Olsa <jolsa@kernel.org>, Ian Rogers <irogers@google.com>,
	Adrian Hunter <adrian.hunter@intel.com>,
	James Clark <james.clark@linaro.org>,
	Thomas Gleixner <tglx@kernel.org>, Borislav Petkov <bp@alien8.de>,
	Dave Hansen <dave.hansen@linux.intel.com>, <x86@kernel.org>,
	"H . Peter Anvin" <hpa@zytor.com>,
	Ravi Bangoria <ravi.bangoria@amd.com>,
	Ananth Narayan <ananth.narayan@amd.com>
Subject: Re: [PATCH 3/3] perf/x86/amd: Implement x86_pmu::print_debug
Date: Thu, 6 Aug 2026 17:44:08 +0200	[thread overview]
Message-ID: <20260806174408.37b8e232@mordecai> (raw)
In-Reply-To: <eedf1d302389327c79a256e8646ac251aba8fefc.1786010408.git.sandipan.das@amd.com>

On Thu, 6 Aug 2026 15:33:28 +0530
Sandipan Das <sandipan.das@amd.com> wrote:

> Implement x86_pmu::print_debug for PerfMonV2 capable processors to dump
> MSR_AMD64_PERF_CNTR_GLOBAL_{CTL,STATUS}, plus MSR_AMD_DBG_EXTN_CFG if
> LBR Extension Version 2 is available. Chain into x86_pmu_print_debug()
> afterwards to dump the event selectors and counters.
> 
> MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_{CLR,SET} are left out since they are
> write-only.
> 
> Fixes: 21d59e3e2c40 ("perf/x86/amd/core: Detect PerfMonV2 support")
> Reported-by: Petr Tesarik <ptesarik@suse.com>
> Closes: https://lore.kernel.org/all/20260717150315.2868314-1-ptesarik@suse.com/
> Cc: stable@vger.kernel.org
> Signed-off-by: Sandipan Das <sandipan.das@amd.com>

This works great on my system, no more unchecked MSR access errors, and
the logged values look correct. Feel free to add

Tested-by: Petr Tesarik <ptesarik@suse.com>

Thank you!

Petr T

> ---
>  arch/x86/events/amd/core.c | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 
> diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
> index a787409f5a62..ecd648af81f7 100644
> --- a/arch/x86/events/amd/core.c
> +++ b/arch/x86/events/amd/core.c
> @@ -841,6 +841,25 @@ static void amd_pmu_v2_disable_all(void)
>  	amd_pmu_check_overflow();
>  }
>  
> +static void amd_pmu_v2_print_debug(int cpu)
> +{
> +	u64 ctrl, status, debugextn;
> +
> +	rdmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_CTL, ctrl);
> +	rdmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS, status);
> +
> +	pr_info("\n");
> +	pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
> +	pr_info("CPU#%d: status:     %016llx\n", cpu, status);
> +
> +	if (cpu_feature_enabled(X86_FEATURE_AMD_LBR_V2)) {
> +		rdmsrq(MSR_AMD_DBG_EXTN_CFG, debugextn);
> +		pr_info("CPU#%d: debugextn:  %016llx\n", cpu, debugextn);
> +	}
> +
> +	x86_pmu_print_debug(cpu);
> +}
> +
>  DEFINE_STATIC_CALL_NULL(amd_pmu_branch_add, *x86_pmu.add);
>  
>  static void amd_pmu_add_event(struct perf_event *event)
> @@ -1452,6 +1471,7 @@ static int __init amd_core_pmu_init(void)
>  		x86_pmu.disable_all = amd_pmu_v2_disable_all;
>  		x86_pmu.enable = amd_pmu_v2_enable_event;
>  		x86_pmu.handle_irq = amd_pmu_v2_handle_irq;
> +		x86_pmu.print_debug = amd_pmu_v2_print_debug;
>  		static_call_update(amd_pmu_test_overflow, amd_pmu_test_overflow_status);
>  	}
>  


      reply	other threads:[~2026-08-06 15:44 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-06 10:03 [PATCH 0/3] perf/x86: Fix perf_event_print_debug() on non-Intel PMUs Sandipan Das
2026-08-06 10:03 ` [PATCH 1/3] perf/x86: Add x86_pmu::print_debug Sandipan Das
2026-08-06 10:03 ` [PATCH 2/3] perf/x86: Move MSR_CORE_PERF_GLOBAL_* dump to vendor code Sandipan Das
2026-08-06 10:03 ` [PATCH 3/3] perf/x86/amd: Implement x86_pmu::print_debug Sandipan Das
2026-08-06 15:44   ` Petr Tesarik [this message]

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