* [PATCH] riscv: dts: spacemit: k3: fix IMSIC guest parameters
@ 2026-08-16 7:41 Guo Ren
2026-08-16 8:40 ` Yixun Lan
2026-08-16 9:01 ` Junhui Liu
0 siblings, 2 replies; 6+ messages in thread
From: Guo Ren @ 2026-08-16 7:41 UTC (permalink / raw)
To: linux-riscv, linux-kernel
Cc: dlan, devicetree, spacemit, GUO Ren (XuanTie), stable, Guodong Xu
From: "GUO Ren (XuanTie)" <guoren@kernel.org>
The initial K3 device tree used generic/placeholder values for the
IMSIC guest configuration:
riscv,guest-index-bits = <6>;
riscv,num-guest-ids = <511>;
According to the SpacemiT K3 User Manual [1] these values are
incorrect for the X100 cores:
- Hypervisor Extension: RVH 1.0, GEILEN = 8
- Advanced Interrupt Architecture (AIA):
- M-mode MSI: 512
- S-mode MSI: 512
- VS-mode MSI: 64
Therefore:
- S-mode IMSIC (simsic) only needs guest-index-bits = 3 (to cover
GEILEN = 8) and num-guest-ids = 63.
- M-mode IMSIC (mimsic) does not implement guest interrupt files at
all, so the guest-related properties must be omitted.
Although the KVM AIA driver will re-detect the actual number of guest
interrupt files via hgeie and correct guest-index-bits at runtime, the
device tree should still describe the correct hardware parameters.
Update the device tree to match the silicon.
[1] https://www.spacemit.com/community/document/info?lang=en&nodepath=hardware/key_stone/k3/k3_docs/k3_usermanual/08_cpu.md
Fixes: 56f37e391a62 ("riscv: dts: spacemit: add initial support for K3 SoC")
Cc: stable@vger.kernel.org
Cc: Guodong Xu <docular.xu@gmail.com>
Cc: Yixun Lan <dlan@kernel.org>
Signed-off-by: GUO Ren (XuanTie) <guoren@kernel.org>
---
arch/riscv/boot/dts/spacemit/k3.dtsi | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
index 19fc9b49668e..4120eb0c4083 100644
--- a/arch/riscv/boot/dts/spacemit/k3.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi
@@ -1127,9 +1127,9 @@ simsic: interrupt-controller@e0400000 {
<&cpu4_intc 9>, <&cpu5_intc 9>,
<&cpu6_intc 9>, <&cpu7_intc 9>;
msi-controller;
- riscv,guest-index-bits = <6>;
+ riscv,guest-index-bits = <3>;
riscv,hart-index-bits = <4>;
- riscv,num-guest-ids = <511>;
+ riscv,num-guest-ids = <63>;
riscv,num-ids = <511>;
};
@@ -1168,9 +1168,7 @@ mimsic: interrupt-controller@f1000000 {
<&cpu4_intc 11>, <&cpu5_intc 11>,
<&cpu6_intc 11>, <&cpu7_intc 11>;
msi-controller;
- riscv,guest-index-bits = <6>;
riscv,hart-index-bits = <4>;
- riscv,num-guest-ids = <511>;
riscv,num-ids = <511>;
status = "reserved";
};
--
2.43.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] riscv: dts: spacemit: k3: fix IMSIC guest parameters
2026-08-16 7:41 [PATCH] riscv: dts: spacemit: k3: fix IMSIC guest parameters Guo Ren
@ 2026-08-16 8:40 ` Yixun Lan
2026-08-17 0:55 ` Guo Ren
2026-08-16 9:01 ` Junhui Liu
1 sibling, 1 reply; 6+ messages in thread
From: Yixun Lan @ 2026-08-16 8:40 UTC (permalink / raw)
To: Guo Ren
Cc: Junhui Liu, linux-riscv, linux-kernel, devicetree, spacemit,
stable, Guodong Xu
hi Guo,
On 07:41 Sun 16 Aug , Guo Ren wrote:
> From: "GUO Ren (XuanTie)" <guoren@kernel.org>
>
> The initial K3 device tree used generic/placeholder values for the
> IMSIC guest configuration:
>
> riscv,guest-index-bits = <6>;
> riscv,num-guest-ids = <511>;
>
> According to the SpacemiT K3 User Manual [1] these values are
> incorrect for the X100 cores:
>
> - Hypervisor Extension: RVH 1.0, GEILEN = 8
> - Advanced Interrupt Architecture (AIA):
> - M-mode MSI: 512
> - S-mode MSI: 512
> - VS-mode MSI: 64
>
> Therefore:
>
> - S-mode IMSIC (simsic) only needs guest-index-bits = 3 (to cover
> GEILEN = 8) and num-guest-ids = 63.
..
> - M-mode IMSIC (mimsic) does not implement guest interrupt files at
> all, so the guest-related properties must be omitted.
>
Cc Junhui
There is already one fix for IMSIC [1], but it's actually too late to
pick for v7.3 .. I'm not sure how best to handle this, would it possible
on your side to pick Junhui's patch and rework to combine them to
send a V2? or I could pick his patch first ..
https://lore.kernel.org/all/20260729-k3-mimsic-fix-v1-1-368c0aec04b9@pigmoral.tech/
> Although the KVM AIA driver will re-detect the actual number of guest
> interrupt files via hgeie and correct guest-index-bits at runtime, the
> device tree should still describe the correct hardware parameters.
>
> Update the device tree to match the silicon.
>
..
> [1] https://www.spacemit.com/community/document/info?lang=en&nodepath=hardware/key_stone/k3/k3_docs/k3_usermanual/08_cpu.md
>
no blank line and use "Link: https://.. [1]" format
> Fixes: 56f37e391a62 ("riscv: dts: spacemit: add initial support for K3 SoC")
> Cc: stable@vger.kernel.org
> Cc: Guodong Xu <docular.xu@gmail.com>
> Cc: Yixun Lan <dlan@kernel.org>
> Signed-off-by: GUO Ren (XuanTie) <guoren@kernel.org>
> ---
> arch/riscv/boot/dts/spacemit/k3.dtsi | 6 ++----
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
> index 19fc9b49668e..4120eb0c4083 100644
> --- a/arch/riscv/boot/dts/spacemit/k3.dtsi
> +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi
> @@ -1127,9 +1127,9 @@ simsic: interrupt-controller@e0400000 {
> <&cpu4_intc 9>, <&cpu5_intc 9>,
> <&cpu6_intc 9>, <&cpu7_intc 9>;
> msi-controller;
> - riscv,guest-index-bits = <6>;
> + riscv,guest-index-bits = <3>;
> riscv,hart-index-bits = <4>;
> - riscv,num-guest-ids = <511>;
> + riscv,num-guest-ids = <63>;
> riscv,num-ids = <511>;
> };
>
> @@ -1168,9 +1168,7 @@ mimsic: interrupt-controller@f1000000 {
> <&cpu4_intc 11>, <&cpu5_intc 11>,
> <&cpu6_intc 11>, <&cpu7_intc 11>;
> msi-controller;
> - riscv,guest-index-bits = <6>;
> riscv,hart-index-bits = <4>;
> - riscv,num-guest-ids = <511>;
> riscv,num-ids = <511>;
> status = "reserved";
> };
> --
> 2.43.0
>
--
Yixun Lan (dlan)
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] riscv: dts: spacemit: k3: fix IMSIC guest parameters
2026-08-16 7:41 [PATCH] riscv: dts: spacemit: k3: fix IMSIC guest parameters Guo Ren
2026-08-16 8:40 ` Yixun Lan
@ 2026-08-16 9:01 ` Junhui Liu
2026-08-17 0:51 ` Guo Ren
1 sibling, 1 reply; 6+ messages in thread
From: Junhui Liu @ 2026-08-16 9:01 UTC (permalink / raw)
To: Guo Ren, linux-riscv, linux-kernel
Cc: dlan, devicetree, spacemit, stable, Guodong Xu, linux-riscv
Hi Guo,
On Sun Aug 16, 2026 at 3:41 PM CST, Guo Ren wrote:
> From: "GUO Ren (XuanTie)" <guoren@kernel.org>
>
> The initial K3 device tree used generic/placeholder values for the
> IMSIC guest configuration:
>
> riscv,guest-index-bits = <6>;
> riscv,num-guest-ids = <511>;
>
> According to the SpacemiT K3 User Manual [1] these values are
> incorrect for the X100 cores:
>
> - Hypervisor Extension: RVH 1.0, GEILEN = 8
> - Advanced Interrupt Architecture (AIA):
> - M-mode MSI: 512
> - S-mode MSI: 512
> - VS-mode MSI: 64
>
> Therefore:
>
> - S-mode IMSIC (simsic) only needs guest-index-bits = 3 (to cover
> GEILEN = 8) and num-guest-ids = 63.
> - M-mode IMSIC (mimsic) does not implement guest interrupt files at
> all, so the guest-related properties must be omitted.
>
> Although the KVM AIA driver will re-detect the actual number of guest
> interrupt files via hgeie and correct guest-index-bits at runtime, the
> device tree should still describe the correct hardware parameters.
>
> Update the device tree to match the silicon.
>
> [1] https://www.spacemit.com/community/document/info?lang=en&nodepath=hardware/key_stone/k3/k3_docs/k3_usermanual/08_cpu.md
>
> Fixes: 56f37e391a62 ("riscv: dts: spacemit: add initial support for K3 SoC")
> Cc: stable@vger.kernel.org
> Cc: Guodong Xu <docular.xu@gmail.com>
> Cc: Yixun Lan <dlan@kernel.org>
> Signed-off-by: GUO Ren (XuanTie) <guoren@kernel.org>
> ---
> arch/riscv/boot/dts/spacemit/k3.dtsi | 6 ++----
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
> index 19fc9b49668e..4120eb0c4083 100644
> --- a/arch/riscv/boot/dts/spacemit/k3.dtsi
> +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi
> @@ -1127,9 +1127,9 @@ simsic: interrupt-controller@e0400000 {
> <&cpu4_intc 9>, <&cpu5_intc 9>,
> <&cpu6_intc 9>, <&cpu7_intc 9>;
> msi-controller;
> - riscv,guest-index-bits = <6>;
> + riscv,guest-index-bits = <3>;
According to the IMSIC DT binding, riscv,guest-index-bits describes
the number of guest-index bits in the MSI target address, not the
number of guest interrupt files actually implemented by a hart.
On K3, the per-hart IMSIC stride is 0x40000 bytes (0x200000 / 8).
Therefore, riscv,guest-index-bits should remain 6, which satisfies the
per-hart stride formula specified by the AIA specification:
2^(guest-index-bits + 12) = 2^(6 + 12) = 0x40000 bytes
KVM already handles the difference between the address space and the
actual number of guest interrupt files. It reads HGEIE to find the
actual number of guest interrupt files and uses the smaller value:
/*
* Number of usable per-HART HGEI lines should be minimum of
* per-HART IMSIC guest files and number of bits in HGEIE.
*/
if (lc)
hgctrl->nr_hgei =
min((ulong)hgctrl->nr_hgei, lc->nr_guest_files);
I also tested this on K3. HGEIE returned 0xfe after writing all ones,
so the driver gets fls_long(0xfe) - 1 = 7 usable guest interrupt files.
> riscv,hart-index-bits = <4>;
> - riscv,num-guest-ids = <511>;
> + riscv,num-guest-ids = <63>;
This change looks good to me.
> riscv,num-ids = <511>;
> };
>
> @@ -1168,9 +1168,7 @@ mimsic: interrupt-controller@f1000000 {
> <&cpu4_intc 11>, <&cpu5_intc 11>,
> <&cpu6_intc 11>, <&cpu7_intc 11>;
> msi-controller;
> - riscv,guest-index-bits = <6>;
> riscv,hart-index-bits = <4>;
> - riscv,num-guest-ids = <511>;
> riscv,num-ids = <511>;
> status = "reserved";
> };
For the mimsic part, I already sent a related fix earlier:
https://lore.kernel.org/linux-riscv/20260729-k3-mimsic-fix-v1-1-368c0aec04b9@pigmoral.tech/
If you would like, you can pick that patch and combine the two changes
into a v2, as Yixun suggested.
--
Best regards,
Junhui Liu
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] riscv: dts: spacemit: k3: fix IMSIC guest parameters
2026-08-16 9:01 ` Junhui Liu
@ 2026-08-17 0:51 ` Guo Ren
2026-08-17 1:37 ` Guo Ren
0 siblings, 1 reply; 6+ messages in thread
From: Guo Ren @ 2026-08-17 0:51 UTC (permalink / raw)
To: Junhui Liu
Cc: linux-riscv, linux-kernel, dlan, devicetree, spacemit, stable,
Guodong Xu, linux-riscv
On Sun, Aug 16, 2026 at 5:01 PM Junhui Liu <junhui.liu@pigmoral.tech> wrote:
>
> Hi Guo,
>
> On Sun Aug 16, 2026 at 3:41 PM CST, Guo Ren wrote:
> > From: "GUO Ren (XuanTie)" <guoren@kernel.org>
> >
> > The initial K3 device tree used generic/placeholder values for the
> > IMSIC guest configuration:
> >
> > riscv,guest-index-bits = <6>;
> > riscv,num-guest-ids = <511>;
> >
> > According to the SpacemiT K3 User Manual [1], these values are
> > incorrect for the X100 cores:
> >
> > - Hypervisor Extension: RVH 1.0, GEILEN = 8
> > - Advanced Interrupt Architecture (AIA):
> > - M-mode MSI: 512
> > - S-mode MSI: 512
> > - VS-mode MSI: 64
> >
> > Therefore:
> >
> > - S-mode IMSIC (simsic) only needs guest-index-bits = 3 (to cover
> > GEILEN = 8) and num-guest-ids = 63.
> > - M-mode IMSIC (mimsic) does not implement guest interrupt files at
> > all, so the guest-related properties must be omitted.
> >
> > Although the KVM AIA driver will re-detect the actual number of guest
> > interrupt files via hgeie and correct guest-index-bits at runtime, the
> > device tree should still describe the correct hardware parameters.
> >
> > Update the device tree to match the silicon.
> >
> > [1] https://www.spacemit.com/community/document/info?lang=en&nodepath=hardware/key_stone/k3/k3_docs/k3_usermanual/08_cpu.md
> >
> > Fixes: 56f37e391a62 ("riscv: dts: spacemit: add initial support for K3 SoC")
> > Cc: stable@vger.kernel.org
> > Cc: Guodong Xu <docular.xu@gmail.com>
> > Cc: Yixun Lan <dlan@kernel.org>
> > Signed-off-by: GUO Ren (XuanTie) <guoren@kernel.org>
> > ---
> > arch/riscv/boot/dts/spacemit/k3.dtsi | 6 ++----
> > 1 file changed, 2 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
> > index 19fc9b49668e..4120eb0c4083 100644
> > --- a/arch/riscv/boot/dts/spacemit/k3.dtsi
> > +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi
> > @@ -1127,9 +1127,9 @@ simsic: interrupt-controller@e0400000 {
> > <&cpu4_intc 9>, <&cpu5_intc 9>,
> > <&cpu6_intc 9>, <&cpu7_intc 9>;
> > msi-controller;
> > - riscv,guest-index-bits = <6>;
> > + riscv,guest-index-bits = <3>;
>
> According to the IMSIC DT binding, riscv,guest-index-bits describes
> the number of guest-index bits in the MSI target address, not the
> number of guest interrupt files actually implemented by a hart.
>
> On K3, the per-hart IMSIC stride is 0x40000 bytes (0x200000 / 8).
> Therefore, riscv,guest-index-bits should remain 6, which satisfies the
> per-hart stride formula specified by the AIA specification:
>
> 2^(guest-index-bits + 12) = 2^(6 + 12) = 0x40000 bytes
>
> KVM already handles the difference between the address space and the
> actual number of guest interrupt files. It reads HGEIE to find the
> actual number of guest interrupt files and uses the smaller value:
>
> /*
> * Number of usable per-HART HGEI lines should be minimum of
> * per-HART IMSIC guest files and number of bits in HGEIE.
> */
> if (lc)
> hgctrl->nr_hgei =
> min((ulong)hgctrl->nr_hgei, lc->nr_guest_files);
>
> I also tested this on K3. HGEIE returned 0xfe after writing all ones,
> so the driver gets fls_long(0xfe) - 1 = 7 usable guest interrupt file
I don't think the reserved per-hart address stride alone is sufficient
reason to set riscv,guest-index-bits to 6.
As mentioned in the commit log:
"Although the KVM AIA driver will re-detect the actual number of guest
interrupt files via hgeie and correct guest-index-bits at runtime, the
device tree should still describe the correct hardware parameters."
Although K3 reserves a 0x40000-byte IMSIC address window per hart, only
the first 0x8000 bytes, corresponding to guest indexes 0 through 7, are
actually implemented. The remaining range from 0x8000 to 0x3ffff does
not correspond to any implemented interrupt file.
If we describe guest-index-bits = <6>, that raises a few questions:
- What hardware resource is represented by guest indexes 8 through 63?
- What behavior does the K3 hardware guarantee for accesses to the
unused 0x8000-0x3ffff range?
- Shall we let the kernel map that unused range and consume
additional page-table entries for it?
>
> > riscv,hart-index-bits = <4>;
> > - riscv,num-guest-ids = <511>;
> > + riscv,num-guest-ids = <63>;
>
> This change looks good to me.
Thx for the review.
>
> > riscv,num-ids = <511>;
> > };
> >
> > @@ -1168,9 +1168,7 @@ mimsic: interrupt-controller@f1000000 {
> > <&cpu4_intc 11>, <&cpu5_intc 11>,
> > <&cpu6_intc 11>, <&cpu7_intc 11>;
> > msi-controller;
> > - riscv,guest-index-bits = <6>;
> > riscv,hart-index-bits = <4>;
> > - riscv,num-guest-ids = <511>;
> > riscv,num-ids = <511>;
> > status = "reserved";
> > };
>
> For the mimsic part, I already sent a related fix earlier:
> https://lore.kernel.org/linux-riscv/20260729-k3-mimsic-fix-v1-1-368c0aec04b9@pigmoral.tech/
Okay, I would remove the mimsic part.
>
> If you would like, you can pick that patch and combine the two changes
> into a v2, as Yixun suggested.
--
Best Regards
Guo Ren
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] riscv: dts: spacemit: k3: fix IMSIC guest parameters
2026-08-16 8:40 ` Yixun Lan
@ 2026-08-17 0:55 ` Guo Ren
0 siblings, 0 replies; 6+ messages in thread
From: Guo Ren @ 2026-08-17 0:55 UTC (permalink / raw)
To: Yixun Lan
Cc: Junhui Liu, linux-riscv, linux-kernel, devicetree, spacemit,
stable, Guodong Xu
On Sun, Aug 16, 2026 at 4:40 PM Yixun Lan <dlan@kernel.org> wrote:
>
> hi Guo,
>
> On 07:41 Sun 16 Aug , Guo Ren wrote:
> > From: "GUO Ren (XuanTie)" <guoren@kernel.org>
> >
> > The initial K3 device tree used generic/placeholder values for the
> > IMSIC guest configuration:
> >
> > riscv,guest-index-bits = <6>;
> > riscv,num-guest-ids = <511>;
> >
> > According to the SpacemiT K3 User Manual [1] these values are
> > incorrect for the X100 cores:
> >
> > - Hypervisor Extension: RVH 1.0, GEILEN = 8
> > - Advanced Interrupt Architecture (AIA):
> > - M-mode MSI: 512
> > - S-mode MSI: 512
> > - VS-mode MSI: 64
> >
> > Therefore:
> >
> > - S-mode IMSIC (simsic) only needs guest-index-bits = 3 (to cover
> > GEILEN = 8) and num-guest-ids = 63.
> ..
> > - M-mode IMSIC (mimsic) does not implement guest interrupt files at
> > all, so the guest-related properties must be omitted.
> >
> Cc Junhui
>
> There is already one fix for IMSIC [1], but it's actually too late to
> pick for v7.3 .. I'm not sure how best to handle this, would it possible
It's not for v7.3; we could merge it in the next window.
The mimsic part is a separate fix; we could do these separately.
> on your side to pick Junhui's patch and rework to combine them to
> send a V2? or I could pick his patch first ..
I would remove the mimsic part, but I won't include it in v2. Because
there is no update for the mimsic patch, v2 makes it confusing.
>
> https://lore.kernel.org/all/20260729-k3-mimsic-fix-v1-1-368c0aec04b9@pigmoral.tech/
>
> > Although the KVM AIA driver will re-detect the actual number of guest
> > interrupt files via hgeie and correct guest-index-bits at runtime, the
> > device tree should still describe the correct hardware parameters.
> >
> > Update the device tree to match the silicon.
> >
> ..
> > [1] https://www.spacemit.com/community/document/info?lang=en&nodepath=hardware/key_stone/k3/k3_docs/k3_usermanual/08_cpu.md
> >
> no blank line and use "Link: https://.. [1]" format
>
> > Fixes: 56f37e391a62 ("riscv: dts: spacemit: add initial support for K3 SoC")
> > Cc: stable@vger.kernel.org
> > Cc: Guodong Xu <docular.xu@gmail.com>
> > Cc: Yixun Lan <dlan@kernel.org>
> > Signed-off-by: GUO Ren (XuanTie) <guoren@kernel.org>
> > ---
> > arch/riscv/boot/dts/spacemit/k3.dtsi | 6 ++----
> > 1 file changed, 2 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
> > index 19fc9b49668e..4120eb0c4083 100644
> > --- a/arch/riscv/boot/dts/spacemit/k3.dtsi
> > +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi
> > @@ -1127,9 +1127,9 @@ simsic: interrupt-controller@e0400000 {
> > <&cpu4_intc 9>, <&cpu5_intc 9>,
> > <&cpu6_intc 9>, <&cpu7_intc 9>;
> > msi-controller;
> > - riscv,guest-index-bits = <6>;
> > + riscv,guest-index-bits = <3>;
> > riscv,hart-index-bits = <4>;
> > - riscv,num-guest-ids = <511>;
> > + riscv,num-guest-ids = <63>;
> > riscv,num-ids = <511>;
> > };
> >
> > @@ -1168,9 +1168,7 @@ mimsic: interrupt-controller@f1000000 {
> > <&cpu4_intc 11>, <&cpu5_intc 11>,
> > <&cpu6_intc 11>, <&cpu7_intc 11>;
> > msi-controller;
> > - riscv,guest-index-bits = <6>;
> > riscv,hart-index-bits = <4>;
> > - riscv,num-guest-ids = <511>;
> > riscv,num-ids = <511>;
> > status = "reserved";
> > };
> > --
> > 2.43.0
> >
>
> --
> Yixun Lan (dlan)
--
Best Regards
Guo Ren
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] riscv: dts: spacemit: k3: fix IMSIC guest parameters
2026-08-17 0:51 ` Guo Ren
@ 2026-08-17 1:37 ` Guo Ren
0 siblings, 0 replies; 6+ messages in thread
From: Guo Ren @ 2026-08-17 1:37 UTC (permalink / raw)
To: Junhui Liu
Cc: linux-riscv, linux-kernel, dlan, devicetree, spacemit, stable,
Guodong Xu, linux-riscv
On Mon, Aug 17, 2026 at 8:51 AM Guo Ren <guoren@kernel.org> wrote:
>
> On Sun, Aug 16, 2026 at 5:01 PM Junhui Liu <junhui.liu@pigmoral.tech> wrote:
> >
> > Hi Guo,
> >
> > On Sun Aug 16, 2026 at 3:41 PM CST, Guo Ren wrote:
> > > From: "GUO Ren (XuanTie)" <guoren@kernel.org>
> > >
> > > The initial K3 device tree used generic/placeholder values for the
> > > IMSIC guest configuration:
> > >
> > > riscv,guest-index-bits = <6>;
> > > riscv,num-guest-ids = <511>;
> > >
> > > According to the SpacemiT K3 User Manual [1], these values are
> > > incorrect for the X100 cores:
> > >
> > > - Hypervisor Extension: RVH 1.0, GEILEN = 8
> > > - Advanced Interrupt Architecture (AIA):
> > > - M-mode MSI: 512
> > > - S-mode MSI: 512
> > > - VS-mode MSI: 64
> > >
> > > Therefore:
> > >
> > > - S-mode IMSIC (simsic) only needs guest-index-bits = 3 (to cover
> > > GEILEN = 8) and num-guest-ids = 63.
> > > - M-mode IMSIC (mimsic) does not implement guest interrupt files at
> > > all, so the guest-related properties must be omitted.
> > >
> > > Although the KVM AIA driver will re-detect the actual number of guest
> > > interrupt files via hgeie and correct guest-index-bits at runtime, the
> > > device tree should still describe the correct hardware parameters.
> > >
> > > Update the device tree to match the silicon.
> > >
> > > [1] https://www.spacemit.com/community/document/info?lang=en&nodepath=hardware/key_stone/k3/k3_docs/k3_usermanual/08_cpu.md
> > >
> > > Fixes: 56f37e391a62 ("riscv: dts: spacemit: add initial support for K3 SoC")
> > > Cc: stable@vger.kernel.org
> > > Cc: Guodong Xu <docular.xu@gmail.com>
> > > Cc: Yixun Lan <dlan@kernel.org>
> > > Signed-off-by: GUO Ren (XuanTie) <guoren@kernel.org>
> > > ---
> > > arch/riscv/boot/dts/spacemit/k3.dtsi | 6 ++----
> > > 1 file changed, 2 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
> > > index 19fc9b49668e..4120eb0c4083 100644
> > > --- a/arch/riscv/boot/dts/spacemit/k3.dtsi
> > > +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi
> > > @@ -1127,9 +1127,9 @@ simsic: interrupt-controller@e0400000 {
> > > <&cpu4_intc 9>, <&cpu5_intc 9>,
> > > <&cpu6_intc 9>, <&cpu7_intc 9>;
> > > msi-controller;
> > > - riscv,guest-index-bits = <6>;
> > > + riscv,guest-index-bits = <3>;
> >
> > According to the IMSIC DT binding, riscv,guest-index-bits describes
> > the number of guest-index bits in the MSI target address, not the
> > number of guest interrupt files actually implemented by a hart.
> >
> > On K3, the per-hart IMSIC stride is 0x40000 bytes (0x200000 / 8).
> > Therefore, riscv,guest-index-bits should remain 6, which satisfies the
> > per-hart stride formula specified by the AIA specification:
> >
> > 2^(guest-index-bits + 12) = 2^(6 + 12) = 0x40000 bytes
> >
> > KVM already handles the difference between the address space and the
> > actual number of guest interrupt files. It reads HGEIE to find the
> > actual number of guest interrupt files and uses the smaller value:
> >
> > /*
> > * Number of usable per-HART HGEI lines should be minimum of
> > * per-HART IMSIC guest files and number of bits in HGEIE.
> > */
> > if (lc)
> > hgctrl->nr_hgei =
> > min((ulong)hgctrl->nr_hgei, lc->nr_guest_files);
> >
> > I also tested this on K3. HGEIE returned 0xfe after writing all ones,
> > so the driver gets fls_long(0xfe) - 1 = 7 usable guest interrupt file
>
> I don't think the reserved per-hart address stride alone is sufficient
> reason to set riscv,guest-index-bits to 6.
>
> As mentioned in the commit log:
> "Although the KVM AIA driver will re-detect the actual number of guest
> interrupt files via hgeie and correct guest-index-bits at runtime, the
> device tree should still describe the correct hardware parameters."
>
> Although K3 reserves a 0x40000-byte IMSIC address window per hart, only
> the first 0x8000 bytes, corresponding to guest indexes 0 through 7, are
> actually implemented. The remaining range from 0x8000 to 0x3ffff does
> not correspond to any implemented interrupt file.
>
> If we describe guest-index-bits = <6>, that raises a few questions:
> - What hardware resource is represented by guest indexes 8 through 63?
> - What behavior does the K3 hardware guarantee for accesses to the
> unused 0x8000-0x3ffff range?
> - Shall we let the kernel map that unused range and consume
> additional page-table entries for it?
After re-reading imsic_parse_fwnode(), you're right. I misunderstood
the semantics here. riscv,guest-index-bits is used to describe the
guest-index field in the IMSIC address layout and therefore determines
the per-hart address stride; it does not directly represent the number
of guest interrupt files actually implemented.
Thanks to you & sashiko-bot for pointing this out.
>
> >
> > > riscv,hart-index-bits = <4>;
> > > - riscv,num-guest-ids = <511>;
> > > + riscv,num-guest-ids = <63>;
> >
> > This change looks good to me.
> Thx for the review.
>
> >
> > > riscv,num-ids = <511>;
> > > };
> > >
> > > @@ -1168,9 +1168,7 @@ mimsic: interrupt-controller@f1000000 {
> > > <&cpu4_intc 11>, <&cpu5_intc 11>,
> > > <&cpu6_intc 11>, <&cpu7_intc 11>;
> > > msi-controller;
> > > - riscv,guest-index-bits = <6>;
> > > riscv,hart-index-bits = <4>;
> > > - riscv,num-guest-ids = <511>;
> > > riscv,num-ids = <511>;
> > > status = "reserved";
> > > };
> >
> > For the mimsic part, I already sent a related fix earlier:
> > https://lore.kernel.org/linux-riscv/20260729-k3-mimsic-fix-v1-1-368c0aec04b9@pigmoral.tech/
> Okay, I would remove the mimsic part.
>
> >
> > If you would like, you can pick that patch and combine the two changes
> > into a v2, as Yixun suggested.
>
> --
> Best Regards
> Guo Ren
--
Best Regards
Guo Ren
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2026-08-17 1:37 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-08-16 7:41 [PATCH] riscv: dts: spacemit: k3: fix IMSIC guest parameters Guo Ren
2026-08-16 8:40 ` Yixun Lan
2026-08-17 0:55 ` Guo Ren
2026-08-16 9:01 ` Junhui Liu
2026-08-17 0:51 ` Guo Ren
2026-08-17 1:37 ` Guo Ren
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