[PATCH 0/2] spi: dw: clean ups from "use threaded interrupt"

[PATCH 0/2] spi: dw: clean ups from "use threaded interrupt"

[Jisheng Zhang]

Two clean ups from the series "spi: dw: use threaded interrupt"

Hi Mark,

The enhanced spi mode was merged, I'm a bit concerned with potential
bugs with "use threaded interrupt" with it, it's better to let the
threaded interrupt tested with it. But I don't have available HW, so I
will cook new version once v7.3-rc1 is out and ask sifive people help
for test.

But the two clean ups in the "use threaded interrupt" series are ready
so I pull them out of the series and rebase on latest spi-next tree, I
hope they can be merged for v7.3-rc1.

Thanks in advance

Jisheng Zhang (2):
  spi: dw: use DW_SPI_ISR directly
  spi: dw: use DW_SPI_INT_MASK instead of hardcoded 0xff

 drivers/spi/spi-dw-core.c | 19 ++++++++++---------
 1 file changed, 10 insertions(+), 9 deletions(-)

-- 
2.53.0

[PATCH 1/2] spi: dw: use DW_SPI_ISR directly

[Jisheng Zhang]

The DW_SPI_ISR register reports the masked interrupts, no need to mask
again.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
 drivers/spi/spi-dw-core.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c
index dfce2fa20adf..299474507663 100644
--- a/drivers/spi/spi-dw-core.c
+++ b/drivers/spi/spi-dw-core.c
@@ -275,7 +275,7 @@ static irqreturn_t dw_spi_irq(int irq, void *dev_id)
 {
 	struct spi_controller *ctlr = dev_id;
 	struct dw_spi *dws = spi_controller_get_devdata(ctlr);
-	u16 irq_status = dw_readl(dws, DW_SPI_ISR) & DW_SPI_INT_MASK;
+	u16 irq_status = dw_readl(dws, DW_SPI_ISR);
 
 	if (!irq_status)
 		return IRQ_NONE;
-- 
2.53.0

[PATCH 2/2] spi: dw: use DW_SPI_INT_MASK instead of hardcoded 0xff

[Jisheng Zhang]

The Interrupt Mask Register valid bits is bit[5:0] which is well
defined with DW_SPI_INT_MASK, use it instead of the incorrect(but no
harm) and hardcoded 0xff.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
 drivers/spi/spi-dw-core.c | 17 +++++++++--------
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c
index 299474507663..75d3f5fd79a3 100644
--- a/drivers/spi/spi-dw-core.c
+++ b/drivers/spi/spi-dw-core.c
@@ -228,7 +228,7 @@ static irqreturn_t dw_spi_transfer_handler(struct dw_spi *dws)
 	 */
 	dw_reader(dws);
 	if (!dws->rx_len) {
-		dw_spi_mask_intr(dws, 0xff);
+		dw_spi_mask_intr(dws, DW_SPI_INT_MASK);
 		spi_finalize_current_transfer(dws->ctlr);
 	} else if (dws->rx_len <= dw_readl(dws, DW_SPI_RXFTLR)) {
 		dw_writel(dws, DW_SPI_RXFTLR, dws->rx_len - 1);
@@ -264,7 +264,7 @@ static irqreturn_t dw_spi_enh_handler(struct dw_spi *dws)
 	if (!dws->tx_len && dws->rx_len) {
 		dw_spi_mask_intr(dws, DW_SPI_INT_TXEI);
 	} else if (!dws->rx_len && !dws->tx_len) {
-		dw_spi_mask_intr(dws, 0xff);
+		dw_spi_mask_intr(dws, DW_SPI_INT_MASK);
 		spi_finalize_current_transfer(dws->ctlr);
 	}
 
@@ -282,12 +282,13 @@ static irqreturn_t dw_spi_irq(int irq, void *dev_id)
 
 	if (!dws->transfer_handler ||
 	    (!ctlr->cur_msg && dws->transfer_handler == dw_spi_transfer_handler)) {
-		dw_spi_mask_intr(dws, 0xff);
+		dw_spi_mask_intr(dws, DW_SPI_INT_MASK);
 		return IRQ_HANDLED;
 	}
+
 	if (dws->transfer_handler == dw_spi_enh_handler &&
 	    !dws->rx_len && !dws->tx_len) {
-		dw_spi_mask_intr(dws, 0xff);
+		dw_spi_mask_intr(dws, DW_SPI_INT_MASK);
 		spi_finalize_current_transfer(ctlr);
 		return IRQ_HANDLED;
 	}
@@ -525,7 +526,7 @@ static int dw_spi_transfer_one(struct spi_controller *ctlr,
 	dws->dma_mapped = spi_xfer_is_dma_mapped(ctlr, spi, transfer);
 
 	/* For poll mode just disable all interrupts */
-	dw_spi_mask_intr(dws, 0xff);
+	dw_spi_mask_intr(dws, DW_SPI_INT_MASK);
 
 	if (dws->dma_mapped) {
 		ret = dws->dma_ops->dma_setup(dws, transfer);
@@ -831,7 +832,7 @@ static int dw_spi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)
 
 	dw_spi_update_config(dws, mem->spi, &cfg, NULL);
 
-	dw_spi_mask_intr(dws, 0xff);
+	dw_spi_mask_intr(dws, DW_SPI_INT_MASK);
 
 	dw_spi_enable_chip(dws, 1);
 
@@ -999,7 +1000,7 @@ static int dw_spi_exec_enh_mem_op(struct spi_mem *mem, const struct spi_mem_op *
 
 	dw_spi_update_config(dws, mem->spi, &cfg, &enh_cfg);
 
-	dw_spi_mask_intr(dws, 0xff);
+	dw_spi_mask_intr(dws, DW_SPI_INT_MASK);
 	reinit_completion(&ctlr->xfer_completion);
 
 	if (op->addr.nbytes && dws->set_addr_nbyte) {
@@ -1038,7 +1039,7 @@ static int dw_spi_exec_enh_mem_op(struct spi_mem *mem, const struct spi_mem_op *
 	ms = wait_for_completion_timeout(&ctlr->xfer_completion,
 					 msecs_to_jiffies(ms));
 	if (ms == 0) {
-		dw_spi_mask_intr(dws, 0xff);
+		dw_spi_mask_intr(dws, DW_SPI_INT_MASK);
 		synchronize_irq(dws->irq);
 		dws->rx = NULL;
 		dws->tx = NULL;
-- 
2.53.0

Re: [PATCH 2/2] spi: dw: use DW_SPI_INT_MASK instead of hardcoded 0xff

[Mark Brown]

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On Mon, Aug 17, 2026 at 11:14:04PM +0800, Jisheng Zhang wrote:
> The Interrupt Mask Register valid bits is bit[5:0] which is well
> defined with DW_SPI_INT_MASK, use it instead of the incorrect(but no
> harm) and hardcoded 0xff.

>  	dw_reader(dws);
>  	if (!dws->rx_len) {
> -		dw_spi_mask_intr(dws, 0xff);
> +		dw_spi_mask_intr(dws, DW_SPI_INT_MASK);

As I'm reasonably sure I said before this looks fairly obviously like
defensive programming intended to handle future versions of the IP that
define more mask bits sensibly.

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