Re: [PATCH 04/27] gpu: nova-core: add Falcon helpers for r000 LOAD_EXEC events

[Zhi Wang <zhiw@nvidia.com>]

On Tue, 18 Aug 2026 20:51:57 -0700
John Hubbard <jhubbard@nvidia.com> wrote:

Looking good to me (double checking the flows aligned with r000
firmware) with one nit below.

Reviewed-by: Zhi Wang <zhiw@nvidia.com>

> The r000 LOAD_EXEC events provide addresses for images that the driver
> must copy into GSP Falcon IMEM and DMEM. The existing Falcon DMA path
> creates its source buffer from a FalconFirmware object, so it cannot
> use those addresses. The protocol also reports GSP RISC-V suspension
> through MAILBOX0 bit 31 rather than CPUCTL.halted.
> 
> Add Falcon operations for DMA from event-provided addresses and for
> the RISC-V suspend indication.
> 

snip

> +
> regs::NV_PFALCON_FALCON_DMATRFMOFFS::zeroed().try_with_offs(dst_offset
> + pos)?,
> +            );
> +            self.bar.write(
> +                WithBase::of::<E>(),
> +
> regs::NV_PFALCON_FALCON_DMATRFFBOFFS::zeroed().with_offs(src_offset +
> pos),
> +            );
> +

Should we think of using check_add() here?

Z.

> +            self.bar.write(WithBase::of::<E>(), cmd);
> +
> +            read_poll_timeout(
> +                ||
> Ok(self.bar.read(regs::NV_PFALCON_FALCON_DMATRFCMD::of::<E>())),
> +                |r| r.idle(),
> +                Delta::ZERO,
> +                Delta::from_secs(2),
> +            )?;
> +        }
> +
> +        Ok(())
> +    }
> +
>      /// Perform a DMA load into `IMEM` and `DMEM` of `fw`, and
> prepare the falcon to run it. fn dma_load<F: FalconFirmware<Target =
> E> + FalconDmaLoadable>(&self, fw: &F) -> Result { // DMA object with
> E> firmware content as the source of the DMA engine.
> @@ -647,6 +763,24 @@ pub(crate) fn wait_till_halted(&self) ->
> Result<()> { Ok(())
>      }
>  
> +    /// Wait until the GSP processor has suspended.
> +    ///
> +    /// The RISC-V GSP signals suspension by setting bit 31
> (`0x8000_0000`) in `MAILBOX0`, rather
> +    /// than through `CPUCTL.halted`.
> +    #[expect(dead_code)]
> +    pub(crate) fn wait_for_processor_suspend(&self) -> Result<()> {
> +        const INTERRUPT_PROCESSOR_SUSPENDED: u32 = 0x8000_0000;
> +
> +        read_poll_timeout(
> +            || Ok(self.read_mailbox0()),
> +            |val| (*val & INTERRUPT_PROCESSOR_SUSPENDED) != 0,
> +            Delta::ZERO,
> +            Delta::from_secs(2),
> +        )?;
> +
> +        Ok(())
> +    }
> +
>      /// Start the falcon CPU.
>      pub(crate) fn start(&self) -> Result<()> {
>          match self
> diff --git a/drivers/gpu/nova-core/regs.rs
> b/drivers/gpu/nova-core/regs.rs index 01fde2c5e5a6..5d265b5788e3
> 100644 --- a/drivers/gpu/nova-core/regs.rs
> +++ b/drivers/gpu/nova-core/regs.rs
> @@ -264,7 +264,7 @@ pub(crate) fn usable_fb_size(self) -> u64 {
>      }
>  
>      pub(crate) NV_PFALCON_FALCON_DMATRFCMD(u32) @ PFalconBase +
> 0x00000118 {
> -        16:16   set_dmtag;
> +        16:16   set_dmtag => bool;
>          14:12   ctxdma;
>          10:8    size ?=> DmaTrfCmdSize;
>          5:5     is_write => bool;