Re: [PATCH 22/27] gpu: nova-core: gsp: add the GSP_INIT request builder

[Zhi Wang <zhiw@nvidia.com>]

On Tue, 18 Aug 2026 20:52:15 -0700
John Hubbard <jhubbard@nvidia.com> wrote:

> The r000 GSP boot protocol replaces the separate system-info, registry
> and static-info commands with one GSP_INIT request, whose payload is
> an NVKV key-value blob rather than a packed struct.
> 
> Nova-core has the NVKV codec and the GSP_INIT schema, but nothing that
> fills the schema in from a PCI device.
> 
> Add the builder. It encodes the PCI identifiers and config mirror
> range the RPC path already sends, and the registry entries, whose
> names carry the NULL that GSP-RM counts in the encoded length.
> 
> Assisted-by: Cursor:claude-opus-5
> Signed-off-by: John Hubbard <jhubbard@nvidia.com>

snip

> [`GspSetSystemInfo::init`] on the RPC path.
> +    pub(crate) fn new(
> +        dev: &pci::Device<device::Bound>,
> +        chipset: Chipset,
> +        regkeys: KVVec<RegKey>,
> +    ) -> Self {
> +        let mirror = chipset.pci_config_mirror_range();
> +        let device_id = (u32::from(dev.device_id()) << 16) |
> u32::from(dev.vendor_id().as_raw());
> +        let sub_device_id =
> +            (u32::from(dev.subsystem_device_id()) << 16) |
> u32::from(dev.subsystem_vendor_id()); +
> +        Self {
> +            pci_device_id: device_id.into(),
> +            pci_sub_device_id: sub_device_id.into(),
> +            pci_revision_id: u32::from(dev.revision_id()).into(),
> +            pci_config_mirror_base: mirror.start.into(),
> +            pci_config_mirror_size: (mirror.end -
> mirror.start).into(),
> +            oor_arch: OorArch::host().into(),
> +            bus_device_func: u64::from(dev.dev_id()).into(),

This looks not correct (though the name looks really really confusing):

https://github.com/NVIDIA/open-gpu-kernel-modules/blob/main/src/nvidia/generated/g_gpu_nvoc.h#L439

// DRF macros for GPUBUSINFO::nvDomainBusDeviceFunc
#define NVGPU_BUSDEVICE_DOMAIN     63:32
#define NVGPU_BUSDEVICE_BUS        15:8
#define NVGPU_BUSDEVICE_DEVICE      7:0

static NV_INLINE NvU64 gpuEncodeDomainBusDevice(NvU32 domain, NvU8 bus,
NvU8 device) {
    return DRF_NUM64(GPU, _BUSDEVICE, _DOMAIN, domain) |
           DRF_NUM64(GPU, _BUSDEVICE, _BUS, bus) |
           DRF_NUM64(GPU, _BUSDEVICE, _DEVICE, device);
}

The output should be ((domain << 32) | (bus << 8) | slot) - DBD

While in our code, dev.dev_id() returns from PCI_DEVID(), which is (bus
<< 8) | (slot << 3) | function - BDF.

Z.

> +            regkeys,
> +            vf_info: None,
> +        }
> +    }
>  }
>  
>  // Decode: