From: Pranjal Shrivastava <praan@google.com>
To: iommu@lists.linux.dev, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org
Cc: Joerg Roedel <joro@8bytes.org>,
Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>,
Vasant Hegde <vasant.hegde@amd.com>,
Ankit Soni <ankit.soni@amd.com>,
Jason Gunthorpe <jgg@nvidia.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Samiullah Khawaja <skhawaja@google.com>,
Pranjal Shrivastava <praan@google.com>
Subject: [PATCH v3 1/5] iommu/amd: Refactor device probe and capability initialization
Date: Mon, 24 Aug 2026 12:23:43 +0000 [thread overview]
Message-ID: <20260824122347.1588592-2-praan@google.com> (raw)
In-Reply-To: <20260824122347.1588592-1-praan@google.com>
Restructure the device probe path to improve readability and prepare for
cleaner error handling. Refactor check_device() into iommu_lookup_device
to explicitly validate and return the amd_iommu ptr & devid. Refactor
iommu_init_device() to return the allocated dev_data. Consolidate all
PCI cap inits (MSI domains, PASID, ATS) into a new helper:
iommu_init_device_caps().
Suggested-by: Vasant Hegde <vasant.hegde@amd.com>
Signed-off-by: Pranjal Shrivastava <praan@google.com>
---
drivers/iommu/amd/iommu.c | 117 +++++++++++++++++++-------------------
1 file changed, 60 insertions(+), 57 deletions(-)
diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
index 4c31294fabc5..e1f9fbb63837 100644
--- a/drivers/iommu/amd/iommu.c
+++ b/drivers/iommu/amd/iommu.c
@@ -675,7 +675,8 @@ static void pdev_disable_caps(struct pci_dev *pdev)
* This function checks if the driver got a valid device from the caller to
* avoid dereferencing invalid pointers.
*/
-static bool check_device(struct device *dev)
+static bool iommu_lookup_device(struct device *dev,
+ struct amd_iommu **iommu_out, u16 *devid_out)
{
struct amd_iommu_pci_seg *pci_seg;
struct amd_iommu *iommu;
@@ -690,7 +691,7 @@ static bool check_device(struct device *dev)
devid = PCI_SBDF_TO_DEVID(sbdf);
iommu = rlookup_amd_iommu(dev);
- if (!iommu)
+ if (!iommu || !iommu->iommu.ops)
return false;
/* Out of our scope? */
@@ -698,47 +699,33 @@ static bool check_device(struct device *dev)
if (devid > pci_seg->last_bdf)
return false;
+ *iommu_out = iommu;
+ *devid_out = devid;
return true;
}
-static int iommu_init_device(struct amd_iommu *iommu, struct device *dev)
+static struct iommu_dev_data *iommu_init_device(struct amd_iommu *iommu,
+ struct device *dev, u16 devid)
{
struct iommu_dev_data *dev_data;
- int devid, sbdf;
-
- if (dev_iommu_priv_get(dev))
- return 0;
- sbdf = get_device_sbdf_id(dev);
- if (sbdf < 0)
- return sbdf;
-
- devid = PCI_SBDF_TO_DEVID(sbdf);
dev_data = find_dev_data(iommu, devid);
if (!dev_data)
- return -ENOMEM;
+ return ERR_PTR(-ENOMEM);
dev_data->dev = dev;
/*
- * The dev_iommu_priv_set() needes to be called before setup_aliases.
+ * The dev_iommu_priv_set() needs to be called before setup_aliases.
* Otherwise, subsequent call to dev_iommu_priv_get() will fail.
*/
dev_iommu_priv_set(dev, dev_data);
setup_aliases(iommu, dev);
- /*
- * By default we use passthrough mode for IOMMUv2 capable device.
- * But if amd_iommu=force_isolation is set (e.g. to debug DMA to
- * invalid address), we ignore the capability for the device so
- * it'll be forced to go into translation mode.
- */
- if ((iommu_default_passthrough() || !amd_iommu_force_isolation) &&
- dev_is_pci(dev) && amd_iommu_gt_ppr_supported()) {
- dev_data->flags = pdev_get_caps(to_pci_dev(dev));
- }
+ /* Wait for DTE updates to go through */
+ iommu_completion_wait(iommu);
- return 0;
+ return dev_data;
}
static void iommu_ignore_device(struct amd_iommu *iommu, struct device *dev)
@@ -2477,49 +2464,75 @@ static void detach_device(struct device *dev)
mutex_unlock(&dev_data->mutex);
}
+static void iommu_init_device_caps(struct iommu_dev_data *dev_data,
+ struct device *dev,
+ struct amd_iommu *iommu)
+{
+ if (FEATURE_NUM_INT_REMAP_SUP_2K(amd_iommu_efr2))
+ dev_data->max_irqs = MAX_IRQS_PER_TABLE_2K;
+ else
+ dev_data->max_irqs = MAX_IRQS_PER_TABLE_512;
+
+ amd_iommu_set_pci_msi_domain(dev, iommu);
+
+ if (!dev_is_pci(dev))
+ return;
+
+ /*
+ * By default we use passthrough mode for IOMMUv2 capable device.
+ * But if amd_iommu=force_isolation is set (e.g. to debug DMA to
+ * invalid address), we ignore the capability for the device so
+ * it'll be forced to go into translation mode.
+ */
+ if ((iommu_default_passthrough() || !amd_iommu_force_isolation) &&
+ amd_iommu_gt_ppr_supported()) {
+ dev_data->flags = pdev_get_caps(to_pci_dev(dev));
+ }
+
+ /*
+ * If IOMMU and device supports PASID then it will contain max
+ * supported PASIDs, else it will be zero.
+ */
+ if (amd_iommu_pasid_supported() &&
+ pdev_pasid_supported(dev_data)) {
+ dev_data->max_pasids = min_t(u32, iommu->iommu.max_pasids,
+ pci_max_pasids(to_pci_dev(dev)));
+ }
+
+ pci_prepare_ats(to_pci_dev(dev), PAGE_SHIFT);
+}
+
static struct iommu_device *amd_iommu_probe_device(struct device *dev)
{
struct iommu_device *iommu_dev;
struct amd_iommu *iommu;
struct iommu_dev_data *dev_data;
int ret;
+ u16 devid;
- if (!check_device(dev))
- return ERR_PTR(-ENODEV);
-
- iommu = rlookup_amd_iommu(dev);
- if (!iommu)
- return ERR_PTR(-ENODEV);
-
- /* Not registered yet? */
- if (!iommu->iommu.ops)
+ if (!iommu_lookup_device(dev, &iommu, &devid))
return ERR_PTR(-ENODEV);
if (dev_iommu_priv_get(dev))
return &iommu->iommu;
- ret = iommu_init_device(iommu, dev);
- if (ret) {
+ dev_data = iommu_init_device(iommu, dev, devid);
+ if (IS_ERR(dev_data)) {
+ ret = PTR_ERR(dev_data);
dev_err(dev, "Failed to initialize - trying to proceed anyway\n");
iommu_dev = ERR_PTR(ret);
iommu_ignore_device(iommu, dev);
goto out_err;
}
- amd_iommu_set_pci_msi_domain(dev, iommu);
+ iommu_init_device_caps(dev_data, dev, iommu);
iommu_dev = &iommu->iommu;
-
+
/*
- * If IOMMU and device supports PASID then it will contain max
- * supported PASIDs, else it will be zero.
+ * When DMA translation is unavailable return error so the iommu core
+ * won't attempt domain attach for this device. But interrupt-remap
+ * is still supported. Hence do not ignore the device.
*/
- dev_data = dev_iommu_priv_get(dev);
- if (amd_iommu_pasid_supported() && dev_is_pci(dev) &&
- pdev_pasid_supported(dev_data)) {
- dev_data->max_pasids = min_t(u32, iommu->iommu.max_pasids,
- pci_max_pasids(to_pci_dev(dev)));
- }
-
if (amd_iommu_pgtable == PD_MODE_NONE) {
pr_warn_once("%s: DMA translation not supported by iommu.\n",
__func__);
@@ -2527,16 +2540,6 @@ static struct iommu_device *amd_iommu_probe_device(struct device *dev)
goto out_err;
}
- iommu_completion_wait(iommu);
-
- if (FEATURE_NUM_INT_REMAP_SUP_2K(amd_iommu_efr2))
- dev_data->max_irqs = MAX_IRQS_PER_TABLE_2K;
- else
- dev_data->max_irqs = MAX_IRQS_PER_TABLE_512;
-
- if (dev_is_pci(dev))
- pci_prepare_ats(to_pci_dev(dev), PAGE_SHIFT);
-
out_err:
return iommu_dev;
}
--
2.55.0.766.g2966f0265a-goog
next prev parent reply other threads:[~2026-08-24 12:24 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-24 12:23 [PATCH v3 0/5] iommu/amd: Refactors for ATS robustness Pranjal Shrivastava
2026-08-24 12:23 ` Pranjal Shrivastava [this message]
2026-08-24 18:13 ` [PATCH v3 1/5] iommu/amd: Refactor device probe and capability initialization Jason Gunthorpe
2026-08-25 10:24 ` Pranjal Shrivastava
2026-08-25 11:50 ` Jason Gunthorpe
2026-08-25 6:59 ` Vasant Hegde
2026-08-25 10:25 ` Pranjal Shrivastava
2026-08-24 12:23 ` [PATCH v3 2/5] iommu/amd: Fix DTE clearing and rename iommu_ignore_device() Pranjal Shrivastava
2026-08-24 18:13 ` Jason Gunthorpe
2026-08-25 10:32 ` Pranjal Shrivastava
2026-08-25 11:49 ` Jason Gunthorpe
2026-08-25 17:29 ` Pranjal Shrivastava
2026-08-25 17:53 ` Jason Gunthorpe
2026-08-25 19:08 ` Pranjal Shrivastava
2026-08-24 21:47 ` Samiullah Khawaja
2026-08-25 7:01 ` Vasant Hegde
2026-08-24 12:23 ` [PATCH v3 3/5] iommu/amd: Split probe error paths to preserve IRQ remapping Pranjal Shrivastava
2026-08-24 18:13 ` Jason Gunthorpe
2026-08-25 10:34 ` Pranjal Shrivastava
2026-08-24 12:23 ` [PATCH v3 4/5] iommu/amd: Fail probe on ATS configuration failure Pranjal Shrivastava
2026-08-24 18:13 ` Jason Gunthorpe
2026-08-24 21:46 ` Samiullah Khawaja
2026-08-24 12:23 ` [PATCH v3 5/5] PCI/ATS: Mandate checking pci_ats_supported() before pci_prepare_ats() Pranjal Shrivastava
2026-08-24 18:13 ` Jason Gunthorpe
2026-08-24 18:13 ` [PATCH v3 0/5] iommu/amd: Refactors for ATS robustness Jason Gunthorpe
2026-08-25 10:39 ` Pranjal Shrivastava
2026-08-25 11:51 ` Jason Gunthorpe
2026-08-25 7:06 ` Vasant Hegde
2026-08-25 10:37 ` Pranjal Shrivastava
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