[PATCH v1 0/2] clk: tegra114: Add CSI pad clock gates

[PATCH v1 0/2] clk: tegra114: Add CSI pad clock gates

[Svyatoslav Ryhel]

Tegra114 has CSI pad bits in both PLLD and PLLD2 clocks that are required
for the correct work of the CSI block. Add CSI pad A and pad B clock gates
with PLLD/PLLD2 parents, respectively.

This change is similar to Tegra30 pad clocks and is required for CSI block.

Svyatoslav Ryhel (2):
  dt-bindings: clock: tegra114: Add IDs for CSI pad clocks
  clk: tegra114: Add CSI pad clock gates

 drivers/clk/tegra/clk-tegra114.c         | 11 +++++++++++
 include/dt-bindings/clock/tegra114-car.h |  3 ++-
 2 files changed, 13 insertions(+), 1 deletion(-)

-- 
2.53.0

[PATCH v1 1/2] dt-bindings: clock: tegra114: Add IDs for CSI pad clocks

[Svyatoslav Ryhel]

Tegra114 has CSI pad clock enable bits embedded into PLLD/PLLD2 registers.
Add ids for these clocks. Additionally, move TEGRA114_CLK_CLK_MAX into
clk-tegra114 source.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
---
 drivers/clk/tegra/clk-tegra114.c         | 1 +
 include/dt-bindings/clock/tegra114-car.h | 3 ++-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 97f5500b13b5f..80b7f64125d92 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -47,6 +47,7 @@
 #define CPU_FINETRIM_R_FCPU_6_MASK	(0x3 << CPU_FINETRIM_R_FCPU_6_SHIFT)
 
 #define TEGRA114_CLK_PERIPH_BANKS	5
+#define TEGRA114_CLK_CLK_MAX		314
 
 #define PLLC_BASE 0x80
 #define PLLC_MISC2 0x88
diff --git a/include/dt-bindings/clock/tegra114-car.h b/include/dt-bindings/clock/tegra114-car.h
index a93426f008acc..b53f5942f4bae 100644
--- a/include/dt-bindings/clock/tegra114-car.h
+++ b/include/dt-bindings/clock/tegra114-car.h
@@ -341,6 +341,7 @@
 #define TEGRA114_CLK_DSIA_MUX 309
 #define TEGRA114_CLK_DSIB_MUX 310
 #define TEGRA114_CLK_XUSB_SS_DIV2 311
-#define TEGRA114_CLK_CLK_MAX 312
+#define TEGRA114_CLK_CSIA_PAD 312
+#define TEGRA114_CLK_CSIB_PAD 313
 
 #endif	/* _DT_BINDINGS_CLOCK_TEGRA114_CAR_H */
-- 
2.53.0

[PATCH v1 2/2] clk: tegra114: Add CSI pad clock gates

[Svyatoslav Ryhel]

Tegra114 has CSI pad bits in both PLLD and PLLD2 clocks that are required
for the correct work of the CSI block. Add CSI pad A and pad B clock gates
with PLLD/PLLD2 parents, respectively.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
---
 drivers/clk/tegra/clk-tegra114.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 80b7f64125d92..e3d8ab76db649 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -1041,6 +1041,16 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base,
 					     0, 82, periph_clk_enb_refcnt);
 	clks[TEGRA114_CLK_DSIB] = clk;
 
+	/* csia_pad */
+	clk = clk_register_gate(NULL, "csia_pad", "pll_d", CLK_SET_RATE_PARENT,
+				clk_base + PLLD_BASE, 26, 0, &pll_d_lock);
+	clks[TEGRA114_CLK_CSIA_PAD] = clk;
+
+	/* csib_pad */
+	clk = clk_register_gate(NULL, "csib_pad", "pll_d2", CLK_SET_RATE_PARENT,
+				clk_base + PLLD2_BASE, 26, 0, &pll_d2_lock);
+	clks[TEGRA114_CLK_CSIB_PAD] = clk;
+
 	/* csus */
 	clk = tegra_clk_register_periph_gate("csus", "vi_sensor", 0,
 					     clk_base, 0, TEGRA114_CLK_CSUS,
-- 
2.53.0

Re: [PATCH v1 1/2] dt-bindings: clock: tegra114: Add IDs for CSI pad clocks

[Conor Dooley]

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On Fri, Nov 13, 2026 at 04:57:07PM +0200, Svyatoslav Ryhel wrote:
> Tegra114 has CSI pad clock enable bits embedded into PLLD/PLLD2 registers.
> Add ids for these clocks. Additionally, move TEGRA114_CLK_CLK_MAX into
> clk-tegra114 source.
> 
> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> ---
>  drivers/clk/tegra/clk-tegra114.c         | 1 +
>  include/dt-bindings/clock/tegra114-car.h | 3 ++-
>  2 files changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
> index 97f5500b13b5f..80b7f64125d92 100644
> --- a/drivers/clk/tegra/clk-tegra114.c
> +++ b/drivers/clk/tegra/clk-tegra114.c
> @@ -47,6 +47,7 @@
>  #define CPU_FINETRIM_R_FCPU_6_MASK	(0x3 << CPU_FINETRIM_R_FCPU_6_SHIFT)
>  
>  #define TEGRA114_CLK_PERIPH_BANKS	5
> +#define TEGRA114_CLK_CLK_MAX		314
>  
>  #define PLLC_BASE 0x80
>  #define PLLC_MISC2 0x88
> diff --git a/include/dt-bindings/clock/tegra114-car.h b/include/dt-bindings/clock/tegra114-car.h
> index a93426f008acc..b53f5942f4bae 100644
> --- a/include/dt-bindings/clock/tegra114-car.h
> +++ b/include/dt-bindings/clock/tegra114-car.h
> @@ -341,6 +341,7 @@
>  #define TEGRA114_CLK_DSIA_MUX 309
>  #define TEGRA114_CLK_DSIB_MUX 310
>  #define TEGRA114_CLK_XUSB_SS_DIV2 311

> -#define TEGRA114_CLK_CLK_MAX 312

Good riddance.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable

> +#define TEGRA114_CLK_CSIA_PAD 312
> +#define TEGRA114_CLK_CSIB_PAD 313
>  
>  #endif	/* _DT_BINDINGS_CLOCK_TEGRA114_CAR_H */
> -- 
> 2.53.0
> 

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Re: [PATCH v1 2/2] clk: tegra114: Add CSI pad clock gates

[Jerome Brunet]

> Tegra114 has CSI pad bits in both PLLD and PLLD2 clocks that are required
> for the correct work of the CSI block. Add CSI pad A and pad B clock gates
> with PLLD/PLLD2 parents, respectively.
> 
> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> ---
>  drivers/clk/tegra/clk-tegra114.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
>
> diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
> index ec537efac692..08e425365469 100644
> --- a/drivers/clk/tegra/clk-tegra114.c
> +++ b/drivers/clk/tegra/clk-tegra114.c
> @@ -1041,6 +1041,16 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base,
>  					     0, 82, periph_clk_enb_refcnt);
>  	clks[TEGRA114_CLK_DSIB] = clk;
>  
> +	/* csia_pad */
> +	clk = clk_register_gate(NULL, "csia_pad", "pll_d", CLK_SET_RATE_PARENT,
> +				clk_base + PLLD_BASE, 26, 0, &pll_d_lock);
> +	clks[TEGRA114_CLK_CSIA_PAD] = clk;
> +
> +	/* csib_pad */
> +	clk = clk_register_gate(NULL, "csib_pad", "pll_d2", CLK_SET_RATE_PARENT,
> +				clk_base + PLLD2_BASE, 26, 0, &pll_d2_lock);
> +	clks[TEGRA114_CLK_CSIB_PAD] = clk;
> +

Change seems ok in itself, just a couple of things I'd like to check with you.

Seems both the CSI and DSI can use the PLL D and D2. Can they be used concurrently ?
If yes, are you sure you want to add CLK_SET_RATE_PARENT which the
DSI counter part does not have ?

Also the DSI get the PLL through a fixed factor 'out0' but not the CSI ? is it something
you have checked ? it just seems a little odd.

-- 
Jerome

Re: [PATCH v1 2/2] clk: tegra114: Add CSI pad clock gates

[Svyatoslav Ryhel]

нд, 15 лист. 2026 р. о 13:03 Jerome Brunet <jbrunet@baylibre.com> пише:
>
> > Tegra114 has CSI pad bits in both PLLD and PLLD2 clocks that are required
> > for the correct work of the CSI block. Add CSI pad A and pad B clock gates
> > with PLLD/PLLD2 parents, respectively.
> >
> > Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> > ---
> >  drivers/clk/tegra/clk-tegra114.c | 10 ++++++++++
> >  1 file changed, 10 insertions(+)
> >
> > diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
> > index ec537efac692..08e425365469 100644
> > --- a/drivers/clk/tegra/clk-tegra114.c
> > +++ b/drivers/clk/tegra/clk-tegra114.c
> > @@ -1041,6 +1041,16 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base,
> >                                            0, 82, periph_clk_enb_refcnt);
> >       clks[TEGRA114_CLK_DSIB] = clk;
> >
> > +     /* csia_pad */
> > +     clk = clk_register_gate(NULL, "csia_pad", "pll_d", CLK_SET_RATE_PARENT,
> > +                             clk_base + PLLD_BASE, 26, 0, &pll_d_lock);
> > +     clks[TEGRA114_CLK_CSIA_PAD] = clk;
> > +
> > +     /* csib_pad */
> > +     clk = clk_register_gate(NULL, "csib_pad", "pll_d2", CLK_SET_RATE_PARENT,
> > +                             clk_base + PLLD2_BASE, 26, 0, &pll_d2_lock);
> > +     clks[TEGRA114_CLK_CSIB_PAD] = clk;
> > +
>
> Change seems ok in itself, just a couple of things I'd like to check with you.
>
> Seems both the CSI and DSI can use the PLL D and D2. Can they be used concurrently ?
> If yes, are you sure you want to add CLK_SET_RATE_PARENT which the
> DSI counter part does not have ?
>

CSI pad clocks are used only by CSI and CSI does not change rate of
pad clocks. Saying "DSI counter part" would not be correct, DSI mux
switched DSI clock parent while csi pad clocks do not touch clock
layout of CSI nor DSI.

Same layout is used in Tegra30 and Tegra114 inherits it.

> Also the DSI get the PLL through a fixed factor 'out0' but not the CSI ? is it something
> you have checked ? it just seems a little odd.
>

Yes, out0 is a fixed div2 of DSI clocks and that is code reflection of
hardware. CSI pad clocks do not have this setup in the hardware.

> --
> Jerome
>