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From: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
To: Richard Cheng <icheng@nvidia.com>
Cc: tony.luck@intel.com, Reinette Chatre <reinette.chatre@intel.com>,
	 shuah@kernel.org, Dave.Martin@arm.com, james.morse@arm.com,
	 babu.moger@amd.com, LKML <linux-kernel@vger.kernel.org>,
	 linux-kselftest@vger.kernel.org, fenghuay@nvidia.com,
	newtonl@nvidia.com,  kristinc@nvidia.com, kaihengf@nvidia.com,
	kobak@nvidia.com
Subject: Re: [PATCH v2 3/3] selftests/resctrl: Recognise aarch64 as a vendor for L3_NONCONT_CAT
Date: Thu, 28 May 2026 14:01:34 +0300 (EEST)	[thread overview]
Message-ID: <215fc6b6-9fc6-29a3-986e-f195c7c8da79@linux.intel.com> (raw)
In-Reply-To: <20260528102956.33121-4-icheng@nvidia.com>

On Thu, 28 May 2026, Richard Cheng wrote:

> aarch64 has no vendor_id in /proc/cpuinfo, so detect_vendor() returns 0
> and arch_supports_noncont_cat() falls through to "return false".
> L3_NONCONT_CAT therefore spuriously fails on every ARM MPAM platform.
> 
> Define ARCH_ARM, short-circuit detect_vendor() to it on aarch64, and
> add it to the AMD/Hygon always-supports early-out in
> arch_supports_noncont_cat().
> 
> aarch64 has many implementers (ARM 0x41, NVIDIA 0x43, etc.), but MPAM
> mandates non-contiguous CPBM uniformly, so per-implementer handling is
> not needed here.
> 
> Signed-off-by: Richard Cheng <icheng@nvidia.com>
> ---
>  tools/testing/selftests/resctrl/cat_test.c      |  9 +++++++--
>  tools/testing/selftests/resctrl/resctrl.h       |  1 +
>  tools/testing/selftests/resctrl/resctrl_tests.c | 11 +++++++++++
>  3 files changed, 19 insertions(+), 2 deletions(-)
> 
> diff --git a/tools/testing/selftests/resctrl/cat_test.c b/tools/testing/selftests/resctrl/cat_test.c
> index dc414e55ae94..ce66016dbd88 100644
> --- a/tools/testing/selftests/resctrl/cat_test.c
> +++ b/tools/testing/selftests/resctrl/cat_test.c
> @@ -292,8 +292,13 @@ static bool arch_supports_noncont_cat(const struct resctrl_test *test)
>  {
>  	unsigned int vendor_id = get_vendor();
>  
> -	/* AMD and Hygon always support non-contiguous CBM. */
> -	if (vendor_id == ARCH_AMD || vendor_id == ARCH_HYGON)
> +	/*
> +	 * AMD and Hygon always support non-contiguous CBM. ARM/MPAM defines
> +	 * MPAMCFG_CPBM as a bitmap with no contiguity constraint per ARM
> +	 * DDI 0598.
> +	 */
> +	if (vendor_id == ARCH_AMD || vendor_id == ARCH_HYGON ||
> +	    vendor_id == ARCH_ARM)
>  		return true;
>  
>  #if defined(__i386__) || defined(__x86_64__) /* arch */
> diff --git a/tools/testing/selftests/resctrl/resctrl.h b/tools/testing/selftests/resctrl/resctrl.h
> index afe635b6e48d..670e5b128b4d 100644
> --- a/tools/testing/selftests/resctrl/resctrl.h
> +++ b/tools/testing/selftests/resctrl/resctrl.h
> @@ -40,6 +40,7 @@
>  #define ARCH_INTEL	BIT(0)
>  #define ARCH_AMD	BIT(1)
>  #define ARCH_HYGON	BIT(2)
> +#define ARCH_ARM	BIT(3)
>  
>  #define END_OF_TESTS	1
>  
> diff --git a/tools/testing/selftests/resctrl/resctrl_tests.c b/tools/testing/selftests/resctrl/resctrl_tests.c
> index dbcd5eea9fbc..b28dae83d0a4 100644
> --- a/tools/testing/selftests/resctrl/resctrl_tests.c
> +++ b/tools/testing/selftests/resctrl/resctrl_tests.c
> @@ -34,6 +34,17 @@ static unsigned int detect_vendor(void)
>  	if (initialized)
>  		return vendor_id;
>  
> +#if defined(__aarch64__)
> +	/*
> +	 * aarch64 has no userspace vendor_id in /proc/cpuinfo. MPAM-capable
> +	 * ARM implementations follow ARM DDI 0598; treat all aarch64 builds
> +	 * as a single vendor for the purposes of resctrl selftests.
> +	 */
> +	vendor_id = ARCH_ARM;
> +	initialized = true;
> +	return vendor_id;
> +#endif

It would be better to create a detect_aarch64() function and put 
the ifdeffery inside it so it returns either true or false here.

> +
>  	inf = fopen("/proc/cpuinfo", "r");
>  	if (!inf) {
>  		vendor_id = 0;
> 

-- 
 i.


      reply	other threads:[~2026-05-28 11:01 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-28 10:29 [PATCH v2 0/3] selftests/resctrl: Fix resctrl selftests issues on aarch64 Richard Cheng
2026-05-28 10:29 ` [PATCH v2 1/3] selftests/resctrl: Skip L3_CAT when no exclusive cache portion exists Richard Cheng
2026-05-28 11:03   ` Ilpo Järvinen
2026-05-28 10:29 ` [PATCH v2 2/3] selftests/resctrl: Implement cl_flush() and sb() for aarch64 Richard Cheng
2026-05-28 10:29 ` [PATCH v2 3/3] selftests/resctrl: Recognise aarch64 as a vendor for L3_NONCONT_CAT Richard Cheng
2026-05-28 11:01   ` Ilpo Järvinen [this message]

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