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From: Dave Jiang <dave.jiang@intel.com>
To: Gregory Price <gourry@gourry.net>, linux-cxl@vger.kernel.org
Cc: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
	kernel-team@meta.com, dave@stgolabs.net,
	jonathan.cameron@huawei.com, alison.schofield@intel.com,
	vishal.l.verma@intel.com, ira.weiny@intel.com,
	dan.j.williams@intel.com, corbet@lwn.net, rakuram.e96@gmail.com,
	alucerop@amd.com
Subject: Re: [PATCH v3 1/2] Documentation/driver-api/cxl: BIOS/EFI expectation update
Date: Mon, 5 Jan 2026 14:00:02 -0700	[thread overview]
Message-ID: <2fb3f73d-a808-4a6a-a90e-b83a32a4da57@intel.com> (raw)
In-Reply-To: <20251219170538.1675743-2-gourry@gourry.net>



On 12/19/25 10:05 AM, Gregory Price wrote:
> Add a snippet about what Linux expects BIOS/EFI to do (and not
> to do) to the BIOS/EFI section.
> 
> Suggested-by: Alejandro Lucero Palau <alucerop@amd.com>
> Signed-off-by: Gregory Price <gourry@gourry.net>

Reviewed-by: Dave Jiang <dave.jiang@intel.com>

> ---
>  .../driver-api/cxl/platform/bios-and-efi.rst  | 20 +++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 
> diff --git a/Documentation/driver-api/cxl/platform/bios-and-efi.rst b/Documentation/driver-api/cxl/platform/bios-and-efi.rst
> index a9aa0ccd92af..9034c206cf8e 100644
> --- a/Documentation/driver-api/cxl/platform/bios-and-efi.rst
> +++ b/Documentation/driver-api/cxl/platform/bios-and-efi.rst
> @@ -29,6 +29,26 @@ at :doc:`ACPI Tables <acpi>`.
>     on physical memory region size and alignment, memory holes, HDM interleave,
>     and what linux expects of HDM decoders trying to work with these features.
>  
> +
> +Linux Expectations of BIOS/EFI Software
> +=======================================
> +Linux expects BIOS/EFI software to construct sufficient ACPI tables (such as
> +CEDT, SRAT, HMAT, etc) and platform-specific configurations (such as HPA spaces
> +and host-bridge interleave configurations) to allow the Linux driver to
> +subsequently configure the devices in the CXL fabric at runtime.
> +
> +Programming of HDM decoders and switch ports is not required, and may be
> +deferred to the CXL driver based on admin policy (e.g. udev rules).
> +
> +Some platforms may require pre-programming HDM decoders and locking them
> +due to quirks (see: Zen5 address translation), but this is not the normal,
> +"expected" configuration path.  This should be avoided if possible.
> +
> +Some platforms may wish to pre-configure these resources to bring memory
> +up without requiring CXL driver support.  These platform vendors should
> +test their configurations with the existing CXL driver and provide driver
> +support for their auto-configurations if features like RAS are required.
> +
>  UEFI Settings
>  =============
>  If your platform supports it, the :code:`uefisettings` command can be used to


  parent reply	other threads:[~2026-01-05 21:00 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-12-19 17:05 [PATCH v3 0/2] Documentation/driver-api/cxl: device hotplug Gregory Price
2025-12-19 17:05 ` [PATCH v3 1/2] Documentation/driver-api/cxl: BIOS/EFI expectation update Gregory Price
2025-12-19 17:28   ` Jonathan Cameron
2025-12-19 17:49     ` Gregory Price
2025-12-20  6:53   ` Alejandro Lucero Palau
2026-01-05 21:00   ` Dave Jiang [this message]
2025-12-19 17:05 ` [PATCH v3 2/2] Documentation/driver-api/cxl: device hotplug section Gregory Price
2025-12-20  6:56   ` Alejandro Lucero Palau
2026-01-05 21:10   ` Dave Jiang
2026-01-07  2:19   ` Alison Schofield
2026-01-07 15:54     ` Gregory Price
2026-01-08  5:42       ` Alison Schofield
2026-01-06 17:54 ` [PATCH v3 0/2] Documentation/driver-api/cxl: device hotplug Dave Jiang

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