From: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
To: "Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Jingoo Han" <jingoohan1@gmail.com>,
"Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
konrad.dybcio@oss.qualcomm.com, quic_mrana@quicinc.com,
quic_vbadigan@quicinc.com, Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Krishna chaitanya chundru <quic_krichai@quicinc.com>
Subject: Re: [PATCH v2 0/4] PCI: dwc: Add support for configuring lane equalization presets
Date: Thu, 12 Dec 2024 16:10:30 +0530 [thread overview]
Message-ID: <39012a4a-7d02-b954-bc06-53708b772a7c@oss.qualcomm.com> (raw)
In-Reply-To: <20241212-preset_v2-v2-0-210430fbcd8a@oss.qualcomm.com>
Please ignore this series it has wrong patches I will send new series to
fix this.
- Krishna Chaitanya.
On 12/12/2024 4:02 PM, Krishna Chaitanya Chundru wrote:
> PCIe equalization presets are predefined settings used to optimize
> signal integrity by compensating for signal loss and distortion in
> high-speed data transmission.
>
> As per PCIe spec 6.0.1 revision section 8.3.3.3 & 4.2.4 for data rates
> of 8.0 GT/s, 16.0 GT/s, 32.0 GT/s, and 64.0 GT/s, there is a way to
> configure lane equalization presets for each lane to enhance the PCIe
> link reliability. Each preset value represents a different combination
> of pre-shoot and de-emphasis values. For each data rate, different
> registers are defined: for 8.0 GT/s, registers are defined in section
> 7.7.3.4; for 16.0 GT/s, in section 7.7.5.9, etc. The 8.0 GT/s rate has
> an extra receiver preset hint, requiring 16 bits per lane, while the
> remaining data rates use 8 bits per lane.
>
> Based on the number of lanes and the supported data rate, read the
> device tree property and stores in the presets structure.
>
> Based upon the lane width and supported data rate update lane
> equalization registers.
>
> This patch depends on the this dt binding pull request: https://github.com/devicetree-org/dt-schema/pull/146
>
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
> ---
> Changes in v2:
> - Fix the kernel test robot error
> - As suggested by konrad use for loop and read "eq-presets-%ugts", (8 << i)
> - Link to v1: https://lore.kernel.org/r/20241116-presets-v1-0-878a837a4fee@quicinc.com
>
> ---
> Krishna chaitanya chundru (4):
> arm64: dts: qcom: x1e80100: Add PCIe lane equalization preset properties
> PCI: of: Add API to retrieve equalization presets from device tree
> PCI: dwc: Improve handling of PCIe lane configuration
> PCI: dwc: Add support for new pci function op
>
> arch/arm64/boot/dts/qcom/x1e80100.dtsi | 8 ++++
> drivers/pci/controller/dwc/pcie-designware-host.c | 21 +++++++++++
> drivers/pci/controller/dwc/pcie-designware.c | 14 ++++++-
> drivers/pci/controller/dwc/pcie-designware.h | 1 +
> drivers/pci/of.c | 45 +++++++++++++++++++++++
> drivers/pci/pci.h | 17 ++++++++-
> 6 files changed, 103 insertions(+), 3 deletions(-)
> ---
> base-commit: 87d6aab2389e5ce0197d8257d5f8ee965a67c4cd
> change-id: 20241212-preset_v2-549b7acda9b7
>
> Best regards,
next prev parent reply other threads:[~2024-12-12 10:40 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-12-12 10:32 [PATCH v2 0/4] PCI: dwc: Add support for configuring lane equalization presets Krishna Chaitanya Chundru
2024-12-12 10:32 ` [PATCH v2 1/4] arm64: dts: qcom: x1e80100: Add PCIe lane equalization preset properties Krishna Chaitanya Chundru
2024-12-12 12:25 ` Krzysztof Kozlowski
2024-12-12 12:32 ` Krishna Chaitanya Chundru
2024-12-12 12:37 ` Krzysztof Kozlowski
2024-12-12 10:32 ` [PATCH v2 2/4] PCI: of: Add API to retrieve equalization presets from device tree Krishna Chaitanya Chundru
2024-12-12 10:32 ` [PATCH v2 3/4] PCI: dwc: Improve handling of PCIe lane configuration Krishna Chaitanya Chundru
2024-12-12 10:32 ` [PATCH v2 4/4] PCI: dwc: Add support for new pci function op Krishna Chaitanya Chundru
2024-12-12 10:40 ` Krishna Chaitanya Chundru [this message]
2024-12-12 12:26 ` [PATCH v2 0/4] PCI: dwc: Add support for configuring lane equalization presets Krzysztof Kozlowski
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=39012a4a-7d02-b954-bc06-53708b772a7c@oss.qualcomm.com \
--to=krishna.chundru@oss.qualcomm.com \
--cc=andersson@kernel.org \
--cc=bhelgaas@google.com \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=jingoohan1@gmail.com \
--cc=konrad.dybcio@oss.qualcomm.com \
--cc=konradybcio@kernel.org \
--cc=krzk+dt@kernel.org \
--cc=kw@linux.com \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=lpieralisi@kernel.org \
--cc=manivannan.sadhasivam@linaro.org \
--cc=quic_krichai@quicinc.com \
--cc=quic_mrana@quicinc.com \
--cc=quic_vbadigan@quicinc.com \
--cc=robh@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox