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* Re: P4 SMP load balancing
@ 2001-10-12 18:38 Manfred Spraul
  2001-10-12 21:38 ` Martin J. Bligh
  0 siblings, 1 reply; 5+ messages in thread
From: Manfred Spraul @ 2001-10-12 18:38 UTC (permalink / raw)
  To: Martin J. Bligh, linux-kernel, Sean Cavanaugh

 
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> > ovendev:~# cat /proc/interrupts 
> >            CPU0       CPU1       
> >   0:    6348212          0    IO-APIC-edge  timer
> >   1:          2          0    IO-APIC-edge  keyboard
> >   2:          0          0          XT-PIC  cascade
> >   8:          1          0    IO-APIC-edge  rtc
> >   9:          0          0    IO-APIC-edge  acpi
> >  16:      92620          0   IO-APIC-level  eth0
> >  18:       5085          0   IO-APIC-level  aic7xxx, aic7xxx
> > NMI:          0          0 
> > LOC:    6348388    6348427 
> > ERR:          0
> > MIS:          0
> 
> I don't think this should happen. In the event of both procs having equal 
> priority (linux never changes them, so they always do), we should fall back 
> to the arbitration priority of the lapic. Whether you have 1 or 2 I/O apics
> working shouldn't make a difference. 

The P 4 has a new apic, and lowest priority delivery doesn't work
anymore.

<<<<<<< Chapter 7.6.10 of 24547202.pdf
In operating systems that use the lowest priority interrupt delivery
mode
but do not update the TPR, the TPR information saved in the chipset will
potentially cause the interrupt to be always delivered to the same
processor from the logical set. This behavior is functionally backward
compatible with the P6 family processor but may result in unexpected
performance implications.
<<<<<<< (search for 245472 on google for the pdf file)


--
	Manfred

^ permalink raw reply	[flat|nested] 5+ messages in thread
* P4 SMP load balancing
@ 2001-10-12  9:28 Sean Cavanaugh
  2001-10-12 17:59 ` Martin J. Bligh
  0 siblings, 1 reply; 5+ messages in thread
From: Sean Cavanaugh @ 2001-10-12  9:28 UTC (permalink / raw)
  To: linux-kernel

I posted this a while back in linux-smp (which seems like a dead list?)

I have several P4 Xeon SMP systems (Supermicro P4DCE, Intel i860
chipset)

ovendev:~# cat /proc/interrupts 
           CPU0       CPU1       
  0:    6348212          0    IO-APIC-edge  timer
  1:          2          0    IO-APIC-edge  keyboard
  2:          0          0          XT-PIC  cascade
  8:          1          0    IO-APIC-edge  rtc
  9:          0          0    IO-APIC-edge  acpi
 16:      92620          0   IO-APIC-level  eth0
 18:       5085          0   IO-APIC-level  aic7xxx, aic7xxx
NMI:          0          0 
LOC:    6348388    6348427 
ERR:          0
MIS:          0


	How much of a problem is this really?  The program's I am
running on these systems (I have 9 of them) seem do ok right now.
Currently the jobs running on them are heavily CPU bound and don't do
any I/O, but this is going to change when I link them up over a private
network so they can work together on some distributable jobs).  I am
running 2.4.10 on most of them, and 2.4.10-ac10 on my developer system
in the farm.  The only difference this newer kernel seems to have made
from older ones is that there is only one 'warning unexpected IO-APIC'
message in my startup instead of two.


Snippet from dmesg:

CPU1: Intel(R) Xeon(TM) CPU 1700MHz stepping 0a
Total of 2 processors activated (6723.99 BogoMIPS).
ENABLING IO-APIC IRQs
...changing IO-APIC physical APIC ID to 2 ... ok.
init IO_APIC IRQs
 IO-APIC (apicid-pin) 2-0, 2-5, 2-10, 2-11, 2-12, 2-17, 2-20, 2-21, 2-22
not connected.
..TIMER: vector=0x31 pin1=2 pin2=0
number of MP IRQ sources: 18.
number of IO-APIC #2 registers: 24.
testing the IO APIC.......................

IO APIC #2......
.... register #00: 02000000
.......    : physical APIC id: 02
.... register #01: 00178020
.......     : max redirection entries: 0017
.......     : PRQ implemented: 1
.......     : IO APIC version: 0020
 WARNING: unexpected IO-APIC, please mail
          to linux-smp@vger.kernel.org
.... register #02: 00000000
.......     : arbitration: 00
.... IRQ redirection table: 
<snip>



	- Sean


^ permalink raw reply	[flat|nested] 5+ messages in thread
end of thread, other threads:[~2001-10-14  9:07 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2001-10-12 18:38 P4 SMP load balancing Manfred Spraul
2001-10-12 21:38 ` Martin J. Bligh
  -- strict thread matches above, loose matches on Subject: below --
2001-10-12  9:28 Sean Cavanaugh
2001-10-12 17:59 ` Martin J. Bligh
2001-10-14  9:07   ` Sean Cavanaugh

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