From: Larisa Ileana Grigore <larisa.grigore@oss.nxp.com>
To: Krzysztof Kozlowski <krzk@kernel.org>, Frank.Li@nxp.com
Cc: dmaengine@vger.kernel.org, imx@lists.linux.dev,
linux-kernel@vger.kernel.org, s32@nxp.com,
Christophe Lizzi <clizzi@redhat.com>,
Alberto Ruiz <aruizrui@redhat.com>,
Enric Balletbo <eballetb@redhat.com>
Subject: Re: [PATCH 7/8] dmaengine: fsl-edma: wait until no hardware request is in progress
Date: Wed, 18 Dec 2024 15:24:34 +0200 [thread overview]
Message-ID: <458f8940-4451-4dbd-bd50-75a43e4248d3@oss.nxp.com> (raw)
In-Reply-To: <2e0e1fe3-af5e-4416-8b34-3fecb923b481@kernel.org>
On 12/17/2024 5:27 PM, Krzysztof Kozlowski wrote:
> On 17/12/2024 15:19, Larisa Ileana Grigore wrote:
>> On 12/17/2024 7:27 AM, Krzysztof Kozlowski wrote:
>>> [You don't often get email from krzk@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>>>
>>> On 16/12/2024 08:58, Larisa Grigore wrote:
>>>> Wait DMA hardware complete cleanup work by checking HRS bit before
>>>> disabling the channel to make sure trail data is already written to
>>>> memory.
>>>>
>>>> Fixes: 72f5801a4e2b7 ("dmaengine: fsl-edma: integrate v3 support")
>>>
>>> Why Fixes are at the end of the patchset? They must be either separate
>>> patchset or first patches.
>>>
>>> Best regards,
>>> Krzysztof
>>
>> Thank you for you review Krzysztof! Indeed, this commit should be moved
>> right after "dmaengine: fsl-edma: add eDMAv3 registers to edma_regs"
>
> I don't understand this. Are you saying you introduce bug in one patch
> and fix in other? Why this cannot be separate patchset?
The bug was introduced by 72f5801a4e2b7 ("dmaengine: fsl-edma: integrate
v3 support"), commit which is already upstream.
In the proposed fix, a channel is disabled after checking the HRS
register which is a eDMAv3 specific register.
In the upstream implementation, "struct edma_regs" is created based on
the eDMAv2 register layout [1] which is different compared to the eDMAv3
register layout.
The "hrs" field, which is used to access the HRS register, was
introduced in one of the patches from this set [2].
So, this fix depends on two other commits:
"dmaengine: fsl-edma: add eDMAv3 registers to edma_regs" [2]
"dmaengine: fsl-edma: move eDMAv2 related registers to a new structure
’edma2_regs’" [3]
"dmaengine: fsl-edma: add support for S32G based platforms" [4] depends
also on [2] because it reads another eDMAv3 specific register "ES". This
is the reason I've sent all these patches together.
Please let me know your thoughts.
[1]
https://elixir.bootlin.com/linux/v6.12.4/source/drivers/dma/fsl-edma-common.h#L123
[2]
https://lore.kernel.org/all/20241216075819.2066772-5-larisa.grigore@oss.nxp.com/
[3]
https://lore.kernel.org/all/20241216075819.2066772-4-larisa.grigore@oss.nxp.com/
[4]
https://lore.kernel.org/all/20241216075819.2066772-7-larisa.grigore@oss.nxp.com/
> Best regards,
> Krzysztof
Best regards,
Larisa
next prev parent reply other threads:[~2024-12-18 13:24 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-12-16 7:58 [PATCH 0/8] Add eDMAv3 support for S32G2/S32G3 SoCs Larisa Grigore
2024-12-16 7:58 ` [PATCH 1/8] dmaengine: fsl-edma: select of_dma_xlate based on the dmamuxs presence Larisa Grigore
2024-12-16 16:16 ` Frank Li
2024-12-17 14:28 ` Larisa Ileana Grigore
2024-12-16 7:58 ` [PATCH 2/8] dmaengine: fsl-edma: remove FSL_EDMA_DRV_SPLIT_REG check when parsing muxbase Larisa Grigore
2024-12-16 16:17 ` Frank Li
2024-12-16 7:58 ` [PATCH 3/8] dmaengine: fsl-edma: move eDMAv2 related registers to a new structure ’edma2_regs’ Larisa Grigore
2024-12-16 16:17 ` Frank Li
2024-12-17 14:27 ` Larisa Ileana Grigore
2024-12-16 7:58 ` [PATCH 4/8] dmaengine: fsl-edma: add eDMAv3 registers to edma_regs Larisa Grigore
2024-12-16 16:18 ` Frank Li
2024-12-16 7:58 ` [PATCH 5/8] dt-bindings: dma: fsl-edma: add nxp,s32g2-edma compatible string Larisa Grigore
2024-12-16 16:18 ` Frank Li
2024-12-17 5:26 ` Krzysztof Kozlowski
2024-12-17 14:26 ` Larisa Ileana Grigore
2024-12-16 7:58 ` [PATCH 6/8] dmaengine: fsl-edma: add support for S32G based platforms Larisa Grigore
2024-12-16 16:20 ` Frank Li
2024-12-16 7:58 ` [PATCH 7/8] dmaengine: fsl-edma: wait until no hardware request is in progress Larisa Grigore
2024-12-17 5:27 ` Krzysztof Kozlowski
2024-12-17 14:19 ` Larisa Ileana Grigore
2024-12-17 15:27 ` Krzysztof Kozlowski
2024-12-18 13:24 ` Larisa Ileana Grigore [this message]
2024-12-18 13:32 ` Krzysztof Kozlowski
2024-12-18 13:38 ` Larisa Ileana Grigore
2024-12-18 14:10 ` Krzysztof Kozlowski
2024-12-18 15:39 ` Frank Li
2024-12-16 7:58 ` [PATCH 8/8] dmaengine: fsl-edma: read/write multiple registers in cyclic transactions Larisa Grigore
2024-12-16 16:09 ` [PATCH 0/8] Add eDMAv3 support for S32G2/S32G3 SoCs Frank Li
2024-12-16 16:22 ` Frank Li
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