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From: christophe leroy <christophe.leroy@c-s.fr>
To: Peter Zijlstra <a.p.zijlstra@chello.nl>,
	Paul Mackerras <paulus@samba.org>, Ingo Molnar <mingo@redhat.com>,
	Arnaldo Carvalho de Melo <acme@ghostprotocols.net>
Cc: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: perf events: how to implement TLB misses as SW event ?
Date: Sun, 24 Nov 2013 19:10:58 +0100	[thread overview]
Message-ID: <52924132.2080209@c-s.fr> (raw)

Today in the perfevents subsystem it looks like DTLB/ITLB misses are 
implemented as HW counter only.
On some processors, like PowerPC 8xx, there is no counter for that. 
However DTLB/ITLB misses are handled as exceptions via software, so we 
have an opportunity to implement a SW counter for that.
What's the easiest/best way to implement it ?

Christophe

             reply	other threads:[~2013-11-24 18:11 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-11-24 18:10 christophe leroy [this message]
2013-11-27 11:43 ` perf events: how to implement TLB misses as SW event ? Peter Zijlstra

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