[PATCH 0/7] riscv: eswin: eic7700: Add support for clocks, resets, pinctrl, HSP power domain, I2C and watchdog

[PATCH 0/7] riscv: eswin: eic7700: Add support for clocks, resets, pinctrl, HSP power domain, I2C and watchdog

[Pinkesh Vaghela]

This series extends the ESWIN's EIC7700 SoC support beyond the
already upstreamed basic DTS and DTSI files. It introduces DT nodes
for reset, clock, pinctrl, HSP power domain, I2C and Watchdog.

As support for boot media is yet to be upstreamed, we have
boot-tested this series with initramfs on HiFive Premier P550 board
using Linux 7.1, U-Boot 2024.01 and OpenSBI 1.8.1.

[1]: https://lore.kernel.org/lkml/20251113014656.2605447-1-samuel.holland@sifive.com/

Pinkesh Vaghela (2):
  dt-bindings: mfd: syscon: add ESWIN EIC7700 compatible
  riscv: dts: eswin: add hsp power domain

Pritesh Patel (4):
  riscv: dts: eswin: add reset generator for EIC7700 SoC
  riscv: dts: eswin: add clock generator for EIC7700 SoC
  riscv: dts: eswin: add I2C controller support
  riscv: dts: eswin: add watchdog support

Yulin Lu (1):
  riscv: dts: eswin: eic7700: add pinctrl support

 .../devicetree/bindings/mfd/syscon.yaml       |   2 +
 .../dts/eswin/eic7700-hifive-premier-p550.dts | 182 ++++
 .../riscv/boot/dts/eswin/eic7700-pinctrl.dtsi | 888 ++++++++++++++++++
 arch/riscv/boot/dts/eswin/eic7700.dtsi        | 234 +++++
 4 files changed, 1306 insertions(+)
 create mode 100644 arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi

-- 
2.34.1

[PATCH 1/7] riscv: dts: eswin: add reset generator for EIC7700 SoC

[Pinkesh Vaghela]

From: Pritesh Patel <pritesh.patel@einfochips.com>

Add reset generator node for EIC7700 SoC

Signed-off-by: Pritesh Patel <pritesh.patel@einfochips.com>
Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
---
 arch/riscv/boot/dts/eswin/eic7700.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/eswin/eic7700.dtsi
index c3ed93008bca..430a210f01e6 100644
--- a/arch/riscv/boot/dts/eswin/eic7700.dtsi
+++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi
@@ -4,6 +4,7 @@
  */
 
 /dts-v1/;
+#include <dt-bindings/reset/eswin,eic7700-reset.h>
 
 / {
 	#address-cells = <2>;
@@ -341,5 +342,11 @@ gpioD: gpio-port@3 {
 				#gpio-cells = <2>;
 			};
 		};
+
+		reset: reset-controller@51828300 {
+			compatible = "eswin,eic7700-reset";
+			reg = <0x0 0x51828300 0x0 0x200>;
+			#reset-cells = <1>;
+		};
 	};
 };
-- 
2.34.1

[PATCH 2/7] riscv: dts: eswin: add clock generator for EIC7700 SoC

[Pinkesh Vaghela]

From: Pritesh Patel <pritesh.patel@einfochips.com>

Add clock generator node for EIC7700 SoC.
HiFive Premier P550 boards have 24MHz crystal oscillator to provide
the input clock.

Signed-off-by: Pritesh Patel <pritesh.patel@einfochips.com>
Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
---
 .../boot/dts/eswin/eic7700-hifive-premier-p550.dts  |  5 +++++
 arch/riscv/boot/dts/eswin/eic7700.dtsi              | 13 +++++++++++++
 2 files changed, 18 insertions(+)

diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
index 131ed1fc6b2e..1fb92f0e7c55 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
@@ -20,6 +20,11 @@ chosen {
 	};
 };
 
+&xtal {
+	clock-frequency = <24000000>;
+	clock-output-names = "xtal24m";
+};
+
 &uart0 {
 	status = "okay";
 };
diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/eswin/eic7700.dtsi
index 430a210f01e6..a7ebb1115958 100644
--- a/arch/riscv/boot/dts/eswin/eic7700.dtsi
+++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi
@@ -4,6 +4,7 @@
  */
 
 /dts-v1/;
+#include <dt-bindings/clock/eswin,eic7700-clock.h>
 #include <dt-bindings/reset/eswin,eic7700-reset.h>
 
 / {
@@ -203,6 +204,11 @@ pmu {
 				<0x00000000 0x0000000f 0xfffffffc 0x000000ff 0x00000078>;
 	};
 
+	xtal: oscillator {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+	};
+
 	soc {
 		compatible = "simple-bus";
 		ranges;
@@ -343,6 +349,13 @@ gpioD: gpio-port@3 {
 			};
 		};
 
+		clk: clock-controller@51828000 {
+			compatible = "eswin,eic7700-clock";
+			reg = <0x0 0x51828000 0x0 0x300>;
+			clocks = <&xtal>;
+			#clock-cells = <1>;
+		};
+
 		reset: reset-controller@51828300 {
 			compatible = "eswin,eic7700-reset";
 			reg = <0x0 0x51828300 0x0 0x200>;
-- 
2.34.1

[PATCH 3/7] riscv: dts: eswin: eic7700: add pinctrl support

[Pinkesh Vaghela]

From: Yulin Lu <luyulin@eswincomputing.com>

Add pinctrl node and related pin configuration for EIC7700 SoC

Co-developed-by: Pritesh Patel <pritesh.patel@einfochips.com>
Signed-off-by: Pritesh Patel <pritesh.patel@einfochips.com>
Signed-off-by: Yulin Lu <luyulin@eswincomputing.com>
Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
---
 .../dts/eswin/eic7700-hifive-premier-p550.dts | 109 +++
 .../riscv/boot/dts/eswin/eic7700-pinctrl.dtsi | 888 ++++++++++++++++++
 arch/riscv/boot/dts/eswin/eic7700.dtsi        |   5 +
 3 files changed, 1002 insertions(+)
 create mode 100644 arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi

diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
index 1fb92f0e7c55..e7bb96e14958 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
@@ -6,6 +6,7 @@
 /dts-v1/;
 
 #include "eic7700.dtsi"
+#include "eic7700-pinctrl.dtsi"
 
 / {
 	compatible = "sifive,hifive-premier-p550", "eswin,eic7700";
@@ -18,6 +19,15 @@ aliases {
 	chosen {
 		stdout-path = "serial0:115200n8";
 	};
+
+	vcc_1v8: vcc1v8 {
+		 compatible = "regulator-fixed";
+		 regulator-name = "vcc1v8";
+		 regulator-always-on;
+		 regulator-boot-on;
+		 regulator-min-microvolt = <1800000>;
+		 regulator-max-microvolt = <1800000>;
+	 };
 };
 
 &xtal {
@@ -25,6 +35,105 @@ &xtal {
 	clock-output-names = "xtal24m";
 };
 
+&gpio0_pins {
+	bias-disable;
+	input-enable;
+};
+
+&gpio5_pins {
+	bias-disable;
+	input-enable;
+};
+
+&gpio11_pins {
+	bias-disable;
+	input-enable;
+};
+
+&gpio14_pins {
+	bias-pull-up;
+	input-disable;
+};
+
+&gpio15_pins {
+	bias-disable;
+	input-enable;
+};
+
+&gpio28_pins {
+	bias-disable;
+	input-enable;
+};
+
+&gpio43_pins {
+	bias-disable;
+	input-disable;
+};
+
+&gpio71_pins {
+	bias-pull-up;
+	input-disable;
+};
+
+&gpio74_pins {
+	bias-pull-up;
+	input-disable;
+};
+
+&gpio76_pins {
+	bias-disable;
+	input-disable;
+};
+
+&gpio77_pins {
+	bias-pull-up;
+	input-disable;
+};
+
+&gpio79_pins {
+	bias-disable;
+	input-disable;
+};
+
+&gpio80_pins {
+	bias-pull-up;
+	input-disable;
+};
+
+&gpio82_pins {
+	bias-pull-up;
+	input-disable;
+};
+
+&gpio84_pins {
+	bias-disable;
+	input-disable;
+};
+
+&gpio85_pins {
+	bias-pull-up;
+	input-disable;
+};
+
+&gpio94_pins {
+	bias-disable;
+	input-disable;
+};
+
+&gpio106_pins {
+	bias-disable;
+	input-disable;
+};
+
+&gpio111_pins {
+	bias-disable;
+	input-disable;
+};
+
+&pinctrl {
+	vrgmii-supply = <&vcc_1v8>;
+};
+
 &uart0 {
 	status = "okay";
 };
diff --git a/arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi b/arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi
new file mode 100644
index 000000000000..7293df146aa7
--- /dev/null
+++ b/arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi
@@ -0,0 +1,888 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (c) 2025 Beijing ESWIN Computing Technology Co., Ltd.
+ *
+ * ESWIN's EIC7700 SoC pin-mux and pin-config options are listed as
+ * device tree nodes in this file.
+ *
+ * Authors: Yulin Lu <luyulin@eswincomputing.com>
+ */
+
+&pinctrl{
+	default-pins-grp {
+		sata_act_led_pins: sata-act-led-pins{
+			pins = "gpio27";
+			function = "sata";
+		};
+
+		emmc_led_ctrl_pins: emmc-led-ctrl-pins {
+			pins = "gpio29";
+			function = "emmc";
+		};
+
+		sd0_led_ctrl_pins: sd0-led-ctrl-pins {
+			pins = "gpio34";
+			function = "sdio";
+		};
+
+		sd1_led_ctrl_pins: sd1-led-ctrl-pins {
+			pins = "spi1_d2";
+			function = "sdio";
+		};
+
+		i2c6_pins: i2c6-pins {
+			pins = "uart1_cts", "uart1_rts";
+			function = "i2c";
+		};
+
+		i2c7_pins: i2c7-pins {
+			pins = "uart2_tx", "uart2_rx";
+			function = "i2c";
+		};
+
+		i2c9_pins: i2c9-pins {
+			pins = "spi1_d0", "spi1_d1";
+			function = "i2c";
+		};
+
+		pwm1_pins: pwm1-pins {
+			pins = "spi1_d3";
+			function = "pwm";
+		};
+
+		pwm2_pins: pwm2-pins {
+			pins = "spi1_cs1_n";
+			function = "pwm";
+		};
+
+		mipi_csi_xtrig0_pins: mipi-csi-xtrig0-pins {
+			pins = "gpio92";
+			function = "mipi_csi";
+		};
+
+		mipi_csi_xtrig1_pins: mipi-csi-xtrig1-pins {
+			pins = "gpio93";
+			function = "mipi_csi";
+		};
+
+		dual_spi2_pins: dual-spi2-pins {
+			pins = "spi2_cs0_n", "jtag0_tck", "jtag0_tms", "jtag0_tdi";
+			function = "spi";
+		};
+
+		quad_spi2_pins: quad-spi2-pins {
+			pins = "spi2_cs0_n", "spi2_cs1_n", "jtag0_tck", "jtag0_tms",
+			       "jtag0_tdi", "jtag0_tdo", "gpio5";
+			function = "spi";
+		};
+
+		gpio1_pins: gpio1-pins {
+			pins = "jtag0_tck";
+			function = "gpio";
+		};
+
+		gpio2_pins: gpio2-pins {
+			pins = "jtag0_tms";
+			function = "gpio";
+		};
+
+		gpio3_pins: gpio3-pins {
+			pins = "jtag0_tdi";
+			function = "gpio";
+		};
+
+		gpio4_pins: gpio4-pins {
+			pins = "jtag0_tdo";
+			function = "gpio";
+		};
+
+		gpio6_pins: gpio6-pins {
+			pins = "spi2_cs0_n";
+			function = "gpio";
+		};
+
+		gpio7_pins: gpio7-pins {
+			pins = "jtag1_tck";
+			function = "gpio";
+		};
+
+		gpio8_pins: gpio8-pins {
+			pins = "jtag1_tms";
+			function = "gpio";
+		};
+
+		gpio9_pins: gpio9-pins {
+			pins = "jtag1_tdi";
+			function = "gpio";
+		};
+
+		gpio10_pins: gpio10-pins {
+			pins = "jtag1_tdo";
+			function = "gpio";
+		};
+
+		gpio12_pins: gpio12-pins {
+			pins = "spi2_cs1_n";
+			function = "gpio";
+		};
+
+		gpio13_pins: gpio13-pins {
+			pins = "mode_set0";
+			function = "gpio";
+		};
+
+		gpio14_pins: gpio14-pins {
+			pins = "mode_set1";
+			function = "gpio";
+		};
+
+		gpio15_pins: gpio15-pins {
+			pins = "mode_set2";
+			function = "gpio";
+		};
+
+		gpio16_pins: gpio16-pins {
+			pins = "mode_set3";
+			function = "gpio";
+		};
+
+		gpio17_pins: gpio17-pins {
+			pins = "jtag2_trst";
+			function = "gpio";
+		};
+
+		gpio18_pins: gpio18-pins {
+			pins = "i2s0_bclk";
+			function = "gpio";
+		};
+
+		gpio19_pins: gpio19-pins {
+			pins = "i2s0_wclk";
+			function = "gpio";
+		};
+
+		gpio20_pins: gpio20-pins {
+			pins = "i2s0_sdi";
+			function = "gpio";
+		};
+
+		gpio21_pins: gpio21-pins {
+			pins = "i2s0_sdo";
+			function = "gpio";
+		};
+
+		gpio22_pins: gpio22-pins {
+			pins = "i2s_mclk";
+			function = "gpio";
+		};
+
+		gpio23_pins: gpio23-pins {
+			pins = "i2s2_bclk";
+			function = "gpio";
+		};
+
+		gpio24_pins: gpio24-pins {
+			pins = "i2s2_wclk";
+			function = "gpio";
+		};
+
+		gpio25_pins: gpio25-pins {
+			pins = "i2s2_sdi";
+			function = "gpio";
+		};
+
+		gpio26_pins: gpio26-pins {
+			pins = "i2s2_sdo";
+			function = "gpio";
+		};
+
+		gpio29_pins: gpio29-pins {
+			pins = "gpio29";
+			function = "gpio";
+		};
+
+		gpio30_pins: gpio30-pins {
+			pins = "i2s1_bclk";
+			function = "gpio";
+		};
+
+		gpio31_pins: gpio31-pins {
+			pins = "i2s1_wclk";
+			function = "gpio";
+		};
+
+		gpio32_pins: gpio32-pins {
+			pins = "i2s1_sdi";
+			function = "gpio";
+		};
+
+		gpio33_pins: gpio33-pins {
+			pins = "i2s1_sdo";
+			function = "gpio";
+		};
+
+		gpio34_pins: gpio34-pins {
+			pins = "gpio34";
+			function = "gpio";
+		};
+
+		gpio35_pins: gpio35-pins {
+			pins = "spi1_cs0_n";
+			function = "gpio";
+		};
+
+		gpio36_pins: gpio36-pins {
+			pins = "spi1_clk";
+			function = "gpio";
+		};
+
+		gpio37_pins: gpio37-pins {
+			pins = "spi1_d0";
+			function = "gpio";
+		};
+
+		gpio38_pins: gpio38-pins {
+			pins = "spi1_d1";
+			function = "gpio";
+		};
+
+		gpio39_pins: gpio39-pins {
+			pins = "spi1_d2";
+			function = "gpio";
+		};
+
+		gpio40_pins: gpio40-pins {
+			pins = "spi1_d3";
+			function = "gpio";
+		};
+
+		gpio41_pins: gpio41-pins {
+			pins = "spi1_cs1_n";
+			function = "gpio";
+		};
+
+		gpio42_pins: gpio42-pins {
+			pins = "usb0_pwren";
+			function = "gpio";
+		};
+
+		gpio43_pins: gpio43-pins {
+			pins = "usb1_pwren";
+			function = "gpio";
+		};
+
+		gpio44_pins: gpio44-pins {
+			pins = "i2c0_scl";
+			function = "gpio";
+		};
+
+		gpio45_pins: gpio45-pins {
+			pins = "i2c0_sda";
+			function = "gpio";
+		};
+
+		gpio46_pins: gpio46-pins {
+			pins = "i2c1_scl";
+			function = "gpio";
+		};
+
+		gpio47_pins: gpio47-pins {
+			pins = "i2c1_sda";
+			function = "gpio";
+		};
+
+		gpio48_pins: gpio48-pins {
+			pins = "i2c2_scl";
+			function = "gpio";
+		};
+
+		gpio49_pins: gpio49-pins {
+			pins = "i2c2_sda";
+			function = "gpio";
+		};
+
+		gpio50_pins: gpio50-pins {
+			pins = "i2c3_scl";
+			function = "gpio";
+		};
+
+		gpio51_pins: gpio51-pins {
+			pins = "i2c3_sda";
+			function = "gpio";
+		};
+
+		gpio52_pins: gpio52-pins {
+			pins = "i2c4_scl";
+			function = "gpio";
+		};
+
+		gpio53_pins: gpio53-pins {
+			pins = "i2c4_sda";
+			function = "gpio";
+		};
+
+		gpio54_pins: gpio54-pins {
+			pins = "i2c5_scl";
+			function = "gpio";
+		};
+
+		gpio55_pins: gpio55-pins {
+			pins = "i2c5_sda";
+			function = "gpio";
+		};
+
+		gpio56_pins: gpio56-pins {
+			pins = "uart0_tx";
+			function = "gpio";
+		};
+
+		gpio57_pins: gpio57-pins {
+			pins = "uart0_rx";
+			function = "gpio";
+		};
+
+		gpio58_pins: gpio58-pins {
+			pins = "uart1_tx";
+			function = "gpio";
+		};
+
+		gpio59_pins: gpio59-pins {
+			pins = "uart1_rx";
+			function = "gpio";
+		};
+
+		gpio60_pins: gpio60-pins {
+			pins = "uart1_cts";
+			function = "gpio";
+		};
+
+		gpio61_pins: gpio61-pins {
+			pins = "uart1_rts";
+			function = "gpio";
+		};
+
+		gpio62_pins: gpio62-pins {
+			pins = "uart2_tx";
+			function = "gpio";
+		};
+
+		gpio63_pins: gpio63-pins {
+			pins = "uart2_rx";
+			function = "gpio";
+		};
+
+		gpio64_pins: gpio64-pins {
+			pins = "jtag2_tck";
+			function = "gpio";
+		};
+
+		gpio65_pins: gpio65-pins {
+			pins = "jtag2_tms";
+			function = "gpio";
+		};
+
+		gpio66_pins: gpio66-pins {
+			pins = "jtag2_tdi";
+			function = "gpio";
+		};
+
+		gpio67_pins: gpio67-pins {
+			pins = "jtag2_tdo";
+			function = "gpio";
+		};
+
+		gpio68_pins: gpio68-pins {
+			pins = "fan_pwm";
+			function = "gpio";
+		};
+
+		gpio69_pins: gpio69-pins {
+			pins = "fan_tach";
+			function = "gpio";
+		};
+
+		gpio70_pins: gpio70-pins {
+			pins = "mipi_csi0_xvs";
+			function = "gpio";
+		};
+
+		gpio71_pins: gpio71-pins {
+			pins = "mipi_csi0_xhs";
+			function = "gpio";
+		};
+
+		gpio72_pins: gpio72-pins {
+			pins = "mipi_csi0_mclk";
+			function = "gpio";
+		};
+
+		gpio73_pins: gpio73-pins {
+			pins = "mipi_csi1_xvs";
+			function = "gpio";
+		};
+
+		gpio74_pins: gpio74-pins {
+			pins = "mipi_csi1_xhs";
+			function = "gpio";
+		};
+
+		gpio75_pins: gpio75-pins {
+			pins = "mipi_csi1_mclk";
+			function = "gpio";
+		};
+
+		gpio76_pins: gpio76-pins {
+			pins = "mipi_csi2_xvs";
+			function = "gpio";
+		};
+
+		gpio77_pins: gpio77-pins {
+			pins = "mipi_csi2_xhs";
+			function = "gpio";
+		};
+
+		gpio78_pins: gpio78-pins {
+			pins = "mipi_csi2_mclk";
+			function = "gpio";
+		};
+
+		gpio79_pins: gpio79-pins {
+			pins = "mipi_csi3_xvs";
+			function = "gpio";
+		};
+
+		gpio80_pins: gpio80-pins {
+			pins = "mipi_csi3_xhs";
+			function = "gpio";
+		};
+
+		gpio81_pins: gpio81-pins {
+			pins = "mipi_csi3_mclk";
+			function = "gpio";
+		};
+
+		gpio82_pins: gpio82-pins {
+			pins = "mipi_csi4_xvs";
+			function = "gpio";
+		};
+
+		gpio83_pins: gpio83-pins {
+			pins = "mipi_csi4_xhs";
+			function = "gpio";
+		};
+
+		gpio84_pins: gpio84-pins {
+			pins = "mipi_csi4_mclk";
+			function = "gpio";
+		};
+
+		gpio85_pins: gpio85-pins {
+			pins = "mipi_csi5_xvs";
+			function = "gpio";
+		};
+
+		gpio86_pins: gpio86-pins {
+			pins = "mipi_csi5_xhs";
+			function = "gpio";
+		};
+
+		gpio87_pins: gpio87-pins {
+			pins = "mipi_csi5_mclk";
+			function = "gpio";
+		};
+
+		gpio88_pins: gpio88-pins {
+			pins = "spi3_cs_n";
+			function = "gpio";
+		};
+
+		gpio89_pins: gpio89-pins {
+			pins = "spi3_clk";
+			function = "gpio";
+		};
+
+		gpio90_pins: gpio90-pins {
+			pins = "spi3_di";
+			function = "gpio";
+		};
+
+		gpio91_pins: gpio91-pins {
+			pins = "spi3_do";
+			function = "gpio";
+		};
+
+		gpio92_pins: gpio92-pins {
+			pins = "gpio92";
+			function = "gpio";
+		};
+
+		gpio93_pins: gpio93-pins {
+			pins = "gpio93";
+			function = "gpio";
+		};
+
+		gpio94_pins: gpio94-pins {
+			pins = "s_mode";
+			function = "gpio";
+		};
+
+		gpio95_pins: gpio95-pins {
+			pins = "gpio95";
+			function = "gpio";
+		};
+
+		gpio96_pins: gpio96-pins {
+			pins = "spi0_cs_n";
+			function = "gpio";
+		};
+
+		gpio97_pins: gpio97-pins {
+			pins = "spi0_clk";
+			function = "gpio";
+		};
+
+		gpio98_pins: gpio98-pins {
+			pins = "spi0_d0";
+			function = "gpio";
+		};
+
+		gpio99_pins: gpio99-pins {
+			pins = "spi0_d1";
+			function = "gpio";
+		};
+
+		gpio100_pins: gpio100-pins {
+			pins = "spi0_d2";
+			function = "gpio";
+		};
+
+		gpio101_pins: gpio101-pins {
+			pins = "spi0_d3";
+			function = "gpio";
+		};
+
+		gpio102_pins: gpio102-pins {
+			pins = "i2c10_scl";
+			function = "gpio";
+		};
+
+		gpio103_pins: gpio103-pins {
+			pins = "i2c10_sda";
+			function = "gpio";
+		};
+
+		gpio104_pins: gpio104-pins {
+			pins = "i2c11_scl";
+			function = "gpio";
+		};
+
+		gpio105_pins: gpio105-pins {
+			pins = "i2c11_sda";
+			function = "gpio";
+		};
+
+		gpio107_pins: gpio107-pins {
+			pins = "boot_sel0";
+			function = "gpio";
+		};
+
+		gpio108_pins: gpio108-pins {
+			pins = "boot_sel1";
+			function = "gpio";
+		};
+
+		gpio109_pins: gpio109-pins {
+			pins = "boot_sel2";
+			function = "gpio";
+		};
+
+		gpio110_pins: gpio110-pins {
+			pins = "boot_sel3";
+			function = "gpio";
+		};
+
+		uart3_pins: uart3-pins {
+			pins = "gpio92", "gpio93";
+			function = "uart";
+		};
+
+		uart4_pins: uart4-pins {
+			pins = "spi1_d0", "spi1_d1";
+			function = "uart";
+		};
+
+		gpio0_pins: gpio0-pins {
+			pins = "gpio0";
+			function = "gpio";
+		};
+
+		gpio5_pins: gpio5-pins {
+			pins = "gpio5";
+			function = "gpio";
+		};
+
+		gpio11_pins: gpio11-pins {
+			pins = "gpio11";
+			function = "gpio";
+		};
+
+		gpio27_pins: gpio27-pins {
+			pins = "gpio27";
+			function = "gpio";
+		};
+
+		gpio28_pins: gpio28-pins {
+			pins = "gpio28";
+			function = "gpio";
+		};
+
+		gpio106_pins: gpio106-pins {
+			pins = "gpio106";
+			function = "gpio";
+		};
+
+		gpio111_pins: gpio111-pins {
+			pins = "gpio111";
+			function = "gpio";
+		};
+
+		chip_mode_pins: chip-mode-pins {
+			pins = "chip_mode";
+			function = "chip_mode";
+		};
+
+		sdio0_pins: sdio0-pins {
+			pins = "mode_set0", "mode_set1";
+			function = "sdio";
+		};
+
+		sdio1_pins: sdio1-pins {
+			pins = "mode_set2", "mode_set3";
+			function = "sdio";
+		};
+
+		jtag0_pins: jtag0-pins {
+			pins = "jtag0_tck", "jtag0_tms", "jtag0_tdi", "jtag0_tdo";
+			function = "jtag";
+		};
+
+		jtag1_pins: jtag1-pins {
+			pins = "jtag1_tck", "jtag1_tms", "jtag1_tdi", "jtag1_tdo";
+			function = "jtag";
+		};
+
+		jtag2_pins: jtag2-pins {
+			pins = "jtag2_trst", "jtag2_tck", "jtag2_tms", "jtag2_tdi",
+			       "jtag2_tdo";
+			function = "jtag";
+		};
+
+		pcie_pins: pcie-pins {
+			pins = "pcie_clkreq_n", "pcie_wake_n", "pcie_perst_n";
+			function = "pcie";
+		};
+
+		hdmi_pins: hdmi-pins {
+			pins = "hdmi_scl", "hdmi_sda", "hdmi_cec";
+			function = "hdmi";
+		};
+
+		rgmii0_pins: rgmii0-pins {
+			pins = "rgmii0_clk_125", "rgmii0_txen", "rgmii0_txclk", "rgmii0_txd0",
+			       "rgmii0_txd1", "rgmii0_txd2", "rgmii0_txd3", "rgmii0_rxclk",
+			       "rgmii0_rxdv", "rgmii0_rxd0", "rgmii0_rxd1", "rgmii0_rxd2",
+			       "rgmii0_rxd3", "rgmii0_mdc", "rgmii0_mdio", "rgmii0_intb";
+			function = "hdmi";
+		};
+
+		rgmii1_pins: rgmii1-pins {
+			pins = "rgmii1_clk_125", "rgmii1_txen", "rgmii1_txclk", "rgmii1_txd0",
+			       "rgmii1_txd1", "rgmii1_txd2", "rgmii1_txd3", "rgmii1_rxclk",
+			       "rgmii1_rxdv", "rgmii1_rxd0", "rgmii1_rxd1", "rgmii1_rxd2",
+			       "rgmii1_rxd3", "rgmii1_mdc", "rgmii1_mdio", "rgmii1_intb";
+			function = "hdmi";
+		};
+
+		i2s0_pins: i2s0-pins {
+			pins = "i2s0_bclk", "i2s0_wclk", "i2s0_sdi", "i2s0_sdo", "i2s_mclk";
+			function = "hdmi";
+		};
+
+		i2s1_pins: i2s1-pins {
+			pins = "i2s1_bclk", "i2s1_wclk", "i2s1_sdi", "i2s1_sdo", "i2s_mclk";
+			function = "hdmi";
+		};
+
+		i2s2_pins: i2s2-pins {
+			pins = "i2s2_bclk", "i2s2_wclk", "i2s2_sdi", "i2s2_sdo", "i2s_mclk";
+			function = "hdmi";
+		};
+
+		usb0_pwren_pins: usb0-pwren-pins {
+			pins = "usb0_pwren";
+			function = "usb";
+		};
+
+		usb1_pwren_pins: usb1-pwren-pins {
+			pins = "usb1_pwren";
+			function = "usb";
+		};
+
+		i2c0_pins: i2c0-pins {
+			pins = "i2c0_scl", "i2c0_sda";
+			function = "i2c";
+		};
+
+		i2c1_pins: i2c1-pins {
+			pins = "i2c1_scl", "i2c1_sda";
+			function = "i2c";
+		};
+
+		i2c2_pins: i2c2-pins {
+			pins = "i2c2_scl", "i2c2_sda";
+			function = "i2c";
+		};
+
+		i2c3_pins: i2c3-pins {
+			pins = "i2c3_scl", "i2c3_sda";
+			function = "i2c";
+		};
+
+		i2c4_pins: i2c4-pins {
+			pins = "i2c4_scl", "i2c4_sda";
+			function = "i2c";
+		};
+
+		i2c5_pins: i2c5-pins {
+			pins = "i2c5_scl", "i2c5_sda";
+			function = "i2c";
+		};
+
+		i2c8_pins: i2c8-pins {
+			pins = "gpio92", "gpio93";
+			function = "i2c";
+		};
+
+		i2c10_pins: i2c10-pins {
+			pins = "i2c10_scl", "i2c10_sda";
+			function = "i2c";
+		};
+
+		i2c11_pins: i2c11-pins {
+			pins = "i2c11_scl", "i2c11_sda";
+			function = "i2c";
+		};
+
+		uart0_pins: uart0-pins {
+			pins = "uart0_tx", "uart0_rx";
+			function = "uart";
+		};
+
+		uart1_pins: uart1-pins {
+			pins = "uart1_tx", "uart1_rx", "uart1_cts", "uart1_rts";
+			function = "uart";
+		};
+
+		uart2_pins: uart2-pins {
+			pins = "uart2_tx", "uart2_rx";
+			function = "uart";
+		};
+
+		fan_pwm_pins: fan-pwm-pins {
+			pins = "fan_pwm";
+			function = "pwm";
+		};
+
+		fan_tach_pins: fan-tach-pins {
+			pins = "fan_tach";
+			function = "fan_tach";
+		};
+
+		mipi_csi0_pins: mipi-csi0-pins {
+			pins = "mipi_csi0_xvs", "mipi_csi0_xhs", "mipi_csi0_mclk";
+			function = "mipi_csi";
+		};
+
+		mipi_csi1_pins: mipi-csi1-pins {
+			pins = "mipi_csi1_xvs", "mipi_csi1_xhs", "mipi_csi1_mclk";
+			function = "mipi_csi";
+		};
+
+		mipi_csi2_pins: mipi-csi2-pins {
+			pins = "mipi_csi2_xvs", "mipi_csi2_xhs", "mipi_csi2_mclk";
+			function = "mipi_csi";
+		};
+
+		mipi_csi3_pins: mipi-csi3-pins {
+			pins = "mipi_csi3_xvs", "mipi_csi3_xhs", "mipi_csi3_mclk";
+			function = "mipi_csi";
+		};
+
+		mipi_csi4_pins: mipi-csi4-pins {
+			pins = "mipi_csi4_xvs", "mipi_csi4_xhs", "mipi_csi4_mclk";
+			function = "mipi_csi";
+		};
+
+		mipi_csi5_pins: mipi-csi5-pins {
+			pins = "mipi_csi5_xvs", "mipi_csi5_xhs", "mipi_csi5_mclk";
+			function = "mipi_csi";
+		};
+
+		s_mode_pins: s-mode-pins {
+			pins = "s_mode";
+			function = "s_mode";
+		};
+
+		boot_sel0_pins: boot-sel0-pins {
+			pins = "boot_sel0";
+			function = "boot_sel";
+		};
+
+		boot_sel1_pins: boot-sel1-pins {
+			pins = "boot_sel1";
+			function = "boot_sel";
+		};
+
+		boot_sel2_pins: boot-sel2-pins {
+			pins = "boot_sel2";
+			function = "boot_sel";
+		};
+
+		boot_sel3_pins: boot-sel3-pins {
+			pins = "boot_sel3";
+			function = "boot_sel";
+		};
+
+		ddr_ref_clk_sel_pins: ddr-ref-clk-sel-pins {
+			pins = "gpio95";
+			function = "ddr_ref_clk_sel";
+		};
+
+		lpddr_ref_clk_pins: lpddr-ref-clk-pins {
+			pins = "lpddr_ref_clk";
+			function = "lpddr_ref_clk";
+		};
+
+		spi0_pins: spi0-pins {
+			pins = "spi0_cs_n", "spi0_clk", "spi0_d0", "spi0_d1", "spi0_d2",
+			       "spi0_d3";
+			function = "spi";
+		};
+
+		dual_spi1_pins: dual-spi1-pins {
+			pins = "spi1_cs0_n", "spi1_clk", "spi1_d0", "spi1_d1";
+			function = "spi";
+		};
+
+		quad_spi1_pins: quad-spi1-pins {
+			pins = "spi1_cs0_n", "spi1_cs1_n", "spi1_clk", "spi1_d0", "spi1_d1",
+			       "spi1_d2", "spi1_d3";
+			function = "spi";
+		};
+
+		spi3_pins: spi3-pins {
+			pins = "spi3_cs_n", "spi3_clk", "spi3_di", "spi3_do";
+			function = "spi";
+		};
+	};
+};
diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/eswin/eic7700.dtsi
index a7ebb1115958..8798c50f7584 100644
--- a/arch/riscv/boot/dts/eswin/eic7700.dtsi
+++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi
@@ -349,6 +349,11 @@ gpioD: gpio-port@3 {
 			};
 		};
 
+		pinctrl: pinctrl@51600080 {
+			compatible = "eswin,eic7700-pinctrl";
+			reg = <0x0 0x51600080 0x0 0x1fff80>;
+		};
+
 		clk: clock-controller@51828000 {
 			compatible = "eswin,eic7700-clock";
 			reg = <0x0 0x51828000 0x0 0x300>;
-- 
2.34.1

[PATCH 4/7] dt-bindings: mfd: syscon: add ESWIN EIC7700 compatible

[Pinkesh Vaghela]

Document ESWIN EIC7700 SoC compatible for syscon registers.

Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
---
 Documentation/devicetree/bindings/mfd/syscon.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml
index e22867088063..7d3365601249 100644
--- a/Documentation/devicetree/bindings/mfd/syscon.yaml
+++ b/Documentation/devicetree/bindings/mfd/syscon.yaml
@@ -62,6 +62,7 @@ select:
           - cirrus,ep7209-syscon3
           - cnxt,cx92755-uc
           - econet,en751221-chip-scu
+          - eswin,eic7700-syscfg
           - freecom,fsg-cs2-system-controller
           - fsl,imx93-aonmix-ns-syscfg
           - fsl,imx93-wakeupmix-syscfg
@@ -175,6 +176,7 @@ properties:
               - cirrus,ep7209-syscon3
               - cnxt,cx92755-uc
               - econet,en751221-chip-scu
+              - eswin,eic7700-syscfg
               - freecom,fsg-cs2-system-controller
               - fsl,imx93-aonmix-ns-syscfg
               - fsl,imx93-wakeupmix-syscfg
-- 
2.34.1

[PATCH 5/7] riscv: dts: eswin: add hsp power domain

[Pinkesh Vaghela]

HSP CSR is inside the HSP power domain. HSP CFG clock must be enabled
to access the HSP CSR registers.
Add HSP power domain node to manage hsp cfg clock

Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
---
 arch/riscv/boot/dts/eswin/eic7700.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/eswin/eic7700.dtsi
index 8798c50f7584..f8caf39616b2 100644
--- a/arch/riscv/boot/dts/eswin/eic7700.dtsi
+++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi
@@ -252,6 +252,19 @@ plic: interrupt-controller@c000000 {
 			#interrupt-cells = <1>;
 		};
 
+		hsp_power_domain: bus@50400000 {
+			compatible = "simple-pm-bus";
+			ranges = <0x0 0x50400000 0x0 0x50400000 0x0 0xa0000>;
+			clocks = <&clk EIC7700_CLK_GATE_HSP_CFG_CLK>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+
+			hsp_sp_csr: hsp-sp-top-csr@50440000 {
+				compatible = "eswin,eic7700-syscfg", "syscon";
+				reg = <0x0 0x50440000 0x0 0x2000>;
+			};
+		};
+
 		uart0: serial@50900000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x0 0x50900000 0x0 0x10000>;
-- 
2.34.1

[PATCH 6/7] riscv: dts: eswin: add I2C controller support

[Pinkesh Vaghela]

From: Pritesh Patel <pritesh.patel@einfochips.com>

Add I2C nodes for EIC7700 SoC.
Also add nodes for corresponding slave devices in dts file and
enable them for HiFive Premier P550 board

Signed-off-by: Pritesh Patel <pritesh.patel@einfochips.com>
Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
---
 .../dts/eswin/eic7700-hifive-premier-p550.dts |  52 ++++++
 arch/riscv/boot/dts/eswin/eic7700.dtsi        | 156 ++++++++++++++++++
 2 files changed, 208 insertions(+)

diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
index e7bb96e14958..0f0c98474c62 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
@@ -130,6 +130,58 @@ &gpio111_pins {
 	input-disable;
 };
 
+&aon_i2c0 {
+	status = "okay";
+
+	eeprom@50 {
+		compatible = "atmel,24c02";
+		reg = <0x50>;
+	};
+};
+
+&aon_i2c1 {
+	status = "okay";
+
+	pac1934@10 {
+		compatible = "microchip,pac1934";
+		reg = <0x10>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		channel@1 {
+			reg = <0x1>;
+			shunt-resistor-micro-ohms = <1000>;
+			label = "VDD_SOM";
+		};
+
+		channel@2 {
+			reg = <0x2>;
+			shunt-resistor-micro-ohms = <1000>;
+			label = "VDD_SOC";
+		};
+
+		channel@3 {
+			reg = <0x3>;
+			shunt-resistor-micro-ohms = <1000>;
+			label = "VDD_CPU";
+		};
+
+		channel@4 {
+			reg = <0x4>;
+			shunt-resistor-micro-ohms = <1000>;
+			label = "VDD_LPDDR";
+		};
+	};
+
+	ina226@44 {
+		compatible = "ti,ina226";
+		reg = <0x44>;
+		#io-channel-cells = <1>;
+		label = "sys_power";
+		shunt-resistor = <1000>;
+	};
+};
+
 &pinctrl {
 	vrgmii-supply = <&vcc_1v8>;
 };
diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/eswin/eic7700.dtsi
index f8caf39616b2..28706431b2c0 100644
--- a/arch/riscv/boot/dts/eswin/eic7700.dtsi
+++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi
@@ -315,6 +315,162 @@ uart4: serial@50940000 {
 			status = "disabled";
 		};
 
+		i2c0: i2c@50950000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x0 0x50950000 0x0 0x8000>;
+			interrupts = <105>;
+			clocks = <&clk EIC7700_CLK_GATE_LSP_I2C0_PCLK>;
+			clock-names = "ref";
+			clock-frequency = <100000>;
+			resets = <&reset EIC7700_RESET_I2C0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c1: i2c@50960000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x0 0x50960000 0x0 0x8000>;
+			interrupts = <106>;
+			clocks = <&clk EIC7700_CLK_GATE_LSP_I2C1_PCLK>;
+			clock-names = "ref";
+			clock-frequency = <100000>;
+			resets = <&reset EIC7700_RESET_I2C1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c2: i2c@50970000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x0 0x50970000 0x0 0x8000>;
+			interrupts = <107>;
+			clocks = <&clk EIC7700_CLK_GATE_LSP_I2C2_PCLK>;
+			clock-names = "ref";
+			clock-frequency = <100000>;
+			resets = <&reset EIC7700_RESET_I2C2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c3: i2c@50980000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x0 0x50980000 0x0 0x8000>;
+			interrupts = <108>;
+			clocks = <&clk EIC7700_CLK_GATE_LSP_I2C3_PCLK>;
+			clock-names = "ref";
+			clock-frequency = <100000>;
+			resets = <&reset EIC7700_RESET_I2C3>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c4: i2c@50990000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x0 0x50990000 0x0 0x8000>;
+			interrupts = <109>;
+			clocks = <&clk EIC7700_CLK_GATE_LSP_I2C4_PCLK>;
+			clock-names = "ref";
+			clock-frequency = <100000>;
+			resets = <&reset EIC7700_RESET_I2C4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c5: i2c@509a0000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x0 0x509a0000 0x0 0x8000>;
+			interrupts = <110>;
+			clocks = <&clk EIC7700_CLK_GATE_LSP_I2C5_PCLK>;
+			clock-names = "ref";
+			clock-frequency = <100000>;
+			resets = <&reset EIC7700_RESET_I2C5>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c6: i2c@509b0000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x0 0x509b0000 0x0 0x8000>;
+			interrupts = <111>;
+			clocks = <&clk EIC7700_CLK_GATE_LSP_I2C6_PCLK>;
+			clock-names = "ref";
+			clock-frequency = <100000>;
+			resets = <&reset EIC7700_RESET_I2C6>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c7: i2c@509c0000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x0 0x509c0000 0x0 0x8000>;
+			interrupts = <112>;
+			clocks = <&clk EIC7700_CLK_GATE_LSP_I2C7_PCLK>;
+			clock-names = "ref";
+			clock-frequency = <100000>;
+			resets = <&reset EIC7700_RESET_I2C7>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c8: i2c@509d0000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x0 0x509d0000 0x0 0x8000>;
+			interrupts = <113>;
+			clocks = <&clk EIC7700_CLK_GATE_LSP_I2C8_PCLK>;
+			clock-names = "ref";
+			clock-frequency = <100000>;
+			resets = <&reset EIC7700_RESET_I2C8>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c9: i2c@509e0000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x0 0x509e0000 0x0 0x8000>;
+			interrupts = <114>;
+			clocks = <&clk EIC7700_CLK_GATE_LSP_I2C9_PCLK>;
+			clock-names = "ref";
+			clock-frequency = <100000>;
+			resets = <&reset EIC7700_RESET_I2C9>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		aon_i2c0: i2c@51830000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x0 0x51830000 0x0 0x8000>;
+			interrupts = <290>;
+			clocks = <&clk EIC7700_CLK_GATE_AON_I2C0_PCLK>;
+			clock-names = "ref";
+			clock-frequency = <100000>;
+			resets = <&reset EIC7700_RESET_ANO0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		aon_i2c1: i2c@51838000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x0 0x51838000 0x0 0x8000>;
+			interrupts = <291>;
+			clocks = <&clk EIC7700_CLK_GATE_AON_I2C1_PCLK>;
+			clock-names = "ref";
+			clock-frequency = <100000>;
+			resets = <&reset EIC7700_RESET_ANO1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		gpio@51600000 {
 			compatible = "snps,dw-apb-gpio";
 			reg = <0x0 0x51600000 0x0 0x80>;
-- 
2.34.1

[PATCH 7/7] riscv: dts: eswin: add watchdog support

[Pinkesh Vaghela]

From: Pritesh Patel <pritesh.patel@einfochips.com>

Add watchdog node for ESWIN EIC7700 SoC and enable them for HiFive
Premier P550 board

Signed-off-by: Pritesh Patel <pritesh.patel@einfochips.com>
Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
---
 .../dts/eswin/eic7700-hifive-premier-p550.dts | 16 ++++++++
 arch/riscv/boot/dts/eswin/eic7700.dtsi        | 40 +++++++++++++++++++
 2 files changed, 56 insertions(+)

diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
index 0f0c98474c62..a188a5e1d526 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
@@ -193,3 +193,19 @@ &uart0 {
 &uart2 {
 	status = "okay";
 };
+
+&wdt0 {
+	status = "okay";
+};
+
+&wdt1 {
+	status = "okay";
+};
+
+&wdt2 {
+	status = "okay";
+};
+
+&wdt3 {
+	status = "okay";
+};
diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/eswin/eic7700.dtsi
index 28706431b2c0..a59a9932be0b 100644
--- a/arch/riscv/boot/dts/eswin/eic7700.dtsi
+++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi
@@ -265,6 +265,46 @@ hsp_sp_csr: hsp-sp-top-csr@50440000 {
 			};
 		};
 
+		wdt0: watchdog@50800000 {
+			compatible = "snps,dw-wdt";
+			reg = <0x0 0x50800000 0x0 0x4000>;
+			interrupts = <87>;
+			clocks =<&clk EIC7700_CLK_GATE_LSP_WDT0_PCLK>;
+			clock-names = "tclk";
+			resets = <&reset EIC7700_RESET_WDT0>;
+			status = "disabled";
+		};
+
+		wdt1: watchdog@50804000 {
+			compatible = "snps,dw-wdt";
+			reg = <0x0 0x50804000 0x0 0x4000>;
+			interrupts = <88>;
+			clocks =<&clk EIC7700_CLK_GATE_LSP_WDT1_PCLK>;
+			clock-names = "tclk";
+			resets = <&reset EIC7700_RESET_WDT1>;
+			status = "disabled";
+		};
+
+		wdt2: watchdog@50808000 {
+			compatible = "snps,dw-wdt";
+			reg = <0x0 0x50808000 0x0 0x4000>;
+			interrupts = <89>;
+			clocks =<&clk EIC7700_CLK_GATE_LSP_WDT2_PCLK>;
+			clock-names = "tclk";
+			resets = <&reset EIC7700_RESET_WDT2>;
+			status = "disabled";
+		};
+
+		wdt3: watchdog@5080c000 {
+			compatible = "snps,dw-wdt";
+			reg = <0x0 0x5080c000 0x0 0x4000>;
+			interrupts = <90>;
+			clocks =<&clk EIC7700_CLK_GATE_LSP_WDT3_PCLK>;
+			clock-names = "tclk";
+			resets = <&reset EIC7700_RESET_WDT3>;
+			status = "disabled";
+		};
+
 		uart0: serial@50900000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x0 0x50900000 0x0 0x10000>;
-- 
2.34.1

Re: [PATCH 4/7] dt-bindings: mfd: syscon: add ESWIN EIC7700 compatible

[Conor Dooley]

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On Mon, Jun 15, 2026 at 05:50:13PM +0530, Pinkesh Vaghela wrote:
> Document ESWIN EIC7700 SoC compatible for syscon registers.

Some detail about what this syscon does would be nice.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable

> 
> Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
> ---
>  Documentation/devicetree/bindings/mfd/syscon.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml
> index e22867088063..7d3365601249 100644
> --- a/Documentation/devicetree/bindings/mfd/syscon.yaml
> +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml
> @@ -62,6 +62,7 @@ select:
>            - cirrus,ep7209-syscon3
>            - cnxt,cx92755-uc
>            - econet,en751221-chip-scu
> +          - eswin,eic7700-syscfg
>            - freecom,fsg-cs2-system-controller
>            - fsl,imx93-aonmix-ns-syscfg
>            - fsl,imx93-wakeupmix-syscfg
> @@ -175,6 +176,7 @@ properties:
>                - cirrus,ep7209-syscon3
>                - cnxt,cx92755-uc
>                - econet,en751221-chip-scu
> +              - eswin,eic7700-syscfg
>                - freecom,fsg-cs2-system-controller
>                - fsl,imx93-aonmix-ns-syscfg
>                - fsl,imx93-wakeupmix-syscfg
> -- 
> 2.34.1
> 

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Re: [PATCH 2/7] riscv: dts: eswin: add clock generator for EIC7700 SoC

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 2251 bytes --]

On Mon, Jun 15, 2026 at 05:50:11PM +0530, Pinkesh Vaghela wrote:
> From: Pritesh Patel <pritesh.patel@einfochips.com>
> 
> Add clock generator node for EIC7700 SoC.
> HiFive Premier P550 boards have 24MHz crystal oscillator to provide
> the input clock.
> 
> Signed-off-by: Pritesh Patel <pritesh.patel@einfochips.com>
> Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
> ---
>  .../boot/dts/eswin/eic7700-hifive-premier-p550.dts  |  5 +++++
>  arch/riscv/boot/dts/eswin/eic7700.dtsi              | 13 +++++++++++++
>  2 files changed, 18 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> index 131ed1fc6b2e..1fb92f0e7c55 100644
> --- a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> +++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> @@ -20,6 +20,11 @@ chosen {
>  	};
>  };
>  
> +&xtal {
> +	clock-frequency = <24000000>;
> +	clock-output-names = "xtal24m";
> +};
> +
>  &uart0 {
>  	status = "okay";
>  };
> diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/eswin/eic7700.dtsi
> index 430a210f01e6..a7ebb1115958 100644
> --- a/arch/riscv/boot/dts/eswin/eic7700.dtsi
> +++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi
> @@ -4,6 +4,7 @@
>   */
>  
>  /dts-v1/;
> +#include <dt-bindings/clock/eswin,eic7700-clock.h>
>  #include <dt-bindings/reset/eswin,eic7700-reset.h>
>  
>  / {
> @@ -203,6 +204,11 @@ pmu {
>  				<0x00000000 0x0000000f 0xfffffffc 0x000000ff 0x00000078>;
>  	};
>  
> +	xtal: oscillator {

Sashiko feedback here on making this clk-<hz> or clk-<something> should
be implemented.

> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +	};
> +
>  	soc {
>  		compatible = "simple-bus";
>  		ranges;
> @@ -343,6 +349,13 @@ gpioD: gpio-port@3 {
>  			};
>  		};
>  
> +		clk: clock-controller@51828000 {
> +			compatible = "eswin,eic7700-clock";
> +			reg = <0x0 0x51828000 0x0 0x300>;
> +			clocks = <&xtal>;
> +			#clock-cells = <1>;
> +		};
> +
>  		reset: reset-controller@51828300 {
>  			compatible = "eswin,eic7700-reset";
>  			reg = <0x0 0x51828300 0x0 0x200>;
> -- 
> 2.34.1
> 

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Re: [PATCH 3/7] riscv: dts: eswin: eic7700: add pinctrl support

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 4275 bytes --]

On Mon, Jun 15, 2026 at 05:50:12PM +0530, Pinkesh Vaghela wrote:
> From: Yulin Lu <luyulin@eswincomputing.com>
> 
> Add pinctrl node and related pin configuration for EIC7700 SoC
> 
> Co-developed-by: Pritesh Patel <pritesh.patel@einfochips.com>
> Signed-off-by: Pritesh Patel <pritesh.patel@einfochips.com>
> Signed-off-by: Yulin Lu <luyulin@eswincomputing.com>
> Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
> ---
>  .../dts/eswin/eic7700-hifive-premier-p550.dts | 109 +++
>  .../riscv/boot/dts/eswin/eic7700-pinctrl.dtsi | 888 ++++++++++++++++++
>  arch/riscv/boot/dts/eswin/eic7700.dtsi        |   5 +
>  3 files changed, 1002 insertions(+)
>  create mode 100644 arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi
> 
> diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> index 1fb92f0e7c55..e7bb96e14958 100644
> --- a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> +++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> @@ -6,6 +6,7 @@
>  /dts-v1/;
>  
>  #include "eic7700.dtsi"
> +#include "eic7700-pinctrl.dtsi"
>  
>  / {
>  	compatible = "sifive,hifive-premier-p550", "eswin,eic7700";
> @@ -18,6 +19,15 @@ aliases {
>  	chosen {
>  		stdout-path = "serial0:115200n8";
>  	};
> +
> +	vcc_1v8: vcc1v8 {

Same here.

> +		 compatible = "regulator-fixed";
> +		 regulator-name = "vcc1v8";
> +		 regulator-always-on;
> +		 regulator-boot-on;
> +		 regulator-min-microvolt = <1800000>;
> +		 regulator-max-microvolt = <1800000>;
> +	 };
>  };
>  
>  &xtal {
> @@ -25,6 +35,105 @@ &xtal {
>  	clock-output-names = "xtal24m";
>  };
>  
> +&gpio0_pins {
> +	bias-disable;
> +	input-enable;
> +};
> +
> +&gpio5_pins {
> +	bias-disable;
> +	input-enable;
> +};
> +
> +&gpio11_pins {
> +	bias-disable;
> +	input-enable;
> +};
> +
> +&gpio14_pins {
> +	bias-pull-up;
> +	input-disable;
> +};
> +
> +&gpio15_pins {
> +	bias-disable;
> +	input-enable;
> +};
> +
> +&gpio28_pins {
> +	bias-disable;
> +	input-enable;
> +};
> +
> +&gpio43_pins {
> +	bias-disable;
> +	input-disable;
> +};
> +
> +&gpio71_pins {
> +	bias-pull-up;
> +	input-disable;
> +};
> +
> +&gpio74_pins {
> +	bias-pull-up;
> +	input-disable;
> +};
> +
> +&gpio76_pins {
> +	bias-disable;
> +	input-disable;
> +};
> +
> +&gpio77_pins {
> +	bias-pull-up;
> +	input-disable;
> +};
> +
> +&gpio79_pins {
> +	bias-disable;
> +	input-disable;
> +};
> +
> +&gpio80_pins {
> +	bias-pull-up;
> +	input-disable;
> +};
> +
> +&gpio82_pins {
> +	bias-pull-up;
> +	input-disable;
> +};
> +
> +&gpio84_pins {
> +	bias-disable;
> +	input-disable;
> +};
> +
> +&gpio85_pins {
> +	bias-pull-up;
> +	input-disable;
> +};
> +
> +&gpio94_pins {
> +	bias-disable;
> +	input-disable;
> +};
> +
> +&gpio106_pins {
> +	bias-disable;
> +	input-disable;
> +};
> +
> +&gpio111_pins {
> +	bias-disable;
> +	input-disable;
> +};
> +
> +&pinctrl {
> +	vrgmii-supply = <&vcc_1v8>;
> +};
> +
>  &uart0 {
>  	status = "okay";
>  };
> diff --git a/arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi b/arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi
> new file mode 100644
> index 000000000000..7293df146aa7
> --- /dev/null
> +++ b/arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi
> @@ -0,0 +1,888 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (c) 2025 Beijing ESWIN Computing Technology Co., Ltd.
> + *
> + * ESWIN's EIC7700 SoC pin-mux and pin-config options are listed as
> + * device tree nodes in this file.
> + *
> + * Authors: Yulin Lu <luyulin@eswincomputing.com>
> + */
> +

I don't really understand the groups here. I think you should make more
effort to put more pins in each group.

> +		gpio1_pins: gpio1-pins {
> +			pins = "jtag0_tck";
> +			function = "gpio";
> +		};
> +
> +		gpio2_pins: gpio2-pins {
> +			pins = "jtag0_tms";
> +			function = "gpio";
> +		};
> +
> +		gpio3_pins: gpio3-pins {
> +			pins = "jtag0_tdi";
> +			function = "gpio";
> +		};
> +
> +		gpio4_pins: gpio4-pins {
> +			pins = "jtag0_tdo";
> +			function = "gpio";
> +		};

Like these 4 for example, why not group these?

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Re: [PATCH 6/7] riscv: dts: eswin: add I2C controller support

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 2577 bytes --]

On Mon, Jun 15, 2026 at 05:50:15PM +0530, Pinkesh Vaghela wrote:
> From: Pritesh Patel <pritesh.patel@einfochips.com>
> 
> Add I2C nodes for EIC7700 SoC.
> Also add nodes for corresponding slave devices in dts file and
> enable them for HiFive Premier P550 board
> 
> Signed-off-by: Pritesh Patel <pritesh.patel@einfochips.com>
> Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
> ---
>  .../dts/eswin/eic7700-hifive-premier-p550.dts |  52 ++++++
>  arch/riscv/boot/dts/eswin/eic7700.dtsi        | 156 ++++++++++++++++++
>  2 files changed, 208 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> index e7bb96e14958..0f0c98474c62 100644
> --- a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> +++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> @@ -130,6 +130,58 @@ &gpio111_pins {
>  	input-disable;
>  };
>  
> +&aon_i2c0 {
> +	status = "okay";
> +
> +	eeprom@50 {
> +		compatible = "atmel,24c02";
> +		reg = <0x50>;
> +	};
> +};
> +
> +&aon_i2c1 {
> +	status = "okay";
> +
> +	pac1934@10 {

Generic node name here please. adc I think.

> +		compatible = "microchip,pac1934";
> +		reg = <0x10>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		channel@1 {
> +			reg = <0x1>;
> +			shunt-resistor-micro-ohms = <1000>;
> +			label = "VDD_SOM";
> +		};
> +
> +		channel@2 {
> +			reg = <0x2>;
> +			shunt-resistor-micro-ohms = <1000>;
> +			label = "VDD_SOC";
> +		};
> +
> +		channel@3 {
> +			reg = <0x3>;
> +			shunt-resistor-micro-ohms = <1000>;
> +			label = "VDD_CPU";
> +		};
> +
> +		channel@4 {
> +			reg = <0x4>;
> +			shunt-resistor-micro-ohms = <1000>;
> +			label = "VDD_LPDDR";
> +		};
> +	};
> +
> +	ina226@44 {

And here. power-sensor.

> +		compatible = "ti,ina226";
> +		reg = <0x44>;
> +		#io-channel-cells = <1>;
> +		label = "sys_power";
> +		shunt-resistor = <1000>;
> +	};
> +};
> +
>  &pinctrl {
>  	vrgmii-supply = <&vcc_1v8>;
>  };
> diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/eswin/eic7700.dtsi
> index f8caf39616b2..28706431b2c0 100644
> --- a/arch/riscv/boot/dts/eswin/eic7700.dtsi
> +++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi
> @@ -315,6 +315,162 @@ uart4: serial@50940000 {
>  			status = "disabled";
>  		};
>  
> +		i2c0: i2c@50950000 {
> +			compatible = "snps,designware-i2c";

Missing a soc-specific compatible here for all i2c controllers.


Cheers,
Conor.

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Re: [PATCH 2/7] riscv: dts: eswin: add clock generator for EIC7700 SoC

[Pinkesh Vaghela]

Hi Conor,

Thanks for your time to review the patch.

On Mon, Jun 15, 2026 at 10:01 PM +0530, Conor Dooley wrote:
> On Mon, Jun 15, 2026 at 05:50:11PM +0530, Pinkesh Vaghela wrote:
> > From: Pritesh Patel <pritesh.patel@einfochips.com>
> >
> > Add clock generator node for EIC7700 SoC.
> > HiFive Premier P550 boards have 24MHz crystal oscillator to provide
> > the input clock.
> >
> > Signed-off-by: Pritesh Patel <pritesh.patel@einfochips.com>
> > Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
> > ---
> >  .../boot/dts/eswin/eic7700-hifive-premier-p550.dts  |  5 +++++
> >  arch/riscv/boot/dts/eswin/eic7700.dtsi              | 13 +++++++++++++
> >  2 files changed, 18 insertions(+)
> >
> > diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> > b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> > index 131ed1fc6b2e..1fb92f0e7c55 100644
> > --- a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> > +++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> > @@ -20,6 +20,11 @@ chosen {
> >  	};
> >  };
> >
> > +&xtal {
> > +	clock-frequency = <24000000>;
> > +	clock-output-names = "xtal24m";
> > +};
> > +
> >  &uart0 {
> >  	status = "okay";
> >  };
> > diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi
> > b/arch/riscv/boot/dts/eswin/eic7700.dtsi
> > index 430a210f01e6..a7ebb1115958 100644
> > --- a/arch/riscv/boot/dts/eswin/eic7700.dtsi
> > +++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi
> > @@ -4,6 +4,7 @@
> >   */
> >
> >  /dts-v1/;
> > +#include <dt-bindings/clock/eswin,eic7700-clock.h>
> >  #include <dt-bindings/reset/eswin,eic7700-reset.h>
> >
> >  / {
> > @@ -203,6 +204,11 @@ pmu {
> >  				<0x00000000 0x0000000f 0xfffffffc 0x000000ff
> 0x00000078>;
> >  	};
> >
> > +	xtal: oscillator {
> 
> Sashiko feedback here on making this clk-<hz> or clk-<something> should be
> implemented.

We will change this to "clock-24m" in v2 patch

Regards,
Pinkesh

> 
> > +		compatible = "fixed-clock";
> > +		#clock-cells = <0>;
> > +	};
> > +
> >  	soc {
> >  		compatible = "simple-bus";
> >  		ranges;
> > @@ -343,6 +349,13 @@ gpioD: gpio-port@3 {
> >  			};
> >  		};
> >
> > +		clk: clock-controller@51828000 {
> > +			compatible = "eswin,eic7700-clock";
> > +			reg = <0x0 0x51828000 0x0 0x300>;
> > +			clocks = <&xtal>;
> > +			#clock-cells = <1>;
> > +		};
> > +
> >  		reset: reset-controller@51828300 {
> >  			compatible = "eswin,eic7700-reset";
> >  			reg = <0x0 0x51828300 0x0 0x200>;
> > --
> > 2.34.1
> >

Re: [PATCH 6/7] riscv: dts: eswin: add I2C controller support

[Pinkesh Vaghela]

Hi Conor,

On Mon, Jun 15, 2026 at 10:05 PM +0530, Conor Dooley wrote:
> On Mon, Jun 15, 2026 at 05:50:15PM +0530, Pinkesh Vaghela wrote:
> > From: Pritesh Patel <pritesh.patel@einfochips.com>
> >
> > Add I2C nodes for EIC7700 SoC.
> > Also add nodes for corresponding slave devices in dts file and enable
> > them for HiFive Premier P550 board
> >
> > Signed-off-by: Pritesh Patel <pritesh.patel@einfochips.com>
> > Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
> > ---
> >  .../dts/eswin/eic7700-hifive-premier-p550.dts |  52 ++++++
> >  arch/riscv/boot/dts/eswin/eic7700.dtsi        | 156 ++++++++++++++++++
> >  2 files changed, 208 insertions(+)
> >
> > diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> > b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> > index e7bb96e14958..0f0c98474c62 100644
> > --- a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> > +++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> > @@ -130,6 +130,58 @@ &gpio111_pins {
> >  	input-disable;
> >  };
> >
> > +&aon_i2c0 {
> > +	status = "okay";
> > +
> > +	eeprom@50 {
> > +		compatible = "atmel,24c02";
> > +		reg = <0x50>;
> > +	};
> > +};
> > +
> > +&aon_i2c1 {
> > +	status = "okay";
> > +
> > +	pac1934@10 {
> 
> Generic node name here please. adc I think.

We will change this to "adc@10" in v2 patch

> 
> > +		compatible = "microchip,pac1934";
> > +		reg = <0x10>;
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +
> > +		channel@1 {
> > +			reg = <0x1>;
> > +			shunt-resistor-micro-ohms = <1000>;
> > +			label = "VDD_SOM";
> > +		};
> > +
> > +		channel@2 {
> > +			reg = <0x2>;
> > +			shunt-resistor-micro-ohms = <1000>;
> > +			label = "VDD_SOC";
> > +		};
> > +
> > +		channel@3 {
> > +			reg = <0x3>;
> > +			shunt-resistor-micro-ohms = <1000>;
> > +			label = "VDD_CPU";
> > +		};
> > +
> > +		channel@4 {
> > +			reg = <0x4>;
> > +			shunt-resistor-micro-ohms = <1000>;
> > +			label = "VDD_LPDDR";
> > +		};
> > +	};
> > +
> > +	ina226@44 {
> 
> And here. power-sensor.

We will change this to "power-sensor@44" in v2 patch

> 
> > +		compatible = "ti,ina226";
> > +		reg = <0x44>;
> > +		#io-channel-cells = <1>;
> > +		label = "sys_power";
> > +		shunt-resistor = <1000>;
> > +	};
> > +};
> > +
> >  &pinctrl {
> >  	vrgmii-supply = <&vcc_1v8>;
> >  };
> > diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi
> > b/arch/riscv/boot/dts/eswin/eic7700.dtsi
> > index f8caf39616b2..28706431b2c0 100644
> > --- a/arch/riscv/boot/dts/eswin/eic7700.dtsi
> > +++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi
> > @@ -315,6 +315,162 @@ uart4: serial@50940000 {
> >  			status = "disabled";
> >  		};
> >
> > +		i2c0: i2c@50950000 {
> > +			compatible = "snps,designware-i2c";
> 
> Missing a soc-specific compatible here for all i2c controllers.

We are using generic DesignWare I2C driver for all I2C controllers with no changes required in the driver. Do we still need to add soc-specific compatible for all i2c controllers?

Regards,
Pinkesh

> 
> 
> Cheers,
> Conor.

Re: [PATCH 6/7] riscv: dts: eswin: add I2C controller support

[Conor Dooley]

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On Tue, Jun 16, 2026 at 11:57:33AM +0000, Pinkesh Vaghela wrote:
> On Mon, Jun 15, 2026 at 10:05 PM +0530, Conor Dooley wrote:
> > On Mon, Jun 15, 2026 at 05:50:15PM +0530, Pinkesh Vaghela wrote:
> > > +		i2c0: i2c@50950000 {
> > > +			compatible = "snps,designware-i2c";
> > 
> > Missing a soc-specific compatible here for all i2c controllers.
> 
> We are using generic DesignWare I2C driver for all I2C controllers with
> no changes required in the driver. Do we still need to add soc-specific
> compatible for all i2c controllers?

Yes. Just use "snps,designware-i2c" as a fallback.

Thanks,
Conor.

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Re: Re: [PATCH 3/7] riscv: dts: eswin: eic7700: add pinctrl support

[Yulin Lu]

Hi, Conor. Thanks for your review.

> On Mon, Jun 15, 2026 at 05:50:12PM +0530, Pinkesh Vaghela wrote:
> > From: Yulin Lu <luyulin@eswincomputing.com>
> > 
> > Add pinctrl node and related pin configuration for EIC7700 SoC
> > 
> > Co-developed-by: Pritesh Patel <pritesh.patel@einfochips.com>
> > Signed-off-by: Pritesh Patel <pritesh.patel@einfochips.com>
> > Signed-off-by: Yulin Lu <luyulin@eswincomputing.com>
> > Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
> > ---
> >  .../dts/eswin/eic7700-hifive-premier-p550.dts | 109 +++
> >  .../riscv/boot/dts/eswin/eic7700-pinctrl.dtsi | 888 ++++++++++++++++++
> >  arch/riscv/boot/dts/eswin/eic7700.dtsi        |   5 +
> >  3 files changed, 1002 insertions(+)
> >  create mode 100644 arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi
> > 
> > diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> > index 1fb92f0e7c55..e7bb96e14958 100644
> > --- a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> > +++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> > @@ -6,6 +6,7 @@
> >  /dts-v1/;
> >  
> >  #include "eic7700.dtsi"
> > +#include "eic7700-pinctrl.dtsi"
> >  

...

> > +&gpio79_pins {
> > +	bias-disable;
> > +	input-disable;
> > +};
> > +
> > +&gpio80_pins {
> > +	bias-pull-up;
> > +	input-disable;
> > +};
> > +
> > +&gpio82_pins {
> > +	bias-pull-up;
> > +	input-disable;
> > +};
> > +
> > +&gpio84_pins {
> > +	bias-disable;
> > +	input-disable;
> > +};
> > +
> > +&gpio85_pins {
> > +	bias-pull-up;
> > +	input-disable;
> > +};
> > +
> > +&gpio94_pins {
> > +	bias-disable;
> > +	input-disable;
> > +};
> > +
> > +&gpio106_pins {
> > +	bias-disable;
> > +	input-disable;
> > +};
> > +
> > +&gpio111_pins {
> > +	bias-disable;
> > +	input-disable;
> > +};
> > +
> > +&pinctrl {
> > +	vrgmii-supply = <&vcc_1v8>;
> > +};
> > +
> >  &uart0 {
> >  	status = "okay";
> >  };
> > diff --git a/arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi b/arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi
> > new file mode 100644
> > index 000000000000..7293df146aa7
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi
> > @@ -0,0 +1,888 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/*
> > + * Copyright (c) 2025 Beijing ESWIN Computing Technology Co., Ltd.
> > + *
> > + * ESWIN's EIC7700 SoC pin-mux and pin-config options are listed as
> > + * device tree nodes in this file.
> > + *
> > + * Authors: Yulin Lu <luyulin@eswincomputing.com>
> > + */
> > +
> 
> I don't really understand the groups here. I think you should make more
> effort to put more pins in each group.
> 
> > +		gpio1_pins: gpio1-pins {
> > +			pins = "jtag0_tck";
> > +			function = "gpio";
> > +		};
> > +
> > +		gpio2_pins: gpio2-pins {
> > +			pins = "jtag0_tms";
> > +			function = "gpio";
> > +		};
> > +
> > +		gpio3_pins: gpio3-pins {
> > +			pins = "jtag0_tdi";
> > +			function = "gpio";
> > +		};
> > +
> > +		gpio4_pins: gpio4-pins {
> > +			pins = "jtag0_tdo";
> > +			function = "gpio";
> > +		};
> 
> Like these 4 for example, why not group these?

The 'group' is used to correspond to the '-grp' tag in the YAML file and
has no practical significance.
Different board designs have different requirements for pin multiplexing.
Therefore, eic7700-pinctrl.dtsi only provides pins for the board-level DTS.
Pins are combined and used in the board-level DTS via pinctrl-0 property.

Re: Re: [PATCH 3/7] riscv: dts: eswin: eic7700: add pinctrl support

[Yulin Lu]

Hi, sashiko.

> [Severity: Low]
> Should this node be named using the generic regulator-* pattern (such as
> regulator-1v8) to avoid dtbs_check warnings for deprecated names?
> There is also an extra leading space on the properties within this node
> that deviates from standard spacing.

I will rename this node to "regulator-1v8".

> > +  regulator-name = "vcc1v8";
> > +  regulator-always-on;
> > +  regulator-boot-on;
> > +  regulator-min-microvolt = <1800000>;
> > +  regulator-max-microvolt = <1800000>;
> > +  };
> >  };
> [ ... ]
> > @@ -25,6 +35,105 @@ &xtal {
>   clock-output-names = "xtal24m";
> >  };
> >  
> > +&gpio0_pins {
> > + bias-disable;
> > + input-enable;
> > +};
> [Severity: High]
> Will these pin configuration overrides be silently ignored by the pinctrl
> core during boot?
> Since these pin definitions are not referenced by a pinctrl-0 property in
> an active device node, and are not configured as pinctrl hogs in the provider,
> the intended hardware states for these pins will not be programmed.

I don't think this is an issue. These pin configurations won't be ignored by the kernel during boot.
Some pins have input-enable, pull-down, or pull-up settings that differ from the chip defaults on
certain boards, these configurations are added these configurations in the board-level DTS.

> [ ... ]
> > diff --git a/arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi b/arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi
> > new file mode 100644
> > index 0000000000000..7293df146aa7b
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi
> > @@ -0,0 +1,888 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> [ ... ]
> > + hdmi_pins: hdmi-pins {
> > + pins = "hdmi_scl", "hdmi_sda", "hdmi_cec";
> > + function = "hdmi";
> > + };
> > +
> > + rgmii0_pins: rgmii0-pins {
> > + pins = "rgmii0_clk_125", "rgmii0_txen", "rgmii0_txclk", "rgmii0_txd0",
> > +        "rgmii0_txd1", "rgmii0_txd2", "rgmii0_txd3", "rgmii0_rxclk",
> > +        "rgmii0_rxdv", "rgmii0_rxd0", "rgmii0_rxd1", "rgmii0_rxd2",
> > +        "rgmii0_rxd3", "rgmii0_mdc", "rgmii0_mdio", "rgmii0_intb";
> > + function = "hdmi";
> > + };
> [Severity: High]
> Is the hdmi function correct for this network pin group?
> It appears that rgmii0, rgmii1, and the i2s pin groups that follow all use
> the hdmi function. This will prevent the pin controller from routing these
> pins properly, likely leading to driver probe failures when peripherals
> attempt to request them.

I will fix the function of rgmii0_pins and rgmii1_pins to rgmii, and the function of i2s0_pins,
i2s1_pins, and i2s2_pins to i2s.

> [ ... ]
> > diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/eswin/eic7700.dtsi
> > index a7ebb11159580..8798c50f7584d 100644
> > --- a/arch/riscv/boot/dts/eswin/eic7700.dtsi
> > +++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi
> > @@ -349,6 +349,11 @@ gpioD: gpio-port@3 {
> >   };
> >   };
> >  
> > + pinctrl: pinctrl@51600080 {
> > + compatible = "eswin,eic7700-pinctrl";
> > + reg = <0x0 0x51600080 0x0 0x1fff80>;
> > + };
> > +
> [Severity: High]
> Should the existing gpio controller nodes (gpioA, gpioB, gpioC, and gpioD)
> be updated with a gpio-ranges property mapping to this new pinctrl provider?
> Without gpio-ranges, the GPIO subsystem cannot translate GPIO offsets into
> pinctrl pins. The pinctrl core's .gpio_request_enable callback will not be
> invoked when a software component requests a GPIO dynamically, preventing
> the multiplexer from automatically switching the pin to GPIO mode.
> >   clk: clock-controller@51828000 {
> >   compatible = "eswin,eic7700-clock";

I think add gpio-ranges is unnecessary, the driver does not implement
the .gpio_request_enable callback.

Regards,
Yulin Lu

Re: Re: [PATCH 3/7] riscv: dts: eswin: eic7700: add pinctrl support

[Conor Dooley]

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On Fri, Jun 26, 2026 at 02:01:42PM +0800, Yulin Lu wrote:
> Hi, Conor. Thanks for your review.
> 
> > On Mon, Jun 15, 2026 at 05:50:12PM +0530, Pinkesh Vaghela wrote:
> > > From: Yulin Lu <luyulin@eswincomputing.com>
> > > 
> > > Add pinctrl node and related pin configuration for EIC7700 SoC
> > > 
> > > Co-developed-by: Pritesh Patel <pritesh.patel@einfochips.com>
> > > Signed-off-by: Pritesh Patel <pritesh.patel@einfochips.com>
> > > Signed-off-by: Yulin Lu <luyulin@eswincomputing.com>
> > > Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
> > > ---
> > >  .../dts/eswin/eic7700-hifive-premier-p550.dts | 109 +++
> > >  .../riscv/boot/dts/eswin/eic7700-pinctrl.dtsi | 888 ++++++++++++++++++
> > >  arch/riscv/boot/dts/eswin/eic7700.dtsi        |   5 +
> > >  3 files changed, 1002 insertions(+)
> > >  create mode 100644 arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi
> > > 
> > > diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> > > index 1fb92f0e7c55..e7bb96e14958 100644
> > > --- a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> > > +++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> > > @@ -6,6 +6,7 @@
> > >  /dts-v1/;
> > >  
> > >  #include "eic7700.dtsi"
> > > +#include "eic7700-pinctrl.dtsi"
> > >  
> 
> ...
> 
> > > +&gpio79_pins {
> > > +	bias-disable;
> > > +	input-disable;
> > > +};
> > > +
> > > +&gpio80_pins {
> > > +	bias-pull-up;
> > > +	input-disable;
> > > +};
> > > +
> > > +&gpio82_pins {
> > > +	bias-pull-up;
> > > +	input-disable;
> > > +};
> > > +
> > > +&gpio84_pins {
> > > +	bias-disable;
> > > +	input-disable;
> > > +};
> > > +
> > > +&gpio85_pins {
> > > +	bias-pull-up;
> > > +	input-disable;
> > > +};
> > > +
> > > +&gpio94_pins {
> > > +	bias-disable;
> > > +	input-disable;
> > > +};
> > > +
> > > +&gpio106_pins {
> > > +	bias-disable;
> > > +	input-disable;
> > > +};
> > > +
> > > +&gpio111_pins {
> > > +	bias-disable;
> > > +	input-disable;
> > > +};
> > > +
> > > +&pinctrl {
> > > +	vrgmii-supply = <&vcc_1v8>;
> > > +};
> > > +
> > >  &uart0 {
> > >  	status = "okay";
> > >  };
> > > diff --git a/arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi b/arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi
> > > new file mode 100644
> > > index 000000000000..7293df146aa7
> > > --- /dev/null
> > > +++ b/arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi
> > > @@ -0,0 +1,888 @@
> > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > > +/*
> > > + * Copyright (c) 2025 Beijing ESWIN Computing Technology Co., Ltd.
> > > + *
> > > + * ESWIN's EIC7700 SoC pin-mux and pin-config options are listed as
> > > + * device tree nodes in this file.
> > > + *
> > > + * Authors: Yulin Lu <luyulin@eswincomputing.com>
> > > + */
> > > +
> > 
> > I don't really understand the groups here. I think you should make more
> > effort to put more pins in each group.
> > 
> > > +		gpio1_pins: gpio1-pins {
> > > +			pins = "jtag0_tck";
> > > +			function = "gpio";
> > > +		};
> > > +
> > > +		gpio2_pins: gpio2-pins {
> > > +			pins = "jtag0_tms";
> > > +			function = "gpio";
> > > +		};
> > > +
> > > +		gpio3_pins: gpio3-pins {
> > > +			pins = "jtag0_tdi";
> > > +			function = "gpio";
> > > +		};
> > > +
> > > +		gpio4_pins: gpio4-pins {
> > > +			pins = "jtag0_tdo";
> > > +			function = "gpio";
> > > +		};
> > 
> > Like these 4 for example, why not group these?
> 
> The 'group' is used to correspond to the '-grp' tag in the YAML file and
> has no practical significance.
> Different board designs have different requirements for pin multiplexing.
> Therefore, eic7700-pinctrl.dtsi only provides pins for the board-level DTS.
> Pins are combined and used in the board-level DTS via pinctrl-0 property.

These 4 pins in the driver are represented as:
	EIC7700_PIN(14,  "jtag0_tck",		[0] = F_JTAG, [1] = F_SPI, [2] = F_GPIO),
	EIC7700_PIN(15,  "jtag0_tms",		[0] = F_JTAG, [1] = F_SPI, [2] = F_GPIO),
	EIC7700_PIN(16,  "jtag0_tdi",		[0] = F_JTAG, [1] = F_SPI, [2] = F_GPIO),
	EIC7700_PIN(17,  "jtag0_tdo",		[0] = F_JTAG, [1] = F_SPI, [2] = F_GPIO),

	EIC7700_PIN(18,  "gpio5",		[0] = F_GPIO, [1] = F_SPI),

There is no reason to ever partially use these as GPIO. Either they will
be all jtag, all spi or all gpio. pin 18 on the other than makes sense to have
in a dedicated group.

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Re: Re: Re: [PATCH 3/7] riscv: dts: eswin: eic7700: add pinctrl support

[Yulin Lu]

> > Hi, Conor. Thanks for your review.
> > 
> > > On Mon, Jun 15, 2026 at 05:50:12PM +0530, Pinkesh Vaghela wrote:
> > > > From: Yulin Lu <luyulin@eswincomputing.com>
> > > > 
> > > > Add pinctrl node and related pin configuration for EIC7700 SoC
> > > > 
> > > > Co-developed-by: Pritesh Patel <pritesh.patel@einfochips.com>
> > > > Signed-off-by: Pritesh Patel <pritesh.patel@einfochips.com>
> > > > Signed-off-by: Yulin Lu <luyulin@eswincomputing.com>
> > > > Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
> > > > ---
> > > >  .../dts/eswin/eic7700-hifive-premier-p550.dts | 109 +++
> > > >  .../riscv/boot/dts/eswin/eic7700-pinctrl.dtsi | 888 ++++++++++++++++++
> > > >  arch/riscv/boot/dts/eswin/eic7700.dtsi        |   5 +
> > > >  3 files changed, 1002 insertions(+)
> > > >  create mode 100644 arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi
> > > > 
> > > > diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> > > > index 1fb92f0e7c55..e7bb96e14958 100644
> > > > --- a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> > > > +++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> > > > @@ -6,6 +6,7 @@
> > > >  /dts-v1/;
> > > >  
> > > >  #include "eic7700.dtsi"
> > > > +#include "eic7700-pinctrl.dtsi"
> > > >  
> > 
> > ...
> > 
> > > > +&gpio79_pins {
> > > > +	bias-disable;
> > > > +	input-disable;
> > > > +};
> > > > +
> > > > +&gpio80_pins {
> > > > +	bias-pull-up;
> > > > +	input-disable;
> > > > +};
> > > > +
> > > > +&gpio82_pins {
> > > > +	bias-pull-up;
> > > > +	input-disable;
> > > > +};
> > > > +
> > > > +&gpio84_pins {
> > > > +	bias-disable;
> > > > +	input-disable;
> > > > +};
> > > > +
> > > > +&gpio85_pins {
> > > > +	bias-pull-up;
> > > > +	input-disable;
> > > > +};
> > > > +
> > > > +&gpio94_pins {
> > > > +	bias-disable;
> > > > +	input-disable;
> > > > +};
> > > > +
> > > > +&gpio106_pins {
> > > > +	bias-disable;
> > > > +	input-disable;
> > > > +};
> > > > +
> > > > +&gpio111_pins {
> > > > +	bias-disable;
> > > > +	input-disable;
> > > > +};
> > > > +
> > > > +&pinctrl {
> > > > +	vrgmii-supply = <&vcc_1v8>;
> > > > +};
> > > > +
> > > >  &uart0 {
> > > >  	status = "okay";
> > > >  };
> > > > diff --git a/arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi b/arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi
> > > > new file mode 100644
> > > > index 000000000000..7293df146aa7
> > > > --- /dev/null
> > > > +++ b/arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi
> > > > @@ -0,0 +1,888 @@
> > > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > > > +/*
> > > > + * Copyright (c) 2025 Beijing ESWIN Computing Technology Co., Ltd.
> > > > + *
> > > > + * ESWIN's EIC7700 SoC pin-mux and pin-config options are listed as
> > > > + * device tree nodes in this file.
> > > > + *
> > > > + * Authors: Yulin Lu <luyulin@eswincomputing.com>
> > > > + */
> > > > +
> > > 
> > > I don't really understand the groups here. I think you should make more
> > > effort to put more pins in each group.
> > > 
> > > > +		gpio1_pins: gpio1-pins {
> > > > +			pins = "jtag0_tck";
> > > > +			function = "gpio";
> > > > +		};
> > > > +
> > > > +		gpio2_pins: gpio2-pins {
> > > > +			pins = "jtag0_tms";
> > > > +			function = "gpio";
> > > > +		};
> > > > +
> > > > +		gpio3_pins: gpio3-pins {
> > > > +			pins = "jtag0_tdi";
> > > > +			function = "gpio";
> > > > +		};
> > > > +
> > > > +		gpio4_pins: gpio4-pins {
> > > > +			pins = "jtag0_tdo";
> > > > +			function = "gpio";
> > > > +		};
> > > 
> > > Like these 4 for example, why not group these?
> > 
> > The 'group' is used to correspond to the '-grp' tag in the YAML file and
> > has no practical significance.
> > Different board designs have different requirements for pin multiplexing.
> > Therefore, eic7700-pinctrl.dtsi only provides pins for the board-level DTS.
> > Pins are combined and used in the board-level DTS via pinctrl-0 property.
> 
> These 4 pins in the driver are represented as:
> 	EIC7700_PIN(14,  "jtag0_tck",		[0] = F_JTAG, [1] = F_SPI, [2] = F_GPIO),
> 	EIC7700_PIN(15,  "jtag0_tms",		[0] = F_JTAG, [1] = F_SPI, [2] = F_GPIO),
> 	EIC7700_PIN(16,  "jtag0_tdi",		[0] = F_JTAG, [1] = F_SPI, [2] = F_GPIO),
> 	EIC7700_PIN(17,  "jtag0_tdo",		[0] = F_JTAG, [1] = F_SPI, [2] = F_GPIO),
> 
> 	EIC7700_PIN(18,  "gpio5",		[0] = F_GPIO, [1] = F_SPI),
> 
> There is no reason to ever partially use these as GPIO. Either they will
> be all jtag, all spi or all gpio. pin 18 on the other than makes sense to have
> in a dedicated group.

Hi, Conor. Thanks for your reply.

For pins 14 to 18, when they are not multiplexed as JTAG or SPI,
they can be used as GPIO. The corresponding -pins combinations
for JTAG, SPI, and GPIO are all implemented in eic7700-pinctrl.dtsi.

Take pin 14 as an example. In eic7700-pinctrl.dtsi, it is defined:

dual_spi2_pins: dual-spi2-pins {
    pins = "spi2_cs0_n", "jtag0_tck", "jtag0_tms", "jtag0_tdi";
    function = "spi";
};

quad_spi2_pins: quad-spi2-pins {
    pins = "spi2_cs0_n", "spi2_cs1_n", "jtag0_tck", "jtag0_tms",
           "jtag0_tdi", "jtag0_tdo", "gpio5";
    function = "spi";
};

gpio1_pins: gpio1-pins {
    pins = "jtag0_tck";
    function = "gpio";
};

jtag0_pins: jtag0-pins {
    pins = "jtag0_tck", "jtag0_tms", "jtag0_tdi", "jtag0_tdo";
    function = "jtag";
};

Which specific combination is called, and how they are combined,
depends on the board-level system design and is referenced in
the device nodes of the board-level DTS. For example:

pinctrl-0 = <&gpio1_pins>, <&jtag2_pins>;

The pin multiplexing configuration depends on the board-level system design.
Using combinations of '-pins' is sufficient to satisfy all requirements,
and there is no need to rely on '-grp' for this purpose.

Regards,
Yulin Lu

Re: Re: Re: [PATCH 3/7] riscv: dts: eswin: eic7700: add pinctrl support

[Conor Dooley]

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On Fri, Jun 26, 2026 at 04:42:32PM +0800, Yulin Lu wrote:
> > > Hi, Conor. Thanks for your review.
> > > 
> > > > On Mon, Jun 15, 2026 at 05:50:12PM +0530, Pinkesh Vaghela wrote:
> > > > > From: Yulin Lu <luyulin@eswincomputing.com>
> > > > > 
> > > > > Add pinctrl node and related pin configuration for EIC7700 SoC
> > > > > 
> > > > > Co-developed-by: Pritesh Patel <pritesh.patel@einfochips.com>
> > > > > Signed-off-by: Pritesh Patel <pritesh.patel@einfochips.com>
> > > > > Signed-off-by: Yulin Lu <luyulin@eswincomputing.com>
> > > > > Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
> > > > > ---
> > > > >  .../dts/eswin/eic7700-hifive-premier-p550.dts | 109 +++
> > > > >  .../riscv/boot/dts/eswin/eic7700-pinctrl.dtsi | 888 ++++++++++++++++++
> > > > >  arch/riscv/boot/dts/eswin/eic7700.dtsi        |   5 +
> > > > >  3 files changed, 1002 insertions(+)
> > > > >  create mode 100644 arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi
> > > > > 
> > > > > diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> > > > > index 1fb92f0e7c55..e7bb96e14958 100644
> > > > > --- a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> > > > > +++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
> > > > > @@ -6,6 +6,7 @@
> > > > >  /dts-v1/;
> > > > >  
> > > > >  #include "eic7700.dtsi"
> > > > > +#include "eic7700-pinctrl.dtsi"
> > > > >  
> > > 
> > > ...
> > > 
> > > > > +&gpio79_pins {
> > > > > +	bias-disable;
> > > > > +	input-disable;
> > > > > +};
> > > > > +
> > > > > +&gpio80_pins {
> > > > > +	bias-pull-up;
> > > > > +	input-disable;
> > > > > +};
> > > > > +
> > > > > +&gpio82_pins {
> > > > > +	bias-pull-up;
> > > > > +	input-disable;
> > > > > +};
> > > > > +
> > > > > +&gpio84_pins {
> > > > > +	bias-disable;
> > > > > +	input-disable;
> > > > > +};
> > > > > +
> > > > > +&gpio85_pins {
> > > > > +	bias-pull-up;
> > > > > +	input-disable;
> > > > > +};
> > > > > +
> > > > > +&gpio94_pins {
> > > > > +	bias-disable;
> > > > > +	input-disable;
> > > > > +};
> > > > > +
> > > > > +&gpio106_pins {
> > > > > +	bias-disable;
> > > > > +	input-disable;
> > > > > +};
> > > > > +
> > > > > +&gpio111_pins {
> > > > > +	bias-disable;
> > > > > +	input-disable;
> > > > > +};
> > > > > +
> > > > > +&pinctrl {
> > > > > +	vrgmii-supply = <&vcc_1v8>;
> > > > > +};
> > > > > +
> > > > >  &uart0 {
> > > > >  	status = "okay";
> > > > >  };
> > > > > diff --git a/arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi b/arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi
> > > > > new file mode 100644
> > > > > index 000000000000..7293df146aa7
> > > > > --- /dev/null
> > > > > +++ b/arch/riscv/boot/dts/eswin/eic7700-pinctrl.dtsi
> > > > > @@ -0,0 +1,888 @@
> > > > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > > > > +/*
> > > > > + * Copyright (c) 2025 Beijing ESWIN Computing Technology Co., Ltd.
> > > > > + *
> > > > > + * ESWIN's EIC7700 SoC pin-mux and pin-config options are listed as
> > > > > + * device tree nodes in this file.
> > > > > + *
> > > > > + * Authors: Yulin Lu <luyulin@eswincomputing.com>
> > > > > + */
> > > > > +
> > > > 
> > > > I don't really understand the groups here. I think you should make more
> > > > effort to put more pins in each group.
> > > > 
> > > > > +		gpio1_pins: gpio1-pins {
> > > > > +			pins = "jtag0_tck";
> > > > > +			function = "gpio";
> > > > > +		};
> > > > > +
> > > > > +		gpio2_pins: gpio2-pins {
> > > > > +			pins = "jtag0_tms";
> > > > > +			function = "gpio";
> > > > > +		};
> > > > > +
> > > > > +		gpio3_pins: gpio3-pins {
> > > > > +			pins = "jtag0_tdi";
> > > > > +			function = "gpio";
> > > > > +		};
> > > > > +
> > > > > +		gpio4_pins: gpio4-pins {
> > > > > +			pins = "jtag0_tdo";
> > > > > +			function = "gpio";
> > > > > +		};
> > > > 
> > > > Like these 4 for example, why not group these?
> > > 
> > > The 'group' is used to correspond to the '-grp' tag in the YAML file and
> > > has no practical significance.
> > > Different board designs have different requirements for pin multiplexing.
> > > Therefore, eic7700-pinctrl.dtsi only provides pins for the board-level DTS.
> > > Pins are combined and used in the board-level DTS via pinctrl-0 property.
> > 
> > These 4 pins in the driver are represented as:
> > 	EIC7700_PIN(14,  "jtag0_tck",		[0] = F_JTAG, [1] = F_SPI, [2] = F_GPIO),
> > 	EIC7700_PIN(15,  "jtag0_tms",		[0] = F_JTAG, [1] = F_SPI, [2] = F_GPIO),
> > 	EIC7700_PIN(16,  "jtag0_tdi",		[0] = F_JTAG, [1] = F_SPI, [2] = F_GPIO),
> > 	EIC7700_PIN(17,  "jtag0_tdo",		[0] = F_JTAG, [1] = F_SPI, [2] = F_GPIO),
> > 
> > 	EIC7700_PIN(18,  "gpio5",		[0] = F_GPIO, [1] = F_SPI),
> > 
> > There is no reason to ever partially use these as GPIO. Either they will
> > be all jtag, all spi or all gpio. pin 18 on the other than makes sense to have
> > in a dedicated group.
> 
> Hi, Conor. Thanks for your reply.
> 
> For pins 14 to 18, when they are not multiplexed as JTAG or SPI,
> they can be used as GPIO. The corresponding -pins combinations
> for JTAG, SPI, and GPIO are all implemented in eic7700-pinctrl.dtsi.
> 
> Take pin 14 as an example. In eic7700-pinctrl.dtsi, it is defined:
> 
> dual_spi2_pins: dual-spi2-pins {
>     pins = "spi2_cs0_n", "jtag0_tck", "jtag0_tms", "jtag0_tdi";
>     function = "spi";
> };
> 
> quad_spi2_pins: quad-spi2-pins {
>     pins = "spi2_cs0_n", "spi2_cs1_n", "jtag0_tck", "jtag0_tms",
>            "jtag0_tdi", "jtag0_tdo", "gpio5";
>     function = "spi";
> };
> 
> gpio1_pins: gpio1-pins {
>     pins = "jtag0_tck";
>     function = "gpio";
> };
> 
> jtag0_pins: jtag0-pins {
>     pins = "jtag0_tck", "jtag0_tms", "jtag0_tdi", "jtag0_tdo";
>     function = "jtag";
> };
> 
> Which specific combination is called, and how they are combined,
> depends on the board-level system design and is referenced in
> the device nodes of the board-level DTS. For example:
> 
> pinctrl-0 = <&gpio1_pins>, <&jtag2_pins>;
> 
> The pin multiplexing configuration depends on the board-level system design.
> Using combinations of '-pins' is sufficient to satisfy all requirements,
> and there is no need to rely on '-grp' for this purpose.

What has -grp got to do with this?
All I am asking for is for you to do
gpio_jtag_pins: gpio-jtag-pins {
	pins = "jtag0_tck", "jtag0_tms", "jtag0_tdi", "jtag0_tdo";
	function = "gpio";
};

and wherever else you can make similar simplifications.

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