[PATCH v2 0/2] arm64: dts: qcom: Add DT support for secondary USB on QCS615

[PATCH v2 0/2] arm64: dts: qcom: Add DT support for secondary USB on QCS615

[Song Xue]

From: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>

These series aim at enabling secondary USB on QCS615. The secondary
controller is High Speed capable and has a QUSB2 Phy.

Base DT Support has been added and is enabled on Ride Platform. The
secondary controller is enabled in host mode.

Signed-off-by: Song Xue <quic_songxue@quicinc.com>
---
Dependencies:
Link to bindings and driver changes:
https://lore.kernel.org/all/20241017130701.3301785-1-quic_kriskura@quicinc.com/

PMIC DT:
https://lore.kernel.org/all/20241202-adds-spmi-pmic-peripherals-for-qcs615-v6-0-bdd306b4940d@quicinc.com/

---
Changes in v2:
- Modified "0" dec to "0x0" hex in reg property. 
- Link to v1: https://lore.kernel.org/r/20241211-add_usb_host_mode_for_qcs615-v1-0-edce37204a85@quicinc.com

---
Krishna Kurapati (2):
      arm64: dts: qcom: Add support for secondary USB node on QCS615
      arm64: dts: qcom: Enable secondary USB controller on QCS615 Ride

 arch/arm64/boot/dts/qcom/qcs615-ride.dts | 28 ++++++++++++
 arch/arm64/boot/dts/qcom/qcs615.dtsi     | 76 ++++++++++++++++++++++++++++++++
 2 files changed, 104 insertions(+)
---
base-commit: f2b086fc9f039773445d2606dc65dc091ec1830f
change-id: 20241211-add_usb_host_mode_for_qcs615-61feb12fabd0

Best regards,
-- 
Song Xue <quic_songxue@quicinc.com>

[PATCH v2 1/2] arm64: dts: qcom: Add support for secondary USB node on QCS615

[Song Xue]

From: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>

Add support for secondary USB controller and its high-speed phy
on QCS615.

Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
Co-developed-by: Song Xue <quic_songxue@quicinc.com>
Signed-off-by: Song Xue <quic_songxue@quicinc.com>
---
 arch/arm64/boot/dts/qcom/qcs615.dtsi | 76 ++++++++++++++++++++++++++++++++++++
 1 file changed, 76 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
index b8388dcca94cd8f4e6f1360305d5f6c7fff4eec3..651c6c8b8bc40886139fa235874e834928e14e77 100644
--- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
@@ -3079,6 +3079,20 @@ usb_1_hsphy: phy@88e2000 {
 			status = "disabled";
 		};
 
+		usb_hsphy_2: phy@88e3000 {
+			compatible = "qcom,qcs615-qusb2-phy";
+			reg = <0x0 0x088e3000 0x0 0x180>;
+
+			clocks = <&gcc GCC_AHB2PHY_WEST_CLK>, <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "cfg_ahb", "ref";
+
+			resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
+
+			#phy-cells = <0>;
+
+			status = "disabled";
+		};
+
 		usb_qmpphy: phy@88e6000 {
 			compatible = "qcom,qcs615-qmp-usb3-phy";
 			reg = <0x0 0x88e6000 0x0 0x1000>;
@@ -3168,6 +3182,68 @@ usb_1_dwc3: usb@a600000 {
 				snps,usb3_lpm_capable;
 			};
 		};
+
+		usb_2: usb@a8f8800 {
+			compatible = "qcom,qcs615-dwc3", "qcom,dwc3";
+			reg = <0x0 0x0a8f8800 0x0 0x400>;
+
+			clocks = <&gcc GCC_CFG_NOC_USB2_SEC_AXI_CLK>,
+				 <&gcc GCC_USB20_SEC_MASTER_CLK>,
+				 <&gcc GCC_AGGRE_USB2_SEC_AXI_CLK>,
+				 <&gcc GCC_USB20_SEC_SLEEP_CLK>,
+				 <&gcc GCC_USB20_SEC_MOCK_UTMI_CLK>,
+				 <&gcc GCC_USB2_PRIM_CLKREF_CLK>;
+			clock-names = "cfg_noc",
+				      "core",
+				      "iface",
+				      "sleep",
+				      "mock_utmi",
+				      "xo";
+
+			assigned-clocks = <&gcc GCC_USB20_SEC_MOCK_UTMI_CLK>,
+					  <&gcc GCC_USB20_SEC_MASTER_CLK>;
+			assigned-clock-rates = <19200000>, <200000000>;
+
+			interrupts-extended = <&intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH>,
+					      <&intc GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>,
+					      <&pdc 11 IRQ_TYPE_EDGE_BOTH>,
+					      <&pdc 10 IRQ_TYPE_EDGE_BOTH>;
+			interrupt-names = "pwr_event",
+					  "hs_phy_irq",
+					  "dp_hs_phy_irq",
+					  "dm_hs_phy_irq";
+
+			power-domains = <&gcc USB20_SEC_GDSC>;
+			required-opps = <&rpmhpd_opp_nom>;
+
+			resets = <&gcc GCC_USB20_SEC_BCR>;
+
+			qcom,select-utmi-as-pipe-clk;
+
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			status = "disabled";
+
+			usb_2_dwc3: usb@a800000 {
+				compatible = "snps,dwc3";
+				reg = <0x0 0x0a800000 0x0 0xcd00>;
+
+				iommus = <&apps_smmu 0xe0 0x0>;
+				interrupts = <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>;
+
+				phys = <&usb_hsphy_2>;
+				phy-names = "usb2-phy";
+
+				snps,dis_u2_susphy_quirk;
+				snps,dis_enblslpm_quirk;
+				snps,has-lpm-erratum;
+				snps,hird-threshold = /bits/ 8 <0x10>;
+
+				maximum-speed = "high-speed";
+			};
+		};
 	};
 
 	arch_timer: timer {

-- 
2.25.1

[PATCH v2 2/2] arm64: dts: qcom: Enable secondary USB controller on QCS615 Ride

[Song Xue]

From: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>

Enable secondary USB controller on QCS615 Ride platform. The secondary
USB controller is made "host", as it is a Type-A port.

Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
Co-developed-by: Song Xue <quic_songxue@quicinc.com>
Signed-off-by: Song Xue <quic_songxue@quicinc.com>
---
 arch/arm64/boot/dts/qcom/qcs615-ride.dts | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
index f41319ff47b983d771da52775fa78b4385c4e532..26ce0496d13ccbfea392c6d50d9edcab85fbc653 100644
--- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts
+++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
@@ -203,6 +203,15 @@ &gcc {
 		 <&sleep_clk>;
 };
 
+&pm8150_gpios {
+	usb2_en_state: usb2-en-state {
+		pins = "gpio10";
+		function = "normal";
+		output-high;
+		power-source = <0>;
+	};
+};
+
 &pon_pwrkey {
 	status = "okay";
 };
@@ -248,6 +257,25 @@ &usb_1_dwc3 {
 	dr_mode = "peripheral";
 };
 
+&usb_hsphy_2 {
+	vdd-supply = <&vreg_l5a>;
+	vdda-pll-supply = <&vreg_l12a>;
+	vdda-phy-dpdm-supply = <&vreg_l13a>;
+
+	status = "okay";
+};
+
+&usb_2 {
+	pinctrl-0 = <&usb2_en_state>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&usb_2_dwc3 {
+	dr_mode = "host";
+};
+
 &watchdog {
 	clocks = <&sleep_clk>;
 };

-- 
2.25.1

Re: [PATCH v2 1/2] arm64: dts: qcom: Add support for secondary USB node on QCS615

[Konrad Dybcio]

On 11.12.2024 9:26 AM, Song Xue wrote:
> From: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
> 
> Add support for secondary USB controller and its high-speed phy
> on QCS615.
> 
> Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
> Co-developed-by: Song Xue <quic_songxue@quicinc.com>
> Signed-off-by: Song Xue <quic_songxue@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/qcs615.dtsi | 76 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 76 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> index b8388dcca94cd8f4e6f1360305d5f6c7fff4eec3..651c6c8b8bc40886139fa235874e834928e14e77 100644
> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> @@ -3079,6 +3079,20 @@ usb_1_hsphy: phy@88e2000 {
>  			status = "disabled";
>  		};
>  
> +		usb_hsphy_2: phy@88e3000 {
> +			compatible = "qcom,qcs615-qusb2-phy";
> +			reg = <0x0 0x088e3000 0x0 0x180>;
> +
> +			clocks = <&gcc GCC_AHB2PHY_WEST_CLK>, <&rpmhcc RPMH_CXO_CLK>;
> +			clock-names = "cfg_ahb", "ref";

Having this be a vertical list would be nice

Nonetheless, this looks good and the magic numbers all line
up with what the computer tells me. You may want to check
with Krishna Kurapati whether snps,parkmode-disable-ss-quirk
here as well.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH v2 2/2] arm64: dts: qcom: Enable secondary USB controller on QCS615 Ride

[Konrad Dybcio]

On 11.12.2024 9:26 AM, Song Xue wrote:
> From: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
> 
> Enable secondary USB controller on QCS615 Ride platform. The secondary
> USB controller is made "host", as it is a Type-A port.
> 
> Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
> Co-developed-by: Song Xue <quic_songxue@quicinc.com>
> Signed-off-by: Song Xue <quic_songxue@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/qcs615-ride.dts | 28 ++++++++++++++++++++++++++++
>  1 file changed, 28 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
> index f41319ff47b983d771da52775fa78b4385c4e532..26ce0496d13ccbfea392c6d50d9edcab85fbc653 100644
> --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts
> +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
> @@ -203,6 +203,15 @@ &gcc {
>  		 <&sleep_clk>;
>  };
>  
> +&pm8150_gpios {
> +	usb2_en_state: usb2-en-state {
> +		pins = "gpio10";
> +		function = "normal";
> +		output-high;
> +		power-source = <0>;
> +	};

Does this go to an enable pin of a vreg / switch?

I think we settled on describing such cases as fixed regulators
(that are always-on for now) - would you remember, +Dmitry?

The rest looks good.

Konrad

Re: [PATCH v2 2/2] arm64: dts: qcom: Enable secondary USB controller on QCS615 Ride

[Dmitry Baryshkov]

On Thu, Dec 12, 2024 at 07:14:22PM +0100, Konrad Dybcio wrote:
> On 11.12.2024 9:26 AM, Song Xue wrote:
> > From: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
> > 
> > Enable secondary USB controller on QCS615 Ride platform. The secondary
> > USB controller is made "host", as it is a Type-A port.
> > 
> > Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
> > Co-developed-by: Song Xue <quic_songxue@quicinc.com>
> > Signed-off-by: Song Xue <quic_songxue@quicinc.com>
> > ---
> >  arch/arm64/boot/dts/qcom/qcs615-ride.dts | 28 ++++++++++++++++++++++++++++
> >  1 file changed, 28 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
> > index f41319ff47b983d771da52775fa78b4385c4e532..26ce0496d13ccbfea392c6d50d9edcab85fbc653 100644
> > --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts
> > +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
> > @@ -203,6 +203,15 @@ &gcc {
> >  		 <&sleep_clk>;
> >  };
> >  
> > +&pm8150_gpios {
> > +	usb2_en_state: usb2-en-state {
> > +		pins = "gpio10";
> > +		function = "normal";
> > +		output-high;
> > +		power-source = <0>;
> > +	};
> 
> Does this go to an enable pin of a vreg / switch?
> 
> I think we settled on describing such cases as fixed regulators
> (that are always-on for now) - would you remember, +Dmitry?

You are right. Usually it's a fixed regulator. At least there should be
an explanation for that pin.

> 
> The rest looks good.
> 
> Konrad

-- 
With best wishes
Dmitry

Re: [PATCH v2 1/2] arm64: dts: qcom: Add support for secondary USB node on QCS615

[Krishna Kurapati]

On 12/12/2024 11:40 PM, Konrad Dybcio wrote:
> On 11.12.2024 9:26 AM, Song Xue wrote:
>> From: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
>>
>> Add support for secondary USB controller and its high-speed phy
>> on QCS615.
>>
>> Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
>> Co-developed-by: Song Xue <quic_songxue@quicinc.com>
>> Signed-off-by: Song Xue <quic_songxue@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/qcs615.dtsi | 76 ++++++++++++++++++++++++++++++++++++
>>   1 file changed, 76 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>> index b8388dcca94cd8f4e6f1360305d5f6c7fff4eec3..651c6c8b8bc40886139fa235874e834928e14e77 100644
>> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>> @@ -3079,6 +3079,20 @@ usb_1_hsphy: phy@88e2000 {
>>   			status = "disabled";
>>   		};
>>   
>> +		usb_hsphy_2: phy@88e3000 {
>> +			compatible = "qcom,qcs615-qusb2-phy";
>> +			reg = <0x0 0x088e3000 0x0 0x180>;
>> +
>> +			clocks = <&gcc GCC_AHB2PHY_WEST_CLK>, <&rpmhcc RPMH_CXO_CLK>;
>> +			clock-names = "cfg_ahb", "ref";
> 
> Having this be a vertical list would be nice
> 
> Nonetheless, this looks good and the magic numbers all line
> up with what the computer tells me. You may want to check
> with Krishna Kurapati whether snps,parkmode-disable-ss-quirk
> here as well.
> 
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>


Thanks for the review Konrad.

This is HS only controller and this quirk is not necessary.

Regards,
Krishna,

Re: [PATCH v2 2/2] arm64: dts: qcom: Enable secondary USB controller on QCS615 Ride

[Song Xue]

On 12/13/2024 2:14 AM, Konrad Dybcio wrote:
> On 11.12.2024 9:26 AM, Song Xue wrote:
>> From: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
>>
>> Enable secondary USB controller on QCS615 Ride platform. The secondary
>> USB controller is made "host", as it is a Type-A port.
>>
>> Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
>> Co-developed-by: Song Xue <quic_songxue@quicinc.com>
>> Signed-off-by: Song Xue <quic_songxue@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/qcs615-ride.dts | 28 ++++++++++++++++++++++++++++
>>   1 file changed, 28 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
>> index f41319ff47b983d771da52775fa78b4385c4e532..26ce0496d13ccbfea392c6d50d9edcab85fbc653 100644
>> --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts
>> +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
>> @@ -203,6 +203,15 @@ &gcc {
>>   		 <&sleep_clk>;
>>   };
>>   
>> +&pm8150_gpios {
>> +	usb2_en_state: usb2-en-state {
>> +		pins = "gpio10";
>> +		function = "normal";
>> +		output-high;
>> +		power-source = <0>;
>> +	};
> 
> Does this go to an enable pin of a vreg / switch?

Thanks for comment.
We go to enable the pin of PMIC chip. The pin of PMIC is connecting to 
host-enable pin of USB converter. Need pin of PMIC chip to be high 
level, when USB is as host mode.
> 
> I think we settled on describing such cases as fixed regulators
> (that are always-on for now) - would you remember, +Dmitry?
> 
> The rest looks good.
> 
> Konrad

Re: [PATCH v2 1/2] arm64: dts: qcom: Add support for secondary USB node on QCS615

[Krzysztof Kozlowski]

On 11/12/2024 09:26, Song Xue wrote:
> From: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
> 
> Add support for secondary USB controller and its high-speed phy
> on QCS615.
> 
> Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
> Co-developed-by: Song Xue <quic_songxue@quicinc.com>
> Signed-off-by: Song Xue <quic_songxue@quicinc.com>


Please use subject prefixes matching the subsystem. You can get them for
example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory
your patch is touching. For bindings, the preferred subjects are
explained here:
https://www.kernel.org/doc/html/latest/devicetree/bindings/submitting-patches.html#i-for-patch-submitters



Best regards,
Krzysztof

Re: [PATCH v2 2/2] arm64: dts: qcom: Enable secondary USB controller on QCS615 Ride

[Dmitry Baryshkov]

On Fri, 13 Dec 2024 at 08:59, Song Xue <quic_songxue@quicinc.com> wrote:
>
>
>
> On 12/13/2024 2:14 AM, Konrad Dybcio wrote:
> > On 11.12.2024 9:26 AM, Song Xue wrote:
> >> From: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
> >>
> >> Enable secondary USB controller on QCS615 Ride platform. The secondary
> >> USB controller is made "host", as it is a Type-A port.
> >>
> >> Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
> >> Co-developed-by: Song Xue <quic_songxue@quicinc.com>
> >> Signed-off-by: Song Xue <quic_songxue@quicinc.com>
> >> ---
> >>   arch/arm64/boot/dts/qcom/qcs615-ride.dts | 28 ++++++++++++++++++++++++++++
> >>   1 file changed, 28 insertions(+)
> >>
> >> diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
> >> index f41319ff47b983d771da52775fa78b4385c4e532..26ce0496d13ccbfea392c6d50d9edcab85fbc653 100644
> >> --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts
> >> +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
> >> @@ -203,6 +203,15 @@ &gcc {
> >>               <&sleep_clk>;
> >>   };
> >>
> >> +&pm8150_gpios {
> >> +    usb2_en_state: usb2-en-state {
> >> +            pins = "gpio10";
> >> +            function = "normal";
> >> +            output-high;
> >> +            power-source = <0>;
> >> +    };
> >
> > Does this go to an enable pin of a vreg / switch?
>
> Thanks for comment.
> We go to enable the pin of PMIC chip. The pin of PMIC is connecting to
> host-enable pin of USB converter. Need pin of PMIC chip to be high
> level, when USB is as host mode.

What kind of USB converter are we talking about?

> >
> > I think we settled on describing such cases as fixed regulators
> > (that are always-on for now) - would you remember, +Dmitry?
> >
> > The rest looks good.
> >
> > Konrad
>


-- 
With best wishes
Dmitry

Re: [PATCH v2 1/2] arm64: dts: qcom: Add support for secondary USB node on QCS615

[Song Xue]

On 12/13/2024 3:54 PM, Krzysztof Kozlowski wrote:
> On 11/12/2024 09:26, Song Xue wrote:
>> From: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
>>
>> Add support for secondary USB controller and its high-speed phy
>> on QCS615.
>>
>> Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
>> Co-developed-by: Song Xue <quic_songxue@quicinc.com>
>> Signed-off-by: Song Xue <quic_songxue@quicinc.com>
> 
> 
> Please use subject prefixes matching the subsystem. You can get them for
> example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory
> your patch is touching. For bindings, the preferred subjects are
> explained here:
> https://www.kernel.org/doc/html/latest/devicetree/bindings/submitting-patches.html#i-for-patch-submitters
> 
>
Let me fix in next version.

Thanks
Song >
> Best regards,
> Krzysztof

Re: [PATCH v2 2/2] arm64: dts: qcom: Enable secondary USB controller on QCS615 Ride

[Song Xue]

On 12/13/2024 4:12 PM, Dmitry Baryshkov wrote:
> On Fri, 13 Dec 2024 at 08:59, Song Xue <quic_songxue@quicinc.com> wrote:
>>
>>
>>
>> On 12/13/2024 2:14 AM, Konrad Dybcio wrote:
>>> On 11.12.2024 9:26 AM, Song Xue wrote:
>>>> From: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
>>>>
>>>> Enable secondary USB controller on QCS615 Ride platform. The secondary
>>>> USB controller is made "host", as it is a Type-A port.
>>>>
>>>> Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
>>>> Co-developed-by: Song Xue <quic_songxue@quicinc.com>
>>>> Signed-off-by: Song Xue <quic_songxue@quicinc.com>
>>>> ---
>>>>    arch/arm64/boot/dts/qcom/qcs615-ride.dts | 28 ++++++++++++++++++++++++++++
>>>>    1 file changed, 28 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
>>>> index f41319ff47b983d771da52775fa78b4385c4e532..26ce0496d13ccbfea392c6d50d9edcab85fbc653 100644
>>>> --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts
>>>> +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
>>>> @@ -203,6 +203,15 @@ &gcc {
>>>>                <&sleep_clk>;
>>>>    };
>>>>
>>>> +&pm8150_gpios {
>>>> +    usb2_en_state: usb2-en-state {
>>>> +            pins = "gpio10";
>>>> +            function = "normal";
>>>> +            output-high;
>>>> +            power-source = <0>;
>>>> +    };
>>>
>>> Does this go to an enable pin of a vreg / switch?
>>
>> Thanks for comment.
>> We go to enable the pin of PMIC chip. The pin of PMIC is connecting to
>> host-enable pin of USB converter. Need pin of PMIC chip to be high
>> level, when USB is as host mode.
> 
> What kind of USB converter are we talking about?

It is like USB charging controller and Power Switch.

Thanks
Song
> 
>>>
>>> I think we settled on describing such cases as fixed regulators
>>> (that are always-on for now) - would you remember, +Dmitry?
>>>
>>> The rest looks good.
>>>
>>> Konrad
>>
> 
> 

Re: [PATCH v2 2/2] arm64: dts: qcom: Enable secondary USB controller on QCS615 Ride

[Krishna Kurapati]

On 12/13/2024 10:50 AM, Dmitry Baryshkov wrote:
> On Thu, Dec 12, 2024 at 07:14:22PM +0100, Konrad Dybcio wrote:
>> On 11.12.2024 9:26 AM, Song Xue wrote:
>>> From: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
>>>
>>> Enable secondary USB controller on QCS615 Ride platform. The secondary
>>> USB controller is made "host", as it is a Type-A port.
>>>
>>> Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
>>> Co-developed-by: Song Xue <quic_songxue@quicinc.com>
>>> Signed-off-by: Song Xue <quic_songxue@quicinc.com>
>>> ---
>>>   arch/arm64/boot/dts/qcom/qcs615-ride.dts | 28 ++++++++++++++++++++++++++++
>>>   1 file changed, 28 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
>>> index f41319ff47b983d771da52775fa78b4385c4e532..26ce0496d13ccbfea392c6d50d9edcab85fbc653 100644
>>> --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts
>>> +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
>>> @@ -203,6 +203,15 @@ &gcc {
>>>   		 <&sleep_clk>;
>>>   };
>>>   
>>> +&pm8150_gpios {
>>> +	usb2_en_state: usb2-en-state {
>>> +		pins = "gpio10";
>>> +		function = "normal";
>>> +		output-high;
>>> +		power-source = <0>;
>>> +	};
>>
>> Does this go to an enable pin of a vreg / switch?
>>
>> I think we settled on describing such cases as fixed regulators
>> (that are always-on for now) - would you remember, +Dmitry?
> 
> You are right. Usually it's a fixed regulator. At least there should be
> an explanation for that pin.
> 

Hi Dmitry, Konrad,

  Thanks for the review. You are right. I missed it. There is a switch 
TPS2549IRTERQ1 that is being controlled by GPIO10 (just like in [2]) and 
provides vbus to external peripherals. I am trying to get some 
additional info from internal teams before sending v2.

  I followed [1] instead of [2] by mistake. Will fix this up in v2:

  [1]: 
https://lore.kernel.org/all/20240206114745.1388491-3-quic_kriskura@quicinc.com/
  [2]: 
https://lore.kernel.org/all/20240429162048.2133512-3-quic_kriskura@quicinc.com/

Regards,
Krishna,