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From: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
To: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Yicong Yang <yang.yicong@picoheart.com>,
	 linux-serial <linux-serial@vger.kernel.org>,
	 LKML <linux-kernel@vger.kernel.org>,
	 Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	 Jiri Slaby <jirislaby@kernel.org>,
	geshijian@picoheart.com,  yangyang.8776@picoheart.com,
	yanligen@picoheart.com
Subject: Re: [PATCH] serial: 8250_dw: Prefer SRBR in bogus RX timeout workaround if available
Date: Mon, 29 Jun 2026 18:14:02 +0300 (EEST)	[thread overview]
Message-ID: <60c05ab5-c805-dd78-1b6b-9c78ee7d7148@linux.intel.com> (raw)
In-Reply-To: <akKHoQOr2Vq9CA1Z@ashevche-desk.local>

On Mon, 29 Jun 2026, Andy Shevchenko wrote:

> On Mon, Jun 29, 2026 at 03:55:10PM +0800, Yicong Yang wrote:
> > The DW uart could get into the cases where a bogus RX timeout
> > interrupt is asserted but no available data. This could be
> > workaround by doing a bogus read.
> > 
> > Currently the driver's using the standard RBR (receive buffer
> > register) for this bogus read. However the reading of RBR
> > in this case is allowed to raise a hardware error if vendor
> > choose to implement in this way (our platform). It's also
> > allowed to do the bogus read using SRBR (shadow RBR) for
> > workaround which won't raise the hardware error. So change
> > to use the SRBR to workaround the issue if it's available.
> 
> ...
> 
> >  /* Offsets for the DesignWare specific registers */
> > +#define DW_UART_SRBR_0	0x0c /* Shadow Receive Buffer Register */
> 
> Is this a name per DesignWare databook for UART? I mean that _0 part.

They have 16 consecutive registers for it. There isn't underscore in the 
databook but n is apparently part of the name.

-- 
 i.


  reply	other threads:[~2026-06-29 15:15 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-29  7:55 [PATCH] serial: 8250_dw: Prefer SRBR in bogus RX timeout workaround if available Yicong Yang
2026-06-29 14:56 ` Andy Shevchenko
2026-06-29 15:14   ` Ilpo Järvinen [this message]
2026-06-29 15:16     ` Andy Shevchenko
2026-06-29 15:56 ` Ilpo Järvinen
2026-06-29 16:07   ` Andy Shevchenko
2026-06-30 17:51   ` Yicong Yang
2026-06-30 18:18     ` Ilpo Järvinen
2026-06-30 18:42       ` Yicong Yang
2026-07-01  8:45         ` Ilpo Järvinen

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