[PATCH 1/2] clk: rockchip: add clock ID for usbphy480m_src

[PATCH 1/2] clk: rockchip: add clock ID for usbphy480m_src

[Kever Yang]

There are 3 different parent clock from different usbphy,
all of them are fixed 480MHz, it is not able to auto select
by clock core to the 2nd and the 3rd parent.
For different use case for different board, we may need to
select different usbphy clock out as parent manually.

Add the clock ID for it so that we can use in dts.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 include/dt-bindings/clock/rk3288-cru.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h
index 100a08c..3dcc906 100644
--- a/include/dt-bindings/clock/rk3288-cru.h
+++ b/include/dt-bindings/clock/rk3288-cru.h
@@ -71,6 +71,7 @@
 #define SCLK_HDMI_CEC		110
 #define SCLK_HEVC_CABAC		111
 #define SCLK_HEVC_CORE		112
+#define SCLK_USBPHY480M_SRC	113
 
 #define DCLK_VOP0		190
 #define DCLK_VOP1		191
-- 
1.9.1

[PATCH 2/2] clk: rockchip: use the clock ID for usbphy480m_src

[Kever Yang]

Use the clock ID for usbphy480m_src so that we can find
this clock node in dts.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 drivers/clk/rockchip/clk-rk3288.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index 74f8324..157b60b 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -586,7 +586,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
 	GATE(0, "jtag", "ext_jtag", 0,
 			RK3288_CLKGATE_CON(4), 14, GFLAGS),
 
-	COMPOSITE_NODIV(0, "usbphy480m_src", mux_usbphy480m_p, 0,
+	COMPOSITE_NODIV(SCLK_USBPHY480M_SRC, "usbphy480m_src", mux_usbphy480m_p, 0,
 			RK3288_CLKSEL_CON(13), 11, 2, MFLAGS,
 			RK3288_CLKGATE_CON(5), 14, GFLAGS),
 	COMPOSITE_NODIV(SCLK_HSICPHY480M, "sclk_hsicphy480m", mux_hsicphy480m_p, 0,
-- 
1.9.1

Re: [PATCH 2/2] clk: rockchip: use the clock ID for usbphy480m_src

[Doug Anderson]

Kever,

On Wed, Nov 12, 2014 at 11:22 PM, Kever Yang <kever.yang@rock-chips.com> wrote:
> Use the clock ID for usbphy480m_src so that we can find
> this clock node in dts.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
>  drivers/clk/rockchip/clk-rk3288.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Tested-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Doug Anderson <dianders@chromium.org>

Re: [PATCH 1/2] clk: rockchip: add clock ID for usbphy480m_src

[Doug Anderson]

Kever,

On Wed, Nov 12, 2014 at 11:22 PM, Kever Yang <kever.yang@rock-chips.com> wrote:
> There are 3 different parent clock from different usbphy,
> all of them are fixed 480MHz, it is not able to auto select
> by clock core to the 2nd and the 3rd parent.
> For different use case for different board, we may need to
> select different usbphy clock out as parent manually.
>
> Add the clock ID for it so that we can use in dts.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
>  include/dt-bindings/clock/rk3288-cru.h | 1 +
>  1 file changed, 1 insertion(+)

Aside from clock ID collisions that Heiko can fixup, this looks good to me.

Reviewed-by: Doug Anderson <dianders@chromium.org>

Re: [PATCH 1/2] clk: rockchip: add clock ID for usbphy480m_src

[Heiko Stübner]

Am Donnerstag, 13. November 2014, 15:22:36 schrieb Kever Yang:
> There are 3 different parent clock from different usbphy,
> all of them are fixed 480MHz, it is not able to auto select
> by clock core to the 2nd and the 3rd parent.
> For different use case for different board, we may need to
> select different usbphy clock out as parent manually.
> 
> Add the clock ID for it so that we can use in dts.
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

applied both patches to my tree

The clock-id addition is living in a separate branch, so if you have dts 
updates using this I can share the clock-id branch easily.


Heiko