[PATCH v3 0/3] Devicetree updates for MT8186

[PATCH v3 0/3] Devicetree updates for MT8186

[Rohit Agarwal]

Hi,

Changes in v3:
 - Update some formatting errors in the bindings patch.

Changes in v2:
 - Update the binding to include power domain in only some
   specific variants.

This series updates the DPI node to add power domain and
adds the Mediatek SVS node as well to MT8186.

Thanks,
Rohit.

Rohit Agarwal (3):
  dt-bindings: display: mediatek: dpi: Add power domains
  arm64: dts: mediatek: mt8186: Add power domain for DPI
  arm64: dts: mediatek: mt8186: Add svs node

 .../display/mediatek/mediatek,dpi.yaml        | 17 +++++++++++++++
 arch/arm64/boot/dts/mediatek/mt8186.dtsi      | 21 +++++++++++++++++++
 2 files changed, 38 insertions(+)

-- 
2.46.0.295.g3b9ea8a38a-goog

[PATCH v3 1/3] dt-bindings: display: mediatek: dpi: Add power domains

[Rohit Agarwal]

Add power domain binding to the mediatek DPI controller
for MT8186.
Also, add power domain binding for other SoCs like
MT6795 and MT8173 that already had power domain property.

Signed-off-by: Rohit Agarwal <rohiagar@chromium.org>
---
 .../bindings/display/mediatek/mediatek,dpi.yaml | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
index 5ca7679d5427..3a82aec9021c 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
@@ -62,6 +62,9 @@ properties:
       - const: default
       - const: sleep
 
+  power-domains:
+    maxItems: 1
+
   port:
     $ref: /schemas/graph.yaml#/properties/port
     description:
@@ -76,6 +79,20 @@ required:
   - clock-names
   - port
 
+allOf:
+  - if:
+      not:
+        properties:
+          compatible:
+            contains:
+              enum:
+                - mediatek,mt6795-dpi
+                - mediatek,mt8173-dpi
+                - mediatek,mt8186-dpi
+    then:
+      properties:
+        power-domains: false
+
 additionalProperties: false
 
 examples:
-- 
2.46.0.295.g3b9ea8a38a-goog

Re: [PATCH v3 1/3] dt-bindings: display: mediatek: dpi: Add power domains

[Krzysztof Kozlowski]

On Thu, Aug 22, 2024 at 06:46:48AM +0000, Rohit Agarwal wrote:
> Add power domain binding to the mediatek DPI controller
> for MT8186.
> Also, add power domain binding for other SoCs like
> MT6795 and MT8173 that already had power domain property.
> 
> Signed-off-by: Rohit Agarwal <rohiagar@chromium.org>
> ---
>  .../bindings/display/mediatek/mediatek,dpi.yaml | 17 +++++++++++++++++

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH v3 1/3] dt-bindings: display: mediatek: dpi: Add power domains

[CK Hu (胡俊光)]

Hi, Rohit:

On Thu, 2024-08-22 at 06:46 +0000, Rohit Agarwal wrote:
>  	 
> External email : Please do not click links or open attachments until you have verified the sender or the content.
>  Add power domain binding to the mediatek DPI controller
> for MT8186.
> Also, add power domain binding for other SoCs like
> MT6795 and MT8173 that already had power domain property.

Reviewed-by: CK Hu <ck.hu@mediatek.com>

> 
> Signed-off-by: Rohit Agarwal <rohiagar@chromium.org>
> ---
>  .../bindings/display/mediatek/mediatek,dpi.yaml | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
> index 5ca7679d5427..3a82aec9021c 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
> @@ -62,6 +62,9 @@ properties:
>        - const: default
>        - const: sleep
>  
> +  power-domains:
> +    maxItems: 1
> +
>    port:
>      $ref: /schemas/graph.yaml#/properties/port
>      description:
> @@ -76,6 +79,20 @@ required:
>    - clock-names
>    - port
>  
> +allOf:
> +  - if:
> +      not:
> +        properties:
> +          compatible:
> +            contains:
> +              enum:
> +                - mediatek,mt6795-dpi
> +                - mediatek,mt8173-dpi
> +                - mediatek,mt8186-dpi
> +    then:
> +      properties:
> +        power-domains: false
> +
>  additionalProperties: false
>  
>  examples:
> -- 
> 2.46.0.295.g3b9ea8a38a-goog
> 

[PATCH v3 2/3] arm64: dts: mediatek: mt8186: Add power domain for DPI

[Rohit Agarwal]

Add power domain phandle to the DPI controller in mediatek
mt8186 SoC.

Signed-off-by: Rohit Agarwal <rohiagar@chromium.org>
---
 arch/arm64/boot/dts/mediatek/mt8186.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index 4763ed5dc86c..e27c69ec8bdd 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -1824,6 +1824,7 @@ dpi: dpi@1400a000 {
 			assigned-clocks = <&topckgen CLK_TOP_DPI>;
 			assigned-clock-parents = <&topckgen CLK_TOP_TVDPLL_D2>;
 			interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_LOW 0>;
+			power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
 			status = "disabled";
 
 			port {
-- 
2.46.0.295.g3b9ea8a38a-goog

[PATCH v3 3/3] arm64: dts: mediatek: mt8186: Add svs node

[Rohit Agarwal]

Add clock/irq/efuse setting in svs nodes for mt8186 SoC.

Signed-off-by: Rohit Agarwal <rohiagar@chromium.org>
---
 arch/arm64/boot/dts/mediatek/mt8186.dtsi | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index e27c69ec8bdd..a51f3d8ce745 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -1361,6 +1361,18 @@ spi0: spi@1100a000 {
 			status = "disabled";
 		};
 
+		svs: svs@1100b000 {
+			compatible = "mediatek,mt8186-svs";
+			reg = <0 0x1100b000 0 0x400>;
+			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
+			clock-names = "main";
+			nvmem-cells = <&svs_calibration>, <&lvts_e_data1>;
+			nvmem-cell-names = "svs-calibration-data", "t-calibration-data";
+			resets = <&infracfg_ao MT8186_INFRA_PTP_CTRL_RST>;
+			reset-names = "svs_rst";
+		};
+
 		pwm0: pwm@1100e000 {
 			compatible = "mediatek,mt8186-disp-pwm", "mediatek,mt8183-disp-pwm";
 			reg = <0 0x1100e000 0 0x1000>;
@@ -1676,6 +1688,14 @@ efuse: efuse@11cb0000 {
 			#address-cells = <1>;
 			#size-cells = <1>;
 
+			lvts_e_data1: data@1cc {
+				reg = <0x1cc 0x14>;
+			};
+
+			svs_calibration: calib@550 {
+				reg = <0x550 0x50>;
+			};
+
 			gpu_speedbin: gpu-speedbin@59c {
 				reg = <0x59c 0x4>;
 				bits = <0 3>;
-- 
2.46.0.295.g3b9ea8a38a-goog

Re: [PATCH v3 3/3] arm64: dts: mediatek: mt8186: Add svs node

[Nícolas F. R. A. Prado]

On Thu, Aug 22, 2024 at 06:46:50AM +0000, Rohit Agarwal wrote:
> Add clock/irq/efuse setting in svs nodes for mt8186 SoC.
> 
> Signed-off-by: Rohit Agarwal <rohiagar@chromium.org>
> ---
>  arch/arm64/boot/dts/mediatek/mt8186.dtsi | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> index e27c69ec8bdd..a51f3d8ce745 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> @@ -1361,6 +1361,18 @@ spi0: spi@1100a000 {
>  			status = "disabled";
>  		};
>  
> +		svs: svs@1100b000 {

There's already another node at address 1100b000:

		lvts: thermal-sensor@1100b000

You should set the starting address of the SVS to 1100bc00 and decrease the
iospace for lvts to avoid intersection. See this commit for a similar change on
mt8195:
https://lore.kernel.org/all/20231121125044.78642-21-angelogioacchino.delregno@collabora.com/

Thanks,
Nícolas

Re: [PATCH v3 3/3] arm64: dts: mediatek: mt8186: Add svs node

[Rohit Agarwal]

On 22/08/24 9:36 PM, Nícolas F. R. A. Prado wrote:
> On Thu, Aug 22, 2024 at 06:46:50AM +0000, Rohit Agarwal wrote:
>> Add clock/irq/efuse setting in svs nodes for mt8186 SoC.
>>
>> Signed-off-by: Rohit Agarwal <rohiagar@chromium.org>
>> ---
>>   arch/arm64/boot/dts/mediatek/mt8186.dtsi | 20 ++++++++++++++++++++
>>   1 file changed, 20 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
>> index e27c69ec8bdd..a51f3d8ce745 100644
>> --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
>> +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
>> @@ -1361,6 +1361,18 @@ spi0: spi@1100a000 {
>>   			status = "disabled";
>>   		};
>>   
>> +		svs: svs@1100b000 {
> There's already another node at address 1100b000:
>
> 		lvts: thermal-sensor@1100b000
>
> You should set the starting address of the SVS to 1100bc00 and decrease the
> iospace for lvts to avoid intersection. See this commit for a similar change on
> mt8195:
> https://lore.kernel.org/all/20231121125044.78642-21-angelogioacchino.delregno@collabora.com/
Sure. Will update this according to the reference.

Thanks,
Rohit.