Re: [PATCH] ARM: smp: Fix missing backtrace IPI statics

[Jinjie Ruan <ruanjinjie@huawei.com>]

On 2024/8/2 9:39, Jinjie Ruan wrote:
> 
> 
> On 2024/8/2 0:36, Russell King (Oracle) wrote:
>> On Thu, Aug 01, 2024 at 05:40:22PM +0800, Jinjie Ruan wrote:
>>> It is similar to ARM64 commit 916b93f4e865 ("arm64: smp: Fix missing IPI
>>> statistics"), commit 56afcd3dbd19 ("ARM: Allow IPIs to be handled as normal
>>> interrupts") set CPU_BACKTRACE IPI "IRQ_HIDDEN" flag but not show it in
>>> show_ipi_list(), which cause the interrupt kstat_irqs accounting
>>> is missing in display.
>>
>> I don't see why this needs to be included. If this IPI fires, it means
>> that the kernel has suffered a lockup and is probably not very useful.
>> So the chances of being able to read out from /proc/interrupts a non-
>> zero "CPU backtrace interrupts" figure is highly unlikely.
> 
> It is more of a change than a bug.
> 
> If we reset the arm32 code to before commit 56afcd3dbd19 ("ARM: Allow
> IPIs to be handled as normal interrupts"), the backtrace IPI statics is
> shown ok as below, but after that it is missing:

Sorry, there is some mistake here, the original result has no backtrace
IPI statics.

> 
> / # cat /proc/interrupts
>            CPU0
>  24:          6 GIC-0  34 Level     timer
>  25:        469 GIC-0  29 Level     twd
>  26:         61 GIC-0  75 Edge      virtio0
>  29:          8 GIC-0  44 Level     kmi-pl050
>  30:        118 GIC-0  45 Level     kmi-pl050
>  31:          0 GIC-0  36 Level     rtc-pl031
>  32:          0 GIC-0  41 Level     mmci-pl18x (cmd)
>  33:          0 GIC-0  42 Level     mmci-pl18x (pio)
>  34:          0 GIC-0  92 Level     arm-pmu
>  35:          0 GIC-0  93 Level     arm-pmu
>  36:          0 GIC-0  94 Level     arm-pmu
>  37:          0 GIC-0  95 Level     arm-pmu
>  39:         15 GIC-0  37 Level     uart-pl011
> IPI0:          0  CPU wakeup interrupts
> IPI1:          0  Timer broadcast interrupts
> IPI2:          0  Rescheduling interrupts
> IPI3:          0  Function call interrupts
> IPI4:          0  CPU stop interrupts
> IPI5:          0  IRQ work interrupts
> IPI6:          0  completion interrupts
> IPI7:          0  CPU backtrace interrupts
> 
> 
>>
>> So, I don't see much point to this change.
>>