From: Georgi Djakov <djakov@kernel.org>
To: Sibi Sankar <quic_sibis@quicinc.com>,
andersson@kernel.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org
Cc: agross@kernel.org, conor+dt@kernel.org, quic_rjendra@quicinc.com,
abel.vesa@linaro.org, linux-arm-msm@vger.kernel.org,
linux-pm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, quic_tsoni@quicinc.com,
neil.armstrong@linaro.org
Subject: Re: [PATCH V2 1/2] dt-bindings: interconnect: Add Qualcomm X1E80100 SoC
Date: Wed, 22 Nov 2023 16:52:34 +0200 [thread overview]
Message-ID: <77f39971-6d8a-4e1a-b7e6-bffb5fbf74db@kernel.org> (raw)
In-Reply-To: <20231117103035.25848-2-quic_sibis@quicinc.com>
Hi Sibi,
On 17.11.23 12:30, Sibi Sankar wrote:
> From: Rajendra Nayak <quic_rjendra@quicinc.com>
>
> The Qualcomm X1E80100 SoC has several bus fabrics that could be controlled
> and tuned dynamically according to the bandwidth demand.
>
> Co-developed-by: Abel Vesa <abel.vesa@linaro.org>
> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com>
> Co-developed-by: Sibi Sankar <quic_sibis@quicinc.com>
> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
>
> v2:
> * Update the part number from sc8380xp to x1e80100.
> * Fixup required property ordering [Krzysztof]
> * Pickup Rbs.
>
> .../interconnect/qcom,x1e80100-rpmh.yaml | 83 +++++++
> .../interconnect/qcom,x1e80100-rpmh.h | 207 ++++++++++++++++++
> 2 files changed, 290 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,x1e80100-rpmh.yaml
> create mode 100644 include/dt-bindings/interconnect/qcom,x1e80100-rpmh.h
[..]
> +#define MASTER_AV1_ENC 0
> +#define MASTER_CAMNOC_HF 1
> +#define MASTER_CAMNOC_ICP 2
> +#define MASTER_CAMNOC_SF 3
> +#define MASTER_EVA 4
> +#define MASTER_MDP 5
> +#define MASTER_VIDEO 6
> +#define MASTER_VIDEO_CV_PROC 7
> +#define MASTER_VIDEO_V_PROC 8
> +#define MASTER_CNOC_MNOC_CFG 9
> +#define SLAVE_MNOC_HF_MEM_NOC 10
> +#define SLAVE_MNOC_SF_MEM_NOC 11
> +#define SLAVE_SERVICE_MNOC 12
> +#define MASTER_MDP_DISP 13
> +#define SLAVE_MNOC_HF_MEM_NOC_DISP 14
> +
> +#define MASTER_CDSP_PROC 0
> +#define SLAVE_CDSP_MEM_NOC 1
> +
> +#define MASTER_PCIE_NORTH 0
> +#define MASTER_PCIE_SOUTH 0
This duplicate index looks like a typo?
> +#define SLAVE_ANOC_PCIE_GEM_NOC 3
> +#define MASTER_PCIE_NORTH_PCIE 4
> +#define MASTER_PCIE_SOUTH_PCIE 5
> +#define SLAVE_ANOC_PCIE_GEM_NOC_PCIE 6
[..]
Thanks,
Georgi
next prev parent reply other threads:[~2023-11-22 14:52 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-17 10:30 [PATCH V2 0/2] interconnect: qcom: Introduce interconnect drivers for X1E80100 Sibi Sankar
2023-11-17 10:30 ` [PATCH V2 1/2] dt-bindings: interconnect: Add Qualcomm X1E80100 SoC Sibi Sankar
2023-11-22 14:52 ` Georgi Djakov [this message]
2023-11-23 9:38 ` Sibi Sankar
2023-11-17 10:30 ` [PATCH V2 2/2] interconnect: qcom: Add X1E80100 interconnect provider driver Sibi Sankar
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