From: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
To: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Cc: Rob Clark <robin.clark@oss.qualcomm.com>,
Dmitry Baryshkov <lumag@kernel.org>,
Abhinav Kumar <abhinav.kumar@linux.dev>,
Sean Paul <sean@poorly.run>,
Marijn Suijten <marijn.suijten@somainline.org>,
David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
Jessica Zhang <jesszhan0024@gmail.com>,
linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org,
Abhinav Kumar <quic_abhinavk@quicinc.com>
Subject: Re: [PATCH RESEND v5 01/25] drm/msm/dp: introduce stream_id for each DP panel
Date: Fri, 21 Aug 2026 17:26:47 +0800 [thread overview]
Message-ID: <7db3d44a-7efa-4eb8-a80b-d3b23850063b@oss.qualcomm.com> (raw)
In-Reply-To: <7fjeip5h4jzvsuowvfgmnm6krh7tvulrv3l3laa65quscq2jzp@lor2elvhmhia>
On 7/12/2026 7:11 PM, Dmitry Baryshkov wrote:
> On Mon, Jun 29, 2026 at 10:14:22PM +0800, Yongxing Mou wrote:
>> From: Abhinav Kumar <quic_abhinavk@quicinc.com>
>>
>> With MST, each DP controller can handle multiple streams. There shall be
>> one dp_panel for each stream but the dp_display object shall be shared
>> among them. To represent this abstraction, create a stream_id for each DP
>
> You are not creating IDs.
>
Got it. Will modify it next patchset.
>> panel which shall be dynamically assigned to actual stream IDs by the MST
>> path. For SST, default this to stream 0.
>>
>> In the MST path, panels are dynamically assigned to actual stream IDs at
>> stream enable time by the MST layer.
>>
>> Use the stream ID to control the pixel clock of that respective stream by
>> extending the clock handles and state tracking of the DP pixel clock to
>> an array of max supported streams. The maximum streams currently is 4.
>>
>> Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
>> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
>> ---
>> drivers/gpu/drm/msm/dp/dp_ctrl.c | 67 +++++++++++++++++++++++--------------
>> drivers/gpu/drm/msm/dp/dp_ctrl.h | 2 +-
>> drivers/gpu/drm/msm/dp/dp_display.c | 2 +-
>> drivers/gpu/drm/msm/dp/dp_panel.c | 1 +
>> drivers/gpu/drm/msm/dp/dp_panel.h | 11 ++++++
>> 5 files changed, 55 insertions(+), 28 deletions(-)
>>
>> @@ -2188,38 +2188,39 @@ static bool msm_dp_ctrl_send_phy_test_pattern(struct msm_dp_ctrl_private *ctrl)
>> return success;
>> }
>>
>> -static int msm_dp_ctrl_on_pixel_clk(struct msm_dp_ctrl_private *ctrl, unsigned long pixel_rate)
>> +static int msm_dp_ctrl_on_pixel_clk(struct msm_dp_ctrl_private *ctrl, unsigned long pixel_rate,
>> + enum msm_dp_stream_id stream_id)
>> {
>> int ret;
>>
>> - ret = clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000);
>> + ret = clk_set_rate(ctrl->pixel_clk[stream_id], pixel_rate * 1000);
>> if (ret) {
>> DRM_ERROR("Failed to set pixel clock rate. ret=%d\n", ret);
>> return ret;
>> }
>>
>> - if (WARN_ON_ONCE(ctrl->stream_clks_on))
>> + if (WARN_ON_ONCE(ctrl->stream_clks_on[stream_id]))
>> return 0;
>
> Is it an error, defensive coding, DT mismatch or something else? Why are
> we warning the users _and_ returning success here?
>
This is primarily defensive code. The normal execution flow is not
expected to reach this path, so we only print a warning here.
>>
>> - ret = clk_prepare_enable(ctrl->pixel_clk);
>> + ret = clk_prepare_enable(ctrl->pixel_clk[stream_id]);
>> if (ret) {
>> DRM_ERROR("Failed to start pixel clocks. ret=%d\n", ret);
>> return ret;
>> }
>> - ctrl->stream_clks_on = true;
>> + ctrl->stream_clks_on[stream_id] = true;
>>
>> return ret;
>> }
>>
>
next prev parent reply other threads:[~2026-08-21 9:27 UTC|newest]
Thread overview: 63+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-29 14:14 [PATCH RESEND v5 00/25] drm/msm/dp: Add MST support for MSM chipsets Yongxing Mou
2026-06-29 14:14 ` [PATCH RESEND v5 01/25] drm/msm/dp: introduce stream_id for each DP panel Yongxing Mou
2026-07-12 11:11 ` Dmitry Baryshkov
2026-08-21 9:26 ` Yongxing Mou [this message]
2026-06-29 14:14 ` [PATCH RESEND v5 02/25] drm/msm/dp: introduce max_streams for DP controller MST support Yongxing Mou
2026-07-12 11:17 ` Dmitry Baryshkov
2026-08-26 7:48 ` Yongxing Mou
2026-06-29 14:14 ` [PATCH RESEND v5 03/25] drm/msm/dp: Add support for programming p1/p2/p3 register blocks Yongxing Mou
2026-07-12 11:23 ` Dmitry Baryshkov
2026-08-21 9:27 ` Yongxing Mou
2026-06-29 14:14 ` [PATCH RESEND v5 04/25] drm/msm/dp: use stream_id to change offsets in dp_catalog Yongxing Mou
2026-07-12 11:29 ` Dmitry Baryshkov
2026-06-29 14:14 ` [PATCH RESEND v5 05/25] drm/msm/dp: add support to send ACT packets for MST Yongxing Mou
2026-07-12 13:56 ` Dmitry Baryshkov
2026-08-26 7:48 ` Yongxing Mou
2026-06-29 14:14 ` [PATCH RESEND v5 06/25] drm/msm/dp: Add support to enable MST in mainlink control Yongxing Mou
2026-06-29 14:14 ` [PATCH RESEND v5 07/25] drm/msm/dp: no need to update tu calculation for mst Yongxing Mou
2026-06-29 14:14 ` [PATCH RESEND v5 08/25] drm/msm/dp: Add support for MST channel slot allocation Yongxing Mou
2026-07-12 18:57 ` Dmitry Baryshkov
2026-08-26 7:48 ` Yongxing Mou
2026-06-29 14:14 ` [PATCH RESEND v5 09/25] drm/msm/dp: Add support for sending VCPF packets in DP controller Yongxing Mou
2026-06-29 14:14 ` [PATCH RESEND v5 10/25] drm/msm/dp: Always program MST_FIFO_CONSTANT_FILL for MST use cases Yongxing Mou
2026-06-29 14:14 ` [PATCH RESEND v5 11/25] drm/msm/dp: move link-level teardown from display_disable to display_unprepare Yongxing Mou
2026-07-12 18:20 ` Dmitry Baryshkov
2026-08-25 6:50 ` Yongxing Mou
2026-06-29 14:14 ` [PATCH RESEND v5 12/25] drm/msm/dp: factor out _helper variants of bridge ops accepting a panel Yongxing Mou
2026-07-12 18:43 ` Dmitry Baryshkov
2026-06-29 14:14 ` [PATCH RESEND v5 13/25] drm/msm/dp: replace power_on with active_stream_cnt for dp_display Yongxing Mou
2026-07-12 18:51 ` Dmitry Baryshkov
2026-08-26 7:48 ` Yongxing Mou
2026-06-29 14:14 ` [PATCH RESEND v5 14/25] drm/msm/dp: Mark the SST bridge disconnected when mst is active Yongxing Mou
2026-07-12 21:00 ` Dmitry Baryshkov
2026-08-26 7:49 ` Yongxing Mou
2026-07-12 21:03 ` Dmitry Baryshkov
2026-06-29 14:14 ` [PATCH RESEND v5 15/25] drm/msm/dp: add an API to initialize MST on sink side Yongxing Mou
2026-07-12 21:35 ` Dmitry Baryshkov
2026-08-26 7:48 ` Yongxing Mou
2026-06-29 14:14 ` [PATCH RESEND v5 16/25] drm/msm/dp: add msm_dp_display_get_panel() to initialize DP panel Yongxing Mou
2026-07-12 21:56 ` Dmitry Baryshkov
2026-06-29 14:14 ` [PATCH RESEND v5 17/25] drm/msm/dp: add link_ready to manage link-level operations Yongxing Mou
2026-07-12 23:46 ` Dmitry Baryshkov
2026-08-26 7:49 ` Yongxing Mou
2026-06-29 14:14 ` [PATCH RESEND v5 18/25] drm/msm/dpu: initialize encoders per stream for DP MST Yongxing Mou
2026-07-12 23:55 ` Dmitry Baryshkov
2026-06-29 14:14 ` [PATCH RESEND v5 19/25] drm/msm/dp: initialize dp_mst module for each DP MST controller Yongxing Mou
2026-06-29 14:14 ` [PATCH RESEND v5 20/25] drm/msm/dpu: expose dpu_encoder ops for DP MST reuse Yongxing Mou
2026-07-13 0:01 ` Dmitry Baryshkov
2026-08-26 7:48 ` Yongxing Mou
2026-06-29 14:14 ` [PATCH RESEND v5 21/25] drm/msm/dpu: use msm_dp_get_mst_intf_id() to get the intf id Yongxing Mou
2026-07-13 0:09 ` Dmitry Baryshkov
2026-08-26 7:48 ` Yongxing Mou
2026-06-29 14:14 ` [PATCH RESEND v5 22/25] drm/msm/dp: wire MST helpers into atomic check and commit paths Yongxing Mou
2026-06-29 14:14 ` [PATCH RESEND v5 23/25] drm/msm/dp: add dp_mst_drm to manage DP MST encoder operations Yongxing Mou
2026-07-13 0:40 ` Dmitry Baryshkov
2026-08-26 7:49 ` Yongxing Mou
2026-06-29 14:14 ` [PATCH RESEND v5 24/25] drm/msm/dp: add connector abstraction for DP MST Yongxing Mou
2026-07-13 0:52 ` Dmitry Baryshkov
2026-08-25 6:29 ` Yongxing Mou
2026-06-29 14:14 ` [PATCH RESEND v5 25/25] drm/msm/dp: add HPD callback for dp MST Yongxing Mou
2026-07-13 0:54 ` Dmitry Baryshkov
2026-08-25 6:29 ` Yongxing Mou
2026-07-12 11:04 ` [PATCH RESEND v5 00/25] drm/msm/dp: Add MST support for MSM chipsets Dmitry Baryshkov
2026-08-26 9:17 ` Yongxing Mou
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