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From: "CK Hu (胡俊光)" <ck.hu@mediatek.com>
To: "dmitry.osipenko@collabora.com" <dmitry.osipenko@collabora.com>,
	"Mac Shen (沈俊)" <Mac.Shen@mediatek.com>,
	"granquet@baylibre.com" <granquet@baylibre.com>,
	"chunkuang.hu@kernel.org" <chunkuang.hu@kernel.org>,
	"simona@ffwll.ch" <simona@ffwll.ch>,
	"AngeloGioacchino Del Regno"
	<angelogioacchino.delregno@collabora.com>,
	Project_Global_Chrome_Upstream_Group
	<Project_Global_Chrome_Upstream_Group@mediatek.com>,
	"airlied@gmail.com" <airlied@gmail.com>,
	"msp@baylibre.com" <msp@baylibre.com>,
	"Rex-BC Chen (陳柏辰)" <Rex-BC.Chen@mediatek.com>,
	"p.zabel@pengutronix.de" <p.zabel@pengutronix.de>,
	"matthias.bgg@gmail.com" <matthias.bgg@gmail.com>,
	"Jitao Shi (石记涛)" <jitao.shi@mediatek.com>,
	"Peng Liu (刘鹏)" <Peng.Liu@mediatek.com>,
	"LIANKUN YANG (杨连坤)" <Liankun.Yang@mediatek.com>
Cc: "dri-devel@lists.freedesktop.org"
	<dri-devel@lists.freedesktop.org>,
	"linux-mediatek@lists.infradead.org"
	<linux-mediatek@lists.infradead.org>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 3/3] drm/mediatek: Adjust bandwidth limit for DP
Date: Wed, 12 Feb 2025 08:28:26 +0000	[thread overview]
Message-ID: <80b6840b34e1427f790b6116ec2b672fa41bd8e8.camel@mediatek.com> (raw)
In-Reply-To: <20241025083036.8829-4-liankun.yang@mediatek.com>

Hi, Liankun:

On Fri, 2024-10-25 at 16:28 +0800, Liankun Yang wrote:
> By adjusting the order of link training and relocating it to HPD,
> link training can identify the usability of each lane in the current link.
> 
> It also supports handling signal instability and weakness due to
> environmental issues, enabling the acquisition of a stable bandwidth
> for the current link. Subsequently, DP work can proceed based on
> the actual maximum bandwidth.
> 
> It should training in the hpd event thread.
> Check the mode with lane count and link rate of training.
> 
> Signed-off-by: Liankun Yang <liankun.yang@mediatek.com>
> ---
> - Adjust DP training timing.
> - Adjust parse capabilities timing.
> - Add power on/off for connect/disconnect
> ---
>  drivers/gpu/drm/mediatek/mtk_dp.c | 37 +++++++++++++++++--------------
>  1 file changed, 20 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/mtk_dp.c
> index ae4807823a5c..e87f6f52bcce 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dp.c
> @@ -1873,6 +1873,7 @@ static irqreturn_t mtk_dp_hpd_event_thread(int hpd, void *dev)
>  	struct mtk_dp *mtk_dp = dev;
>  	unsigned long flags;
>  	u32 status;
> +	int ret;
>  
>  	if (mtk_dp->need_debounce && mtk_dp->train_info.cable_plugged_in)
>  		msleep(100);
> @@ -1891,9 +1892,28 @@ static irqreturn_t mtk_dp_hpd_event_thread(int hpd, void *dev)
>  			memset(&mtk_dp->info.audio_cur_cfg, 0,
>  			       sizeof(mtk_dp->info.audio_cur_cfg));
>  
> +			mtk_dp->enabled = false;

If 'mtk_dp->enabled = false' is directly associated to power off aux,
remove 'mtk_dp->enabled = false" in atomic disable.

> +			/* power off aux */
> +			mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE,
> +			       DP_PWR_STATE_BANDGAP_TPLL,
> +			       DP_PWR_STATE_MASK);

I know original atomic disable just power off aux, but why just power off aux not power off panel?

> +
>  			mtk_dp->need_debounce = false;
>  			mod_timer(&mtk_dp->debounce_timer,
>  				  jiffies + msecs_to_jiffies(100) - 1);
> +		} else {
> +			mtk_dp_aux_panel_poweron(mtk_dp, true);
> +
> +			ret = mtk_dp_parse_capabilities(mtk_dp);
> +			if (ret)
> +				drm_err(mtk_dp->drm_dev, "Can't parse capabilities\n");
> +
> +			/* Training */
> +			ret = mtk_dp_training(mtk_dp);
> +			if (ret)
> +				drm_err(mtk_dp->drm_dev, "Training failed, %d\n", ret);
> +
> +			mtk_dp->enabled = true;

You move part code in atomic_enable to here.
It seems that 'mtk_dp->enabled = true' is directly associated to mtk_dp_aux_panel_poweron(),
remove 'mtk_dp->enabled = true' in atomic enable.

Regards,
CK

>  		}
>  	}
>  
> @@ -2060,16 +2080,6 @@ static const struct drm_edid *mtk_dp_edid_read(struct drm_bridge *bridge,
>  
>  	drm_edid = drm_edid_read_ddc(connector, &mtk_dp->aux.ddc);
>  
> -	/*
> -	 * Parse capability here to let atomic_get_input_bus_fmts and
> -	 * mode_valid use the capability to calculate sink bitrates.
> -	 */
> -	if (mtk_dp_parse_capabilities(mtk_dp)) {
> -		drm_err(mtk_dp->drm_dev, "Can't parse capabilities\n");
> -		drm_edid_free(drm_edid);
> -		drm_edid = NULL;
> -	}
> -
>  	if (drm_edid) {
>  		/*
>  		 * FIXME: get rid of drm_edid_raw()
> @@ -2263,13 +2273,6 @@ static void mtk_dp_bridge_atomic_enable(struct drm_bridge *bridge,
>  
>  	mtk_dp_aux_panel_poweron(mtk_dp, true);
>  
> -	/* Training */
> -	ret = mtk_dp_training(mtk_dp);
> -	if (ret) {
> -		drm_err(mtk_dp->drm_dev, "Training failed, %d\n", ret);
> -		goto power_off_aux;
> -	}
> -
>  	ret = mtk_dp_video_config(mtk_dp);
>  	if (ret)
>  		goto power_off_aux;


      reply	other threads:[~2025-02-12  8:28 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-10-25  8:28 [PATCH v2 0/3] Adjust YCbCr422/bandwidth/training for DP Liankun Yang
2024-10-25  8:28 ` [PATCH v2 1/3] drm/mediatek: Fix YCbCr422 color format issue " Liankun Yang
2024-12-30 14:17   ` Chun-Kuang Hu
2024-10-25  8:28 ` [PATCH v2 2/3] drm/mediatek: Fix mode valid issue for dp Liankun Yang
2024-12-30 14:33   ` Chun-Kuang Hu
2024-10-25  8:28 ` [PATCH v2 3/3] drm/mediatek: Adjust bandwidth limit for DP Liankun Yang
2025-02-12  8:28   ` CK Hu (胡俊光) [this message]

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