[PATCH v2 0/3] Adjust YCbCr422/bandwidth/training for DP

[PATCH v2 0/3] Adjust YCbCr422/bandwidth/training for DP

[Liankun Yang]

The change in mode filtering bandwidth calculation method must rely on
DP training at the beginning, and get the current train info to calculate
the bandwidth.

Color format support capability must also rely on DP training time to
get the most reliable link capability and choose which color format to use.

Fixed YCbCr422 problem and bandwidth calculation from color format are
both in the color format category, so they are bound.

In summary, YCbCr 422 and mode valid must rely on DP training timing,
so they are strongly bound.

Liankun Yang (3):
  drm/mediatek: Fix YCbCr422 color format issue for DP
  drm/mediatek: Fix mode valid issue for dp
  drm/mediatek: Adjust bandwidth limit for DP

 drivers/gpu/drm/mediatek/mtk_dp.c | 78 ++++++++++++++++++-------------
 1 file changed, 45 insertions(+), 33 deletions(-)

-- 
2.45.2

[PATCH v2 1/3] drm/mediatek: Fix YCbCr422 color format issue for DP

[Liankun Yang]

Setting up misc0 for Pixel Encoding Format.

According to the definition of YCbCr in spec 1.2a Table 2-96,
0x1 << 1 should be written to the register.

Use switch case to distinguish RGB, YCbCr422,
and unsupported color formats.

Fixes: f70ac097a2cf ("drm/mediatek: Add MT8195 Embedded DisplayPort driver")
Signed-off-by: Liankun Yang <liankun.yang@mediatek.com>
---
Change in V2
- Modify the value written to the register
Per suggestion from the previous thread:
https://patchwork.kernel.org/project/linux-mediatek/patch/20240510021810.19302-1-liankun.yang@mediatek.com/
---
 drivers/gpu/drm/mediatek/mtk_dp.c | 13 ++++++++-----
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/mtk_dp.c
index f0f6f402994a..613e1c842478 100644
--- a/drivers/gpu/drm/mediatek/mtk_dp.c
+++ b/drivers/gpu/drm/mediatek/mtk_dp.c
@@ -460,18 +460,16 @@ static int mtk_dp_set_color_format(struct mtk_dp *mtk_dp,
 				   enum dp_pixelformat color_format)
 {
 	u32 val;
-
-	/* update MISC0 */
-	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3034,
-			   color_format << DP_TEST_COLOR_FORMAT_SHIFT,
-			   DP_TEST_COLOR_FORMAT_MASK);
+	u32 misc0_color;
 
 	switch (color_format) {
 	case DP_PIXELFORMAT_YUV422:
 		val = PIXEL_ENCODE_FORMAT_DP_ENC0_P0_YCBCR422;
+		misc0_color = DP_COLOR_FORMAT_YCbCr422;
 		break;
 	case DP_PIXELFORMAT_RGB:
 		val = PIXEL_ENCODE_FORMAT_DP_ENC0_P0_RGB;
+		misc0_color = DP_COLOR_FORMAT_RGB;
 		break;
 	default:
 		drm_warn(mtk_dp->drm_dev, "Unsupported color format: %d\n",
@@ -479,6 +477,11 @@ static int mtk_dp_set_color_format(struct mtk_dp *mtk_dp,
 		return -EINVAL;
 	}
 
+	/* update MISC0 */
+	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3034,
+			   misc0_color,
+			   DP_TEST_COLOR_FORMAT_MASK);
+
 	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_303C,
 			   val, PIXEL_ENCODE_FORMAT_DP_ENC0_P0_MASK);
 	return 0;
-- 
2.45.2

Re: [PATCH v2 1/3] drm/mediatek: Fix YCbCr422 color format issue for DP

[Chun-Kuang Hu]

Hi, Liankun:

Liankun Yang <liankun.yang@mediatek.com> 於 2024年10月25日 週五 下午4:32寫道：
>
> Setting up misc0 for Pixel Encoding Format.
>
> According to the definition of YCbCr in spec 1.2a Table 2-96,
> 0x1 << 1 should be written to the register.
>
> Use switch case to distinguish RGB, YCbCr422,
> and unsupported color formats.

Applied to mediatek-drm-fixes [1], thanks.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-fixes

Regards,
Chun-Kuang.

>
> Fixes: f70ac097a2cf ("drm/mediatek: Add MT8195 Embedded DisplayPort driver")
> Signed-off-by: Liankun Yang <liankun.yang@mediatek.com>
> ---
> Change in V2
> - Modify the value written to the register
> Per suggestion from the previous thread:
> https://patchwork.kernel.org/project/linux-mediatek/patch/20240510021810.19302-1-liankun.yang@mediatek.com/
> ---
>  drivers/gpu/drm/mediatek/mtk_dp.c | 13 ++++++++-----
>  1 file changed, 8 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/mtk_dp.c
> index f0f6f402994a..613e1c842478 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dp.c
> @@ -460,18 +460,16 @@ static int mtk_dp_set_color_format(struct mtk_dp *mtk_dp,
>                                    enum dp_pixelformat color_format)
>  {
>         u32 val;
> -
> -       /* update MISC0 */
> -       mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3034,
> -                          color_format << DP_TEST_COLOR_FORMAT_SHIFT,
> -                          DP_TEST_COLOR_FORMAT_MASK);
> +       u32 misc0_color;
>
>         switch (color_format) {
>         case DP_PIXELFORMAT_YUV422:
>                 val = PIXEL_ENCODE_FORMAT_DP_ENC0_P0_YCBCR422;
> +               misc0_color = DP_COLOR_FORMAT_YCbCr422;
>                 break;
>         case DP_PIXELFORMAT_RGB:
>                 val = PIXEL_ENCODE_FORMAT_DP_ENC0_P0_RGB;
> +               misc0_color = DP_COLOR_FORMAT_RGB;
>                 break;
>         default:
>                 drm_warn(mtk_dp->drm_dev, "Unsupported color format: %d\n",
> @@ -479,6 +477,11 @@ static int mtk_dp_set_color_format(struct mtk_dp *mtk_dp,
>                 return -EINVAL;
>         }
>
> +       /* update MISC0 */
> +       mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3034,
> +                          misc0_color,
> +                          DP_TEST_COLOR_FORMAT_MASK);
> +
>         mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_303C,
>                            val, PIXEL_ENCODE_FORMAT_DP_ENC0_P0_MASK);
>         return 0;
> --
> 2.45.2
>

[PATCH v2 2/3] drm/mediatek: Fix mode valid issue for dp

[Liankun Yang]

Fix dp mode valid issue to avoid abnormal display of limit state.

After DP passes link training, it can express the lane count of the
current link status is good. Calculate the maximum bandwidth supported
by DP using the current lane count.

The color format will select the best one based on the bandwidth
requirements of the current timing mode. If the current timing mode
uses RGB and meets the DP link bandwidth requirements, RGB will be used.

If the timing mode uses RGB but does not meet the DP link bandwidthi
requirements, it will continue to check whether YUV422 meetsi
the DP link bandwidth.

FEC overhead is approximately 2.4% from DP 1.4a spec 2.2.1.4.2.
The down-spread amplitude shall either be disabled (0.0%) or up
to 0.5% from 1.4a 3.5.2.6. Add up to approximately 3% total overhead.

Because rate is already divided by 10,
mode->clock does not need to be multiplied by 10.

Fixes: f70ac097a2cf ("drm/mediatek: Add MT8195 Embedded DisplayPort driver")
Signed-off-by: Liankun Yang <liankun.yang@mediatek.com>
---
Change in V2:
- Adjust the writing style.
- Add instructions.
---
 drivers/gpu/drm/mediatek/mtk_dp.c | 28 +++++++++++++++++-----------
 1 file changed, 17 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/mtk_dp.c
index 613e1c842478..ae4807823a5c 100644
--- a/drivers/gpu/drm/mediatek/mtk_dp.c
+++ b/drivers/gpu/drm/mediatek/mtk_dp.c
@@ -2328,12 +2328,19 @@ mtk_dp_bridge_mode_valid(struct drm_bridge *bridge,
 {
 	struct mtk_dp *mtk_dp = mtk_dp_from_bridge(bridge);
 	u32 bpp = info->color_formats & DRM_COLOR_FORMAT_YCBCR422 ? 16 : 24;
-	u32 rate = min_t(u32, drm_dp_max_link_rate(mtk_dp->rx_cap) *
-			      drm_dp_max_lane_count(mtk_dp->rx_cap),
-			 drm_dp_bw_code_to_link_rate(mtk_dp->max_linkrate) *
-			 mtk_dp->max_lanes);
+	u32 lane_count_min = mtk_dp->train_info.lane_count;
+	u32 rate = drm_dp_bw_code_to_link_rate(mtk_dp->train_info.link_rate) *
+			 lane_count_min;
 
-	if (rate < mode->clock * bpp / 8)
+	/*
+	 *FEC overhead is approximately 2.4% from DP 1.4a spec 2.2.1.4.2.
+	 *The down-spread amplitude shall either be disabled (0.0%) or up
+	 *to 0.5% from 1.4a 3.5.2.6. Add up to approximately 3% total overhead.
+	 *
+	 *Because rate is already divided by 10,
+	 *mode->clock does not need to be multiplied by 10
+	 */
+	if ((rate * 97 / 100) < (mode->clock * bpp / 8))
 		return MODE_CLOCK_HIGH;
 
 	return MODE_OK;
@@ -2374,10 +2381,9 @@ static u32 *mtk_dp_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
 	struct drm_display_mode *mode = &crtc_state->adjusted_mode;
 	struct drm_display_info *display_info =
 		&conn_state->connector->display_info;
-	u32 rate = min_t(u32, drm_dp_max_link_rate(mtk_dp->rx_cap) *
-			      drm_dp_max_lane_count(mtk_dp->rx_cap),
-			 drm_dp_bw_code_to_link_rate(mtk_dp->max_linkrate) *
-			 mtk_dp->max_lanes);
+	u32 lane_count_min = mtk_dp->train_info.lane_count;
+	u32 rate = drm_dp_bw_code_to_link_rate(mtk_dp->train_info.link_rate) *
+			 lane_count_min;
 
 	*num_input_fmts = 0;
 
@@ -2386,8 +2392,8 @@ static u32 *mtk_dp_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
 	 * datarate of YUV422 and sink device supports YUV422, we output YUV422
 	 * format. Use this condition, we can support more resolution.
 	 */
-	if ((rate < (mode->clock * 24 / 8)) &&
-	    (rate > (mode->clock * 16 / 8)) &&
+	if (((rate * 97 / 100) < (mode->clock * 24 / 8)) &&
+	    ((rate * 97 / 100) > (mode->clock * 16 / 8)) &&
 	    (display_info->color_formats & DRM_COLOR_FORMAT_YCBCR422)) {
 		input_fmts = kcalloc(1, sizeof(*input_fmts), GFP_KERNEL);
 		if (!input_fmts)
-- 
2.45.2

Re: [PATCH v2 2/3] drm/mediatek: Fix mode valid issue for dp

[Chun-Kuang Hu]

Hi, Liankun:

Liankun Yang <liankun.yang@mediatek.com> 於 2024年10月25日 週五 下午4:31寫道：
>
> Fix dp mode valid issue to avoid abnormal display of limit state.
>
> After DP passes link training, it can express the lane count of the
> current link status is good. Calculate the maximum bandwidth supported
> by DP using the current lane count.
>
> The color format will select the best one based on the bandwidth
> requirements of the current timing mode. If the current timing mode
> uses RGB and meets the DP link bandwidth requirements, RGB will be used.
>
> If the timing mode uses RGB but does not meet the DP link bandwidthi
> requirements, it will continue to check whether YUV422 meetsi
> the DP link bandwidth.
>
> FEC overhead is approximately 2.4% from DP 1.4a spec 2.2.1.4.2.
> The down-spread amplitude shall either be disabled (0.0%) or up
> to 0.5% from 1.4a 3.5.2.6. Add up to approximately 3% total overhead.
>
> Because rate is already divided by 10,
> mode->clock does not need to be multiplied by 10.

Applied to mediatek-drm-fixes [1], thanks.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-fixes

Regards,
Chun-Kuang.

>
> Fixes: f70ac097a2cf ("drm/mediatek: Add MT8195 Embedded DisplayPort driver")
> Signed-off-by: Liankun Yang <liankun.yang@mediatek.com>
> ---
> Change in V2:
> - Adjust the writing style.
> - Add instructions.
> ---
>  drivers/gpu/drm/mediatek/mtk_dp.c | 28 +++++++++++++++++-----------
>  1 file changed, 17 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/mtk_dp.c
> index 613e1c842478..ae4807823a5c 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dp.c
> @@ -2328,12 +2328,19 @@ mtk_dp_bridge_mode_valid(struct drm_bridge *bridge,
>  {
>         struct mtk_dp *mtk_dp = mtk_dp_from_bridge(bridge);
>         u32 bpp = info->color_formats & DRM_COLOR_FORMAT_YCBCR422 ? 16 : 24;
> -       u32 rate = min_t(u32, drm_dp_max_link_rate(mtk_dp->rx_cap) *
> -                             drm_dp_max_lane_count(mtk_dp->rx_cap),
> -                        drm_dp_bw_code_to_link_rate(mtk_dp->max_linkrate) *
> -                        mtk_dp->max_lanes);
> +       u32 lane_count_min = mtk_dp->train_info.lane_count;
> +       u32 rate = drm_dp_bw_code_to_link_rate(mtk_dp->train_info.link_rate) *
> +                        lane_count_min;
>
> -       if (rate < mode->clock * bpp / 8)
> +       /*
> +        *FEC overhead is approximately 2.4% from DP 1.4a spec 2.2.1.4.2.
> +        *The down-spread amplitude shall either be disabled (0.0%) or up
> +        *to 0.5% from 1.4a 3.5.2.6. Add up to approximately 3% total overhead.
> +        *
> +        *Because rate is already divided by 10,
> +        *mode->clock does not need to be multiplied by 10
> +        */
> +       if ((rate * 97 / 100) < (mode->clock * bpp / 8))
>                 return MODE_CLOCK_HIGH;
>
>         return MODE_OK;
> @@ -2374,10 +2381,9 @@ static u32 *mtk_dp_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
>         struct drm_display_mode *mode = &crtc_state->adjusted_mode;
>         struct drm_display_info *display_info =
>                 &conn_state->connector->display_info;
> -       u32 rate = min_t(u32, drm_dp_max_link_rate(mtk_dp->rx_cap) *
> -                             drm_dp_max_lane_count(mtk_dp->rx_cap),
> -                        drm_dp_bw_code_to_link_rate(mtk_dp->max_linkrate) *
> -                        mtk_dp->max_lanes);
> +       u32 lane_count_min = mtk_dp->train_info.lane_count;
> +       u32 rate = drm_dp_bw_code_to_link_rate(mtk_dp->train_info.link_rate) *
> +                        lane_count_min;
>
>         *num_input_fmts = 0;
>
> @@ -2386,8 +2392,8 @@ static u32 *mtk_dp_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
>          * datarate of YUV422 and sink device supports YUV422, we output YUV422
>          * format. Use this condition, we can support more resolution.
>          */
> -       if ((rate < (mode->clock * 24 / 8)) &&
> -           (rate > (mode->clock * 16 / 8)) &&
> +       if (((rate * 97 / 100) < (mode->clock * 24 / 8)) &&
> +           ((rate * 97 / 100) > (mode->clock * 16 / 8)) &&
>             (display_info->color_formats & DRM_COLOR_FORMAT_YCBCR422)) {
>                 input_fmts = kcalloc(1, sizeof(*input_fmts), GFP_KERNEL);
>                 if (!input_fmts)
> --
> 2.45.2
>

[PATCH v2 3/3] drm/mediatek: Adjust bandwidth limit for DP

[Liankun Yang]

By adjusting the order of link training and relocating it to HPD,
link training can identify the usability of each lane in the current link.

It also supports handling signal instability and weakness due to
environmental issues, enabling the acquisition of a stable bandwidth
for the current link. Subsequently, DP work can proceed based on
the actual maximum bandwidth.

It should training in the hpd event thread.
Check the mode with lane count and link rate of training.

Signed-off-by: Liankun Yang <liankun.yang@mediatek.com>
---
- Adjust DP training timing.
- Adjust parse capabilities timing.
- Add power on/off for connect/disconnect
---
 drivers/gpu/drm/mediatek/mtk_dp.c | 37 +++++++++++++++++--------------
 1 file changed, 20 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/mtk_dp.c
index ae4807823a5c..e87f6f52bcce 100644
--- a/drivers/gpu/drm/mediatek/mtk_dp.c
+++ b/drivers/gpu/drm/mediatek/mtk_dp.c
@@ -1873,6 +1873,7 @@ static irqreturn_t mtk_dp_hpd_event_thread(int hpd, void *dev)
 	struct mtk_dp *mtk_dp = dev;
 	unsigned long flags;
 	u32 status;
+	int ret;
 
 	if (mtk_dp->need_debounce && mtk_dp->train_info.cable_plugged_in)
 		msleep(100);
@@ -1891,9 +1892,28 @@ static irqreturn_t mtk_dp_hpd_event_thread(int hpd, void *dev)
 			memset(&mtk_dp->info.audio_cur_cfg, 0,
 			       sizeof(mtk_dp->info.audio_cur_cfg));
 
+			mtk_dp->enabled = false;
+			/* power off aux */
+			mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE,
+			       DP_PWR_STATE_BANDGAP_TPLL,
+			       DP_PWR_STATE_MASK);
+
 			mtk_dp->need_debounce = false;
 			mod_timer(&mtk_dp->debounce_timer,
 				  jiffies + msecs_to_jiffies(100) - 1);
+		} else {
+			mtk_dp_aux_panel_poweron(mtk_dp, true);
+
+			ret = mtk_dp_parse_capabilities(mtk_dp);
+			if (ret)
+				drm_err(mtk_dp->drm_dev, "Can't parse capabilities\n");
+
+			/* Training */
+			ret = mtk_dp_training(mtk_dp);
+			if (ret)
+				drm_err(mtk_dp->drm_dev, "Training failed, %d\n", ret);
+
+			mtk_dp->enabled = true;
 		}
 	}
 
@@ -2060,16 +2080,6 @@ static const struct drm_edid *mtk_dp_edid_read(struct drm_bridge *bridge,
 
 	drm_edid = drm_edid_read_ddc(connector, &mtk_dp->aux.ddc);
 
-	/*
-	 * Parse capability here to let atomic_get_input_bus_fmts and
-	 * mode_valid use the capability to calculate sink bitrates.
-	 */
-	if (mtk_dp_parse_capabilities(mtk_dp)) {
-		drm_err(mtk_dp->drm_dev, "Can't parse capabilities\n");
-		drm_edid_free(drm_edid);
-		drm_edid = NULL;
-	}
-
 	if (drm_edid) {
 		/*
 		 * FIXME: get rid of drm_edid_raw()
@@ -2263,13 +2273,6 @@ static void mtk_dp_bridge_atomic_enable(struct drm_bridge *bridge,
 
 	mtk_dp_aux_panel_poweron(mtk_dp, true);
 
-	/* Training */
-	ret = mtk_dp_training(mtk_dp);
-	if (ret) {
-		drm_err(mtk_dp->drm_dev, "Training failed, %d\n", ret);
-		goto power_off_aux;
-	}
-
 	ret = mtk_dp_video_config(mtk_dp);
 	if (ret)
 		goto power_off_aux;
-- 
2.45.2

Re: [PATCH v2 3/3] drm/mediatek: Adjust bandwidth limit for DP

[CK Hu (胡俊光)]

Hi, Liankun:

On Fri, 2024-10-25 at 16:28 +0800, Liankun Yang wrote:
> By adjusting the order of link training and relocating it to HPD,
> link training can identify the usability of each lane in the current link.
> 
> It also supports handling signal instability and weakness due to
> environmental issues, enabling the acquisition of a stable bandwidth
> for the current link. Subsequently, DP work can proceed based on
> the actual maximum bandwidth.
> 
> It should training in the hpd event thread.
> Check the mode with lane count and link rate of training.
> 
> Signed-off-by: Liankun Yang <liankun.yang@mediatek.com>
> ---
> - Adjust DP training timing.
> - Adjust parse capabilities timing.
> - Add power on/off for connect/disconnect
> ---
>  drivers/gpu/drm/mediatek/mtk_dp.c | 37 +++++++++++++++++--------------
>  1 file changed, 20 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/mtk_dp.c
> index ae4807823a5c..e87f6f52bcce 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dp.c
> @@ -1873,6 +1873,7 @@ static irqreturn_t mtk_dp_hpd_event_thread(int hpd, void *dev)
>  	struct mtk_dp *mtk_dp = dev;
>  	unsigned long flags;
>  	u32 status;
> +	int ret;
>  
>  	if (mtk_dp->need_debounce && mtk_dp->train_info.cable_plugged_in)
>  		msleep(100);
> @@ -1891,9 +1892,28 @@ static irqreturn_t mtk_dp_hpd_event_thread(int hpd, void *dev)
>  			memset(&mtk_dp->info.audio_cur_cfg, 0,
>  			       sizeof(mtk_dp->info.audio_cur_cfg));
>  
> +			mtk_dp->enabled = false;

If 'mtk_dp->enabled = false' is directly associated to power off aux,
remove 'mtk_dp->enabled = false" in atomic disable.

> +			/* power off aux */
> +			mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE,
> +			       DP_PWR_STATE_BANDGAP_TPLL,
> +			       DP_PWR_STATE_MASK);

I know original atomic disable just power off aux, but why just power off aux not power off panel?

> +
>  			mtk_dp->need_debounce = false;
>  			mod_timer(&mtk_dp->debounce_timer,
>  				  jiffies + msecs_to_jiffies(100) - 1);
> +		} else {
> +			mtk_dp_aux_panel_poweron(mtk_dp, true);
> +
> +			ret = mtk_dp_parse_capabilities(mtk_dp);
> +			if (ret)
> +				drm_err(mtk_dp->drm_dev, "Can't parse capabilities\n");
> +
> +			/* Training */
> +			ret = mtk_dp_training(mtk_dp);
> +			if (ret)
> +				drm_err(mtk_dp->drm_dev, "Training failed, %d\n", ret);
> +
> +			mtk_dp->enabled = true;

You move part code in atomic_enable to here.
It seems that 'mtk_dp->enabled = true' is directly associated to mtk_dp_aux_panel_poweron(),
remove 'mtk_dp->enabled = true' in atomic enable.

Regards,
CK

>  		}
>  	}
>  
> @@ -2060,16 +2080,6 @@ static const struct drm_edid *mtk_dp_edid_read(struct drm_bridge *bridge,
>  
>  	drm_edid = drm_edid_read_ddc(connector, &mtk_dp->aux.ddc);
>  
> -	/*
> -	 * Parse capability here to let atomic_get_input_bus_fmts and
> -	 * mode_valid use the capability to calculate sink bitrates.
> -	 */
> -	if (mtk_dp_parse_capabilities(mtk_dp)) {
> -		drm_err(mtk_dp->drm_dev, "Can't parse capabilities\n");
> -		drm_edid_free(drm_edid);
> -		drm_edid = NULL;
> -	}
> -
>  	if (drm_edid) {
>  		/*
>  		 * FIXME: get rid of drm_edid_raw()
> @@ -2263,13 +2273,6 @@ static void mtk_dp_bridge_atomic_enable(struct drm_bridge *bridge,
>  
>  	mtk_dp_aux_panel_poweron(mtk_dp, true);
>  
> -	/* Training */
> -	ret = mtk_dp_training(mtk_dp);
> -	if (ret) {
> -		drm_err(mtk_dp->drm_dev, "Training failed, %d\n", ret);
> -		goto power_off_aux;
> -	}
> -
>  	ret = mtk_dp_video_config(mtk_dp);
>  	if (ret)
>  		goto power_off_aux;