[PATCH v3 0/5] Add bootph-all property for J7 boards

[PATCH v3 0/5] Add bootph-all property for J7 boards

[Manorit Chawdhry]

The idea of this series is to add bootph-all and bootph-pre-ram property
in all the leaf nodes wherever required and cleanup any other places where
bootph-all/bootph-pre-ram exist in the parent nodes as well.

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
---
Changes in v3:
* Vignesh
- Remove bootph-all from sms/dmsc node

- Remove bootph-all j7200 from main_uart2 and mcu_cpsw
- Link to v2: https://lore.kernel.org/r/20240705-b4-upstream-bootph-all-v2-0-9007681ed7d8@ti.com

---
Manorit Chawdhry (5):
      arm64: dts: ti: k3-j721s2*: Add bootph-* properties
      arm64: dts: ti: k3-j784s4*: Remove bootph properties from parent nodes
      arm64: dts: ti: k3-am68*: Add bootph-* properties
      arm64: dts: ti: k3-j721e*: Add bootph-* properties
      arm64: dts: ti: k3-j7200*: Add bootph-* properties

 arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts     | 10 ++++++++++
 arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi           |  2 ++
 .../arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 20 ++++++++++++++++++++
 arch/arm64/boot/dts/ti/k3-j7200-main.dtsi            |  2 ++
 arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi      | 10 ++++++++++
 arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi          |  7 +++++++
 .../arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 20 ++++++++++++++++++++
 arch/arm64/boot/dts/ti/k3-j721e-main.dtsi            |  2 ++
 arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi      |  9 +++++++++
 arch/arm64/boot/dts/ti/k3-j721e-sk.dts               | 18 ++++++++++++++++++
 arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi          |  5 +++++
 .../boot/dts/ti/k3-j721s2-common-proc-board.dts      | 14 ++++++++++++++
 arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi           |  2 ++
 arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi     | 11 +++++++++++
 arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi         |  2 ++
 arch/arm64/boot/dts/ti/k3-j784s4-evm.dts             |  9 +--------
 arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi     |  8 ++++----
 17 files changed, 139 insertions(+), 12 deletions(-)
---
base-commit: cd19ac2f903276b820f5d0d89de0c896c27036ed
change-id: 20240430-b4-upstream-bootph-all-8d47b72bc0fd

Best regards,
-- 
Manorit Chawdhry <m-chawdhry@ti.com>

[PATCH v3 1/5] arm64: dts: ti: k3-j721s2*: Add bootph-* properties

[Manorit Chawdhry]

Adds bootph-* properties to the leaf nodes to enable U-boot to
utilise them.

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts | 14 ++++++++++++++
 arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi             |  2 ++
 arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi       | 11 +++++++++++
 arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi           |  2 ++
 4 files changed, 29 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
index c5a0b7cbb14f..6ce14f9e087b 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
@@ -138,6 +138,7 @@ J721S2_IOPAD(0x044, PIN_OUTPUT, 14) /* (Y26) MCASP0_AXR1.UART8_RTSn */
 			J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */
 			J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */
 		>;
+		bootph-all;
 	};
 
 	main_i2c3_pins_default: main-i2c3-default-pins {
@@ -165,6 +166,7 @@ J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */
 			J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */
 			J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */
 		>;
+		bootph-all;
 	};
 
 	vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
@@ -177,6 +179,7 @@ main_usbss0_pins_default: main-usbss0-default-pins {
 		pinctrl-single,pins = <
 			J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */
 		>;
+		bootph-all;
 	};
 
 	main_mcan3_pins_default: main-mcan3-default-pins {
@@ -200,6 +203,7 @@ wkup_uart0_pins_default: wkup-uart0-default-pins {
 			J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */
 			J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */
 		>;
+		bootph-all;
 	};
 
 	mcu_uart0_pins_default: mcu-uart0-default-pins {
@@ -209,6 +213,7 @@ J721S2_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (D25) WKUP_GPIO0_15.MCU_UART0_RTSn */
 			J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */
 			J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */
 		>;
+		bootph-all;
 	};
 
 	mcu_cpsw_pins_default: mcu-cpsw-default-pins {
@@ -301,6 +306,7 @@ J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */
 			J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */
 			J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */
 		>;
+		bootph-all;
 	};
 };
 
@@ -316,12 +322,14 @@ &wkup_uart0 {
 	status = "reserved";
 	pinctrl-names = "default";
 	pinctrl-0 = <&wkup_uart0_pins_default>;
+	bootph-all;
 };
 
 &mcu_uart0 {
 	status = "okay";
 	pinctrl-names = "default";
 	pinctrl-0 = <&mcu_uart0_pins_default>;
+	bootph-all;
 };
 
 &main_uart8 {
@@ -330,6 +338,7 @@ &main_uart8 {
 	pinctrl-0 = <&main_uart8_pins_default>;
 	/* Shared with TFA on this platform */
 	power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>;
+	bootph-all;
 };
 
 &main_i2c0 {
@@ -385,6 +394,7 @@ &main_sdhci0 {
 	non-removable;
 	ti,driver-strength-ohm = <50>;
 	disable-wp;
+	bootph-all;
 };
 
 &main_sdhci1 {
@@ -395,6 +405,7 @@ &main_sdhci1 {
 	disable-wp;
 	vmmc-supply = <&vdd_mmc1>;
 	vqmmc-supply = <&vdd_sd_dv>;
+	bootph-all;
 };
 
 &mcu_cpsw {
@@ -446,11 +457,13 @@ &usbss0 {
 	pinctrl-names = "default";
 	ti,vbus-divider;
 	ti,usb2-only;
+	bootph-all;
 };
 
 &usb0 {
 	dr_mode = "otg";
 	maximum-speed = "high-speed";
+	bootph-all;
 };
 
 &ospi1 {
@@ -469,6 +482,7 @@ flash@0 {
 		cdns,tchsh-ns = <60>;
 		cdns,tslch-ns = <60>;
 		cdns,read-delay = <2>;
+		bootph-all;
 	};
 };
 
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index 9ed6949b40e9..0ea6817de65c 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -816,6 +816,7 @@ secure_proxy_main: mailbox@32c00000 {
 			      <0x00 0x32800000 0x00 0x100000>;
 			interrupt-names = "rx_011";
 			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+			bootph-all;
 		};
 
 		hwspinlock: spinlock@30e00000 {
@@ -1225,6 +1226,7 @@ usb0: usb@6000000 {
 			interrupt-names = "host", "peripheral", "otg";
 			maximum-speed = "super-speed";
 			dr_mode = "otg";
+			bootph-all;
 		};
 	};
 
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
index 8feb42c89e47..8345313f8d94 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
@@ -21,16 +21,19 @@ sms: system-controller@44083000 {
 		k3_pds: power-controller {
 			compatible = "ti,sci-pm-domain";
 			#power-domain-cells = <2>;
+			bootph-all;
 		};
 
 		k3_clks: clock-controller {
 			compatible = "ti,k2g-sci-clk";
 			#clock-cells = <2>;
+			bootph-all;
 		};
 
 		k3_reset: reset-controller {
 			compatible = "ti,sci-reset";
 			#reset-cells = <2>;
+			bootph-all;
 		};
 	};
 
@@ -43,6 +46,7 @@ wkup_conf: bus@43000000 {
 		chipid: chipid@14 {
 			compatible = "ti,am654-chipid";
 			reg = <0x14 0x4>;
+			bootph-all;
 		};
 	};
 
@@ -59,6 +63,7 @@ secure_proxy_sa3: mailbox@43600000 {
 		 * firmware on non-MPU processors
 		 */
 		status = "disabled";
+		bootph-pre-ram;
 	};
 
 	mcu_ram: sram@41c00000 {
@@ -170,6 +175,7 @@ mcu_timer0: timer@40400000 {
 		ti,timer-pwm;
 		/* Non-MPU Firmware usage */
 		status = "reserved";
+		bootph-pre-ram;
 	};
 
 	mcu_timer1: timer@40410000 {
@@ -362,6 +368,7 @@ wkup_i2c0: i2c@42120000 {
 		clock-names = "fck";
 		power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>;
 		status = "disabled";
+		bootph-all;
 	};
 
 	mcu_i2c0: i2c@40b00000 {
@@ -474,6 +481,7 @@ mcu_ringacc: ringacc@2b800000 {
 			ti,sci = <&sms>;
 			ti,sci-dev-id = <272>;
 			msi-parent = <&main_udmass_inta>;
+			bootph-all;
 		};
 
 		mcu_udmap: dma-controller@285c0000 {
@@ -497,6 +505,7 @@ mcu_udmap: dma-controller@285c0000 {
 			ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
 						<0x0b>; /* RX_HCHAN */
 			ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
+			bootph-all;
 		};
 	};
 
@@ -513,6 +522,7 @@ secure_proxy_mcu: mailbox@2a480000 {
 		 * firmware on non-MPU processors
 		 */
 		status = "disabled";
+		bootph-pre-ram;
 	};
 
 	mcu_cpsw: ethernet@46000000 {
@@ -667,6 +677,7 @@ wkup_vtm0: temperature-sensor@42040000 {
 		      <0x00 0x42050000 0x0 0x350>;
 		power-domains = <&k3_pds 180 TI_SCI_PD_SHARED>;
 		#thermal-sensor-cells = <1>;
+		bootph-pre-ram;
 	};
 
 	mcu_r5fss0: r5fss@41000000 {
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
index 82aacc01e8fe..dfcc223809e7 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
@@ -170,6 +170,7 @@ J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */
 			J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */
 			J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */
 		>;
+		bootph-all;
 	};
 };
 
@@ -445,6 +446,7 @@ flash@0 {
 		cdns,tchsh-ns = <60>;
 		cdns,tslch-ns = <60>;
 		cdns,read-delay = <4>;
+		bootph-all;
 	};
 };
 

-- 
2.45.1

[PATCH v3 2/5] arm64: dts: ti: k3-j784s4*: Remove bootph properties from parent nodes

[Manorit Chawdhry]

Removes bootph-* properties from parent nodes and aligns the bootph-* to
other u-boot.dtsi

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j784s4-evm.dts         | 9 +--------
 arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 8 ++++----
 2 files changed, 5 insertions(+), 12 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
index ffa38f41679d..311844490027 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
@@ -461,7 +461,6 @@ J784S4_IOPAD(0x078, PIN_OUTPUT, 1) /* (AH37) MCAN2_RX.AUDIO_EXT_REFCLK1 */
 };
 
 &wkup_pmx2 {
-	bootph-all;
 	wkup_uart0_pins_default: wkup-uart0-default-pins {
 		bootph-all;
 		pinctrl-single,pins = <
@@ -577,7 +576,6 @@ J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 7)
 };
 
 &wkup_pmx0 {
-	bootph-all;
 	mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
 		bootph-all;
 		pinctrl-single,pins = <
@@ -597,7 +595,6 @@ J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */
 };
 
 &wkup_pmx1 {
-	bootph-all;
 	mcu_fss0_ospi0_1_pins_default: mcu-fss0-ospi0-1-default-pins {
 		bootph-all;
 		pinctrl-single,pins = <
@@ -668,6 +665,7 @@ bucka12: buck12 {
 				regulator-max-microvolt = <1100000>;
 				regulator-boot-on;
 				regulator-always-on;
+				bootph-pre-ram;
 			};
 
 			bucka3: buck3 {
@@ -769,18 +767,15 @@ &ufs_wrapper {
 };
 
 &fss {
-	bootph-all;
 	status = "okay";
 };
 
 &ospi0 {
-	bootph-all;
 	status = "okay";
 	pinctrl-names = "default";
 	pinctrl-0 = <&mcu_fss0_ospi0_pins_default>, <&mcu_fss0_ospi0_1_pins_default>;
 
 	flash@0 {
-		bootph-all;
 		compatible = "jedec,spi-nor";
 		reg = <0x0>;
 		spi-tx-bus-width = <8>;
@@ -837,13 +832,11 @@ partition@3fc0000 {
 };
 
 &ospi1 {
-	bootph-all;
 	status = "okay";
 	pinctrl-names = "default";
 	pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
 
 	flash@0 {
-		bootph-all;
 		compatible = "jedec,spi-nor";
 		reg = <0x0>;
 		spi-tx-bus-width = <1>;
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
index f3a6ed1c979d..3f89277e3c2c 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
@@ -7,7 +7,6 @@
 
 &cbass_mcu_wakeup {
 	sms: system-controller@44083000 {
-		bootph-all;
 		compatible = "ti,k2g-sci";
 		ti,host-id = <12>;
 
@@ -39,7 +38,6 @@ k3_reset: reset-controller {
 	};
 
 	wkup_conf: bus@43000000 {
-		bootph-all;
 		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -65,6 +63,7 @@ secure_proxy_sa3: mailbox@43600000 {
 		 * firmware on non-MPU processors
 		 */
 		status = "disabled";
+		bootph-pre-ram;
 	};
 
 	mcu_ram: sram@41c00000 {
@@ -175,10 +174,10 @@ mcu_timer0: timer@40400000 {
 		ti,timer-pwm;
 		/* Non-MPU Firmware usage */
 		status = "reserved";
+		bootph-all;
 	};
 
 	mcu_timer1: timer@40410000 {
-		bootph-all;
 		compatible = "ti,am654-timer";
 		reg = <0x00 0x40410000 0x00 0x400>;
 		interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>;
@@ -458,7 +457,6 @@ mcu_spi2: spi@40320000 {
 	};
 
 	mcu_navss: bus@28380000 {
-		bootph-all;
 		compatible = "simple-bus";
 		#address-cells = <2>;
 		#size-cells = <2>;
@@ -521,6 +519,7 @@ secure_proxy_mcu: mailbox@2a480000 {
 		 * firmware on non-MPU processors
 		 */
 		status = "disabled";
+		bootph-pre-ram;
 	};
 
 	mcu_cpsw: ethernet@46000000 {
@@ -632,6 +631,7 @@ wkup_vtm0: temperature-sensor@42040000 {
 		      <0x00 0x42050000 0x00 0x350>;
 		power-domains = <&k3_pds 243 TI_SCI_PD_SHARED>;
 		#thermal-sensor-cells = <1>;
+		bootph-pre-ram;
 	};
 
 	tscadc0: tscadc@40200000 {

-- 
2.45.1

[PATCH v3 3/5] arm64: dts: ti: k3-am68*: Add bootph-* properties

[Manorit Chawdhry]

Adds bootph-* properties to the leaf nodes to enable U-boot to
utilise them.

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts | 10 ++++++++++
 arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi       |  2 ++
 2 files changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts
index 90dbe31c5b81..38f146f6d8e9 100644
--- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts
@@ -184,6 +184,7 @@ main_uart8_pins_default: main-uart8-default-pins {
 			J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */
 			J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */
 		>;
+		bootph-all;
 	};
 
 	main_i2c0_pins_default: main-i2c0-default-pins {
@@ -210,6 +211,7 @@ J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */
 			J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */
 			J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */
 		>;
+		bootph-all;
 	};
 
 	vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
@@ -222,6 +224,7 @@ main_usbss0_pins_default: main-usbss0-default-pins {
 		pinctrl-single,pins = <
 			J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */
 		>;
+		bootph-all;
 	};
 
 	main_mcan6_pins_default: main-mcan6-default-pins {
@@ -312,6 +315,7 @@ J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */
 			J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */
 			J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */
 		>;
+		bootph-all;
 	};
 
 	mcu_cpsw_pins_default: mcu-cpsw-default-pins {
@@ -412,6 +416,7 @@ &wkup_uart0 {
 	status = "reserved";
 	pinctrl-names = "default";
 	pinctrl-0 = <&wkup_uart0_pins_default>;
+	bootph-all;
 };
 
 &wkup_i2c0 {
@@ -494,6 +499,7 @@ &mcu_uart0 {
 	status = "okay";
 	pinctrl-names = "default";
 	pinctrl-0 = <&mcu_uart0_pins_default>;
+	bootph-all;
 };
 
 &main_uart8 {
@@ -502,6 +508,7 @@ &main_uart8 {
 	pinctrl-0 = <&main_uart8_pins_default>;
 	/* Shared with TFA on this platform */
 	power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>;
+	bootph-all;
 };
 
 &main_i2c0 {
@@ -596,6 +603,7 @@ &main_sdhci1 {
 	disable-wp;
 	vmmc-supply = <&vdd_mmc1>;
 	vqmmc-supply = <&vdd_sd_dv>;
+	bootph-all;
 };
 
 &mcu_cpsw {
@@ -728,6 +736,7 @@ &usbss0 {
 	pinctrl-0 = <&main_usbss0_pins_default>;
 	pinctrl-names = "default";
 	ti,vbus-divider;
+	bootph-all;
 };
 
 &usb0 {
@@ -735,4 +744,5 @@ &usb0 {
 	maximum-speed = "super-speed";
 	phys = <&serdes0_usb_link>;
 	phy-names = "cdns3,usb3-phy";
+	bootph-all;
 };
diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi b/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi
index 5c66e0ec6e82..f2ec7ed0f2ec 100644
--- a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi
@@ -156,6 +156,7 @@ wkup_i2c0_pins_default: wkup-i2c0-default-pins {
 			J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */
 			J721S2_WKUP_IOPAD(0x09c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */
 		>;
+		bootph-all;
 	};
 };
 
@@ -169,6 +170,7 @@ eeprom@51 {
 		/* AT24C512C-MAHM-T */
 		compatible = "atmel,24c512";
 		reg = <0x51>;
+		bootph-all;
 	};
 };
 

-- 
2.45.1

[PATCH v3 4/5] arm64: dts: ti: k3-j721e*: Add bootph-* properties

[Manorit Chawdhry]

Adds bootph-* properties to the leaf nodes to enable U-boot to
utilise them.

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
---
 .../arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 20 ++++++++++++++++++++
 arch/arm64/boot/dts/ti/k3-j721e-main.dtsi            |  2 ++
 arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi      |  9 +++++++++
 arch/arm64/boot/dts/ti/k3-j721e-sk.dts               | 18 ++++++++++++++++++
 arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi          |  5 +++++
 5 files changed, 54 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index 8230d53cd696..ebc9ab3b6790 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -193,6 +193,7 @@ J721E_IOPAD(0x1c0, PIN_OUTPUT, 1) /* (AA2) SPI0_CS0.UART0_RTSn */
 			J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
 			J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
 		>;
+		bootph-all;
 	};
 
 	main_uart1_pins_default: main-uart1-default-pins {
@@ -234,6 +235,7 @@ J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
 			J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
 			J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */
 		>;
+		bootph-all;
 	};
 
 	vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins {
@@ -247,6 +249,7 @@ main_usbss0_pins_default: main-usbss0-default-pins {
 			J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
 			J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
 		>;
+		bootph-all;
 	};
 
 	main_usbss1_pins_default: main-usbss1-default-pins {
@@ -272,6 +275,7 @@ main_i2c0_pins_default: main-i2c0-default-pins {
 			J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
 			J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
 		>;
+		bootph-all;
 	};
 
 	main_i2c1_pins_default: main-i2c1-default-pins {
@@ -342,6 +346,7 @@ wkup_uart0_pins_default: wkup-uart0-default-pins {
 			J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */
 			J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */
 		>;
+		bootph-all;
 	};
 
 	mcu_uart0_pins_default: mcu-uart0-default-pins {
@@ -351,6 +356,7 @@ J721E_WKUP_IOPAD(0xec, PIN_OUTPUT, 0) /* (J27) WKUP_GPIO0_15.MCU_UART0_RTSn */
 			J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */
 			J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0) /* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */
 		>;
+		bootph-all;
 	};
 
 	sw11_button_pins_default: sw11-button-default-pins {
@@ -370,6 +376,7 @@ J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23) MCU_OSPI1_D3 */
 			J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */
 			J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */
 		>;
+		bootph-all;
 	};
 
 	mcu_cpsw_pins_default: mcu-cpsw-default-pins {
@@ -427,6 +434,7 @@ wkup_gpio_pins_default: wkup-gpio-default-pins {
 		pinctrl-single,pins = <
 			J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_8 */
 		>;
+		bootph-all;
 	};
 };
 
@@ -435,12 +443,14 @@ &wkup_uart0 {
 	status = "reserved";
 	pinctrl-names = "default";
 	pinctrl-0 = <&wkup_uart0_pins_default>;
+	bootph-all;
 };
 
 &mcu_uart0 {
 	status = "okay";
 	pinctrl-names = "default";
 	pinctrl-0 = <&mcu_uart0_pins_default>;
+	bootph-all;
 };
 
 &main_uart0 {
@@ -449,6 +459,7 @@ &main_uart0 {
 	pinctrl-0 = <&main_uart0_pins_default>;
 	/* Shared with ATF on this platform */
 	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
+	bootph-all;
 };
 
 &main_uart1 {
@@ -473,6 +484,7 @@ &wkup_gpio0 {
 	status = "okay";
 	pinctrl-names = "default";
 	pinctrl-0 = <&wkup_gpio_pins_default>;
+	bootph-all;
 };
 
 &main_gpio0 {
@@ -489,6 +501,7 @@ &main_sdhci0 {
 	non-removable;
 	ti,driver-strength-ohm = <50>;
 	disable-wp;
+	bootph-all;
 };
 
 &main_sdhci1 {
@@ -500,10 +513,12 @@ &main_sdhci1 {
 	pinctrl-0 = <&main_mmc1_pins_default>;
 	ti,driver-strength-ohm = <50>;
 	disable-wp;
+	bootph-all;
 };
 
 &usb_serdes_mux {
 	idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */
+	bootph-all;
 };
 
 &serdes_ln_ctrl {
@@ -513,6 +528,7 @@ &serdes_ln_ctrl {
 		      <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
 		      <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
 		      <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
+	bootph-all;
 };
 
 &serdes_wiz3 {
@@ -534,6 +550,7 @@ &usbss0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&main_usbss0_pins_default>;
 	ti,vbus-divider;
+	bootph-all;
 };
 
 &usb0 {
@@ -541,6 +558,7 @@ &usb0 {
 	maximum-speed = "super-speed";
 	phys = <&serdes3_usb_link>;
 	phy-names = "cdns3,usb3-phy";
+	bootph-all;
 };
 
 &usbss1 {
@@ -569,6 +587,7 @@ flash@0 {
 		cdns,tchsh-ns = <60>;
 		cdns,tslch-ns = <60>;
 		cdns,read-delay = <2>;
+		bootph-all;
 
 		partitions {
 			compatible = "fixed-partitions";
@@ -650,6 +669,7 @@ exp2: gpio@22 {
 		reg = <0x22>;
 		gpio-controller;
 		#gpio-cells = <2>;
+		bootph-all;
 
 		p09-hog {
 			/* P11 - MCASP/TRACE_MUX_S0 */
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index 0da785be80ff..584badcb796d 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -226,6 +226,7 @@ secure_proxy_main: mailbox@32c00000 {
 			      <0x00 0x32800000 0x00 0x100000>;
 			interrupt-names = "rx_011";
 			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+			bootph-all;
 		};
 
 		smmu0: iommu@36600000 {
@@ -2854,5 +2855,6 @@ main_esm: esm@700000 {
 		compatible = "ti,j721e-esm";
 		reg = <0x0 0x700000 0x0 0x1000>;
 		ti,esm-pins = <344>, <345>;
+		bootph-all;
 	};
 };
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
index 6b6ef6a30614..6ecbf5ee8b78 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
@@ -21,16 +21,19 @@ dmsc: system-controller@44083000 {
 		k3_pds: power-controller {
 			compatible = "ti,sci-pm-domain";
 			#power-domain-cells = <2>;
+			bootph-all;
 		};
 
 		k3_clks: clock-controller {
 			compatible = "ti,k2g-sci-clk";
 			#clock-cells = <2>;
+			bootph-all;
 		};
 
 		k3_reset: reset-controller {
 			compatible = "ti,sci-reset";
 			#reset-cells = <2>;
+			bootph-all;
 		};
 	};
 
@@ -61,6 +64,7 @@ wkup_conf: bus@43000000 {
 		chipid: chipid@14 {
 			compatible = "ti,am654-chipid";
 			reg = <0x14 0x4>;
+			bootph-all;
 		};
 	};
 
@@ -115,6 +119,7 @@ mcu_timer0: timer@40400000 {
 		ti,timer-pwm;
 		/* Non-MPU Firmware usage */
 		status = "reserved";
+		bootph-pre-ram;
 	};
 
 	mcu_timer1: timer@40410000 {
@@ -475,6 +480,7 @@ mcu_ringacc: ringacc@2b800000 {
 			ti,sci = <&dmsc>;
 			ti,sci-dev-id = <235>;
 			msi-parent = <&main_udmass_inta>;
+			bootph-all;
 		};
 
 		mcu_udmap: dma-controller@285c0000 {
@@ -499,6 +505,7 @@ mcu_udmap: dma-controller@285c0000 {
 			ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
 						<0x0b>; /* RX_HCHAN */
 			ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
+			bootph-all;
 		};
 	};
 
@@ -515,6 +522,7 @@ secure_proxy_mcu: mailbox@2a480000 {
 		 * firmware on non-MPU processors
 		 */
 		status = "disabled";
+		bootph-pre-ram;
 	};
 
 	mcu_cpsw: ethernet@46000000 {
@@ -687,6 +695,7 @@ wkup_vtm0: temperature-sensor@42040000 {
 		      <0x00 0x43000300 0x00 0x10>;
 		power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
 		#thermal-sensor-cells = <1>;
+		bootph-pre-ram;
 	};
 
 	mcu_esm: esm@40800000 {
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
index 89fbfb21e5d3..b63d48719090 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
@@ -346,6 +346,7 @@ J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
 			J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
 			J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
 		>;
+		bootph-all;
 	};
 
 	main_uart0_pins_default: main-uart0-default-pins {
@@ -355,6 +356,7 @@ J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */
 			J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
 			J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
 		>;
+		bootph-all;
 	};
 
 	main_uart1_pins_default: main-uart1-default-pins {
@@ -390,12 +392,14 @@ main_usbss0_pins_default: main-usbss0-default-pins {
 			J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
 			J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
 		>;
+		bootph-all;
 	};
 
 	main_usbss1_pins_default: main-usbss1-default-pins {
 		pinctrl-single,pins = <
 			J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
 		>;
+		bootph-all;
 	};
 
 	main_csi_mux_sel_pins_default: main-csi-mux-sel-default-pins {
@@ -594,6 +598,7 @@ J721E_WKUP_IOPAD(0x24, PIN_INPUT, 0) /* (B22) MCU_OSPI0_D6 */
 			J721E_WKUP_IOPAD(0x28, PIN_INPUT, 0) /* (G21) MCU_OSPI0_D7 */
 			J721E_WKUP_IOPAD(0x8, PIN_INPUT, 0) /* (D21) MCU_OSPI0_DQS */
 		>;
+		bootph-all;
 	};
 
 	vdd_mmc1_en_pins_default: vdd-mmc1-en-default-pins {
@@ -622,6 +627,7 @@ J721E_WKUP_IOPAD(0xf4, PIN_OUTPUT, 2)/* (D25) MCU_I3C0_SDA.MCU_UART0_RTSn */
 			J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */
 			J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0)/* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */
 		>;
+		bootph-pre-ram;
 	};
 
 	wkup_i2c0_pins_default: wkup-i2c0-default-pins {
@@ -629,6 +635,7 @@ wkup_i2c0_pins_default: wkup-i2c0-default-pins {
 			J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
 			J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
 		>;
+		bootph-all;
 	};
 
 	mcu_mcan0_pins_default: mcu-mcan0-default-pins {
@@ -657,6 +664,7 @@ &wkup_uart0 {
 	status = "reserved";
 	pinctrl-names = "default";
 	pinctrl-0 = <&wkup_uart0_pins_default>;
+	bootph-all;
 };
 
 &wkup_i2c0 {
@@ -821,6 +829,7 @@ &mcu_uart0 {
 	status = "okay";
 	pinctrl-names = "default";
 	pinctrl-0 = <&mcu_uart0_pins_default>;
+	bootph-all;
 };
 
 &main_uart0 {
@@ -829,6 +838,7 @@ &main_uart0 {
 	pinctrl-0 = <&main_uart0_pins_default>;
 	/* Shared with ATF on this platform */
 	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
+	bootph-all;
 };
 
 &main_uart1 {
@@ -846,6 +856,7 @@ &main_sdhci1 {
 	pinctrl-0 = <&main_mmc1_pins_default>;
 	ti,driver-strength-ohm = <50>;
 	disable-wp;
+	bootph-all;
 };
 
 &ospi0 {
@@ -864,6 +875,7 @@ flash@0 {
 		cdns,tchsh-ns = <60>;
 		cdns,tslch-ns = <60>;
 		cdns,read-delay = <4>;
+		bootph-all;
 
 		partitions {
 			compatible = "fixed-partitions";
@@ -1003,6 +1015,7 @@ &wkup_gpio0 {
 
 &usb_serdes_mux {
 	idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */
+	bootph-all;
 };
 
 &serdes_ln_ctrl {
@@ -1012,6 +1025,7 @@ &serdes_ln_ctrl {
 		      <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
 		      <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
 		      <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
+	bootph-all;
 };
 
 &serdes_wiz3 {
@@ -1051,6 +1065,7 @@ &usbss0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&main_usbss0_pins_default>;
 	ti,vbus-divider;
+	bootph-all;
 };
 
 &usb0 {
@@ -1058,6 +1073,7 @@ &usb0 {
 	maximum-speed = "super-speed";
 	phys = <&serdes3_usb_link>;
 	phy-names = "cdns3,usb3-phy";
+	bootph-all;
 };
 
 &serdes2 {
@@ -1074,6 +1090,7 @@ &usbss1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&main_usbss1_pins_default>;
 	ti,vbus-divider;
+	bootph-all;
 };
 
 &usb1 {
@@ -1081,6 +1098,7 @@ &usb1 {
 	maximum-speed = "super-speed";
 	phys = <&serdes2_usb_link>;
 	phy-names = "cdns3,usb3-phy";
+	bootph-all;
 };
 
 &mcu_cpsw {
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
index 5ba947771b84..86bfc5e21eed 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
@@ -151,6 +151,7 @@ wkup_i2c0_pins_default: wkup-i2c0-default-pins {
 			J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
 			J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
 		>;
+		bootph-all;
 	};
 
 	pmic_irq_pins_default: pmic-irq-default-pins {
@@ -173,6 +174,7 @@ J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0)  /* MCU_OSPI0_D6 */
 			J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0)  /* MCU_OSPI0_D7 */
 			J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */
 		>;
+		bootph-all;
 	};
 
 	mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-default-pins {
@@ -192,6 +194,7 @@ J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1)  /* MCU_HYPERBUS0_DQ5 */
 			J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1)  /* MCU_HYPERBUS0_DQ6 */
 			J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1)  /* MCU_HYPERBUS0_DQ7 */
 		>;
+		bootph-all;
 	};
 };
 
@@ -378,6 +381,7 @@ flash@0 {
 		cdns,tchsh-ns = <60>;
 		cdns,tslch-ns = <60>;
 		cdns,read-delay = <0>;
+		bootph-all;
 
 		partitions {
 			compatible = "fixed-partitions";
@@ -440,6 +444,7 @@ &hbmc {
 	flash@0,0 {
 		compatible = "cypress,hyperflash", "cfi-flash";
 		reg = <0x00 0x00 0x4000000>;
+		bootph-all;
 
 		partitions {
 			compatible = "fixed-partitions";

-- 
2.45.1

[PATCH v3 5/5] arm64: dts: ti: k3-j7200*: Add bootph-* properties

[Manorit Chawdhry]

Adds bootph-* properties to the leaf nodes to enable U-boot to
utilise them.

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
---
 .../arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 20 ++++++++++++++++++++
 arch/arm64/boot/dts/ti/k3-j7200-main.dtsi            |  2 ++
 arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi      | 10 ++++++++++
 arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi          |  7 +++++++
 4 files changed, 39 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
index 6593c5da82c0..ec522595fc83 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
@@ -129,6 +129,7 @@ J721E_WKUP_IOPAD(0x94, PIN_OUTPUT, 0) /* (E21) MCU_UART0_RTSn */
 			J721E_WKUP_IOPAD(0x8c, PIN_INPUT, 0) /* (D20) MCU_UART0_RXD */
 			J721E_WKUP_IOPAD(0x88, PIN_OUTPUT, 0) /* (D19) MCU_UART0_TXD */
 		>;
+		bootph-all;
 	};
 
 	wkup_uart0_pins_default: wkup-uart0-default-pins {
@@ -136,6 +137,7 @@ wkup_uart0_pins_default: wkup-uart0-default-pins {
 			J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */
 			J721E_WKUP_IOPAD(0x4c, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */
 		>;
+		bootph-all;
 	};
 
 	mcu_cpsw_pins_default: mcu-cpsw-default-pins {
@@ -159,6 +161,7 @@ wkup_gpio_pins_default: wkup-gpio-default-pins {
 		pinctrl-single,pins = <
 			J721E_WKUP_IOPAD(0x70, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */
 		>;
+		bootph-all;
 	};
 
 	mcu_mdio_pins_default: mcu-mdio1-default-pins {
@@ -204,6 +207,7 @@ J721E_IOPAD(0xb4, PIN_OUTPUT, 0) /* (T17) UART0_TXD */
 			J721E_IOPAD(0xc0, PIN_INPUT, 2) /* (W3) SPI0_CS0.UART0_CTSn */
 			J721E_IOPAD(0xc4, PIN_OUTPUT, 2) /* (U5) SPI0_CS1.UART0_RTSn */
 		>;
+		bootph-all;
 	};
 
 	main_uart1_pins_default: main-uart1-default-pins {
@@ -238,6 +242,7 @@ J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */
 			J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */
 			J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */
 		>;
+		bootph-all;
 	};
 
 	vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
@@ -259,6 +264,7 @@ main_usbss0_pins_default: main-usbss0-default-pins {
 		pinctrl-single,pins = <
 			J721E_IOPAD(0x04, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
 		>;
+		bootph-all;
 	};
 };
 
@@ -267,12 +273,14 @@ &wkup_uart0 {
 	status = "reserved";
 	pinctrl-names = "default";
 	pinctrl-0 = <&wkup_uart0_pins_default>;
+	bootph-all;
 };
 
 &mcu_uart0 {
 	status = "okay";
 	pinctrl-names = "default";
 	pinctrl-0 = <&mcu_uart0_pins_default>;
+	bootph-all;
 };
 
 &main_uart0 {
@@ -281,6 +289,7 @@ &main_uart0 {
 	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&main_uart0_pins_default>;
+	bootph-all;
 };
 
 &main_uart1 {
@@ -310,6 +319,7 @@ &wkup_gpio0 {
 	status = "okay";
 	pinctrl-names = "default";
 	pinctrl-0 = <&wkup_gpio_pins_default>;
+	bootph-all;
 };
 
 &mcu_cpsw {
@@ -341,6 +351,7 @@ exp1: gpio@20 {
 		reg = <0x20>;
 		gpio-controller;
 		#gpio-cells = <2>;
+		bootph-all;
 	};
 
 	exp2: gpio@22 {
@@ -348,6 +359,7 @@ exp2: gpio@22 {
 		reg = <0x22>;
 		gpio-controller;
 		#gpio-cells = <2>;
+		bootph-all;
 	};
 };
 
@@ -381,6 +393,7 @@ &main_sdhci0 {
 	non-removable;
 	ti,driver-strength-ohm = <50>;
 	disable-wp;
+	bootph-all;
 };
 
 &main_sdhci1 {
@@ -392,15 +405,18 @@ &main_sdhci1 {
 	vqmmc-supply = <&vdd_sd_dv>;
 	ti,driver-strength-ohm = <50>;
 	disable-wp;
+	bootph-all;
 };
 
 &serdes_ln_ctrl {
 	idle-states = <J7200_SERDES0_LANE0_PCIE1_LANE0>, <J7200_SERDES0_LANE1_PCIE1_LANE1>,
 		      <J7200_SERDES0_LANE2_QSGMII_LANE1>, <J7200_SERDES0_LANE3_IP4_UNUSED>;
+	bootph-all;
 };
 
 &usb_serdes_mux {
 	idle-states = <1>; /* USB0 to SERDES lane 3 */
+	bootph-all;
 };
 
 &usbss0 {
@@ -408,11 +424,13 @@ &usbss0 {
 	pinctrl-0 = <&main_usbss0_pins_default>;
 	ti,vbus-divider;
 	ti,usb2-only;
+	bootph-all;
 };
 
 &usb0 {
 	dr_mode = "otg";
 	maximum-speed = "high-speed";
+	bootph-all;
 };
 
 &tscadc0 {
@@ -432,6 +450,7 @@ serdes0_pcie_link: phy@0 {
 		#phy-cells = <0>;
 		cdns,phy-type = <PHY_TYPE_PCIE>;
 		resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
+		bootph-all;
 	};
 
 	serdes0_qsgmii_link: phy@1 {
@@ -440,6 +459,7 @@ serdes0_qsgmii_link: phy@1 {
 		#phy-cells = <0>;
 		cdns,phy-type = <PHY_TYPE_QSGMII>;
 		resets = <&serdes_wiz0 3>;
+		bootph-all;
 	};
 };
 
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index 9386bf3ef9f6..b95656942412 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -136,6 +136,7 @@ secure_proxy_main: mailbox@32c00000 {
 			      <0x00 0x32800000 0x00 0x100000>;
 			interrupt-names = "rx_011";
 			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+			bootph-all;
 		};
 
 		hwspinlock: spinlock@30e00000 {
@@ -1528,5 +1529,6 @@ main_esm: esm@700000 {
 		compatible = "ti,j721e-esm";
 		reg = <0x0 0x700000 0x0 0x1000>;
 		ti,esm-pins = <656>, <657>;
+		bootph-all;
 	};
 };
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
index 5097d192c2b2..f8a5ad4737da 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
@@ -21,16 +21,19 @@ dmsc: system-controller@44083000 {
 		k3_pds: power-controller {
 			compatible = "ti,sci-pm-domain";
 			#power-domain-cells = <2>;
+			bootph-all;
 		};
 
 		k3_clks: clock-controller {
 			compatible = "ti,k2g-sci-clk";
 			#clock-cells = <2>;
+			bootph-all;
 		};
 
 		k3_reset: reset-controller {
 			compatible = "ti,sci-reset";
 			#reset-cells = <2>;
+			bootph-all;
 		};
 	};
 
@@ -45,6 +48,7 @@ mcu_timer0: timer@40400000 {
 		assigned-clock-parents = <&k3_clks 35 2>;
 		power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
 		ti,timer-pwm;
+		bootph-pre-ram;
 	};
 
 	mcu_timer1: timer@40410000 {
@@ -191,6 +195,7 @@ wkup_conf: bus@43000000 {
 		chipid: chipid@14 {
 			compatible = "ti,am654-chipid";
 			reg = <0x14 0x4>;
+			bootph-all;
 		};
 	};
 
@@ -349,6 +354,7 @@ mcu_ringacc: ringacc@2b800000 {
 			ti,sci = <&dmsc>;
 			ti,sci-dev-id = <235>;
 			msi-parent = <&main_udmass_inta>;
+			bootph-all;
 		};
 
 		mcu_udmap: dma-controller@285c0000 {
@@ -373,6 +379,7 @@ mcu_udmap: dma-controller@285c0000 {
 			ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
 						<0x0b>; /* RX_HCHAN */
 			ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
+			bootph-all;
 		};
 	};
 
@@ -389,6 +396,7 @@ secure_proxy_mcu: mailbox@2a480000 {
 		 * firmware on non-MPU processors
 		 */
 		status = "disabled";
+		bootph-pre-ram;
 	};
 
 	mcu_cpsw: ethernet@46000000 {
@@ -534,6 +542,7 @@ hbmc_mux: mux-controller@47000004 {
 			reg = <0x00 0x47000004 0x00 0x4>;
 			#mux-control-cells = <1>;
 			mux-reg-masks = <0x0 0x2>; /* HBMC select */
+			bootph-pre-ram;
 		};
 
 		hbmc: hyperbus@47034000 {
@@ -652,6 +661,7 @@ wkup_vtm0: temperature-sensor@42040000 {
 		      <0x00 0x42050000 0x00 0x350>;
 		power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
 		#thermal-sensor-cells = <1>;
+		bootph-pre-ram;
 	};
 
 	mcu_esm: esm@40800000 {
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
index 21fe194a5766..d78f86889bf9 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
@@ -121,6 +121,7 @@ J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (B8) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
 			J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
 			J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
 		>;
+		bootph-all;
 	};
 
 	mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
@@ -137,6 +138,7 @@ J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0)  /* MCU_OSPI0_D6 */
 			J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0)  /* MCU_OSPI0_D7 */
 			J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0)  /* MCU_OSPI0_DQS */
 		>;
+		bootph-all;
 	};
 };
 
@@ -146,6 +148,7 @@ wkup_i2c0_pins_default: wkup-i2c0-default-pins {
 			J721E_WKUP_IOPAD(0x98, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */
 			J721E_WKUP_IOPAD(0x9c, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */
 		>;
+		bootph-all;
 	};
 };
 
@@ -163,6 +166,7 @@ main_i2c0_pins_default: main-i2c0-default-pins {
 			J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
 			J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
 		>;
+		bootph-all;
 	};
 
 	main_mcan0_pins_default: main-mcan0-default-pins {
@@ -186,6 +190,7 @@ &hbmc {
 	flash@0,0 {
 		compatible = "cypress,hyperflash", "cfi-flash";
 		reg = <0x00 0x00 0x4000000>;
+		bootph-all;
 
 		partitions {
 			compatible = "fixed-partitions";
@@ -330,6 +335,7 @@ bucka1: buck1 {
 				regulator-max-microvolt = <1800000>;
 				regulator-boot-on;
 				regulator-always-on;
+				bootph-all;
 			};
 
 			bucka2: buck2 {
@@ -464,6 +470,7 @@ flash@0 {
 		cdns,tchsh-ns = <60>;
 		cdns,tslch-ns = <60>;
 		cdns,read-delay = <4>;
+		bootph-all;
 
 		partitions {
 			compatible = "fixed-partitions";

-- 
2.45.1

Re: [PATCH v3 1/5] arm64: dts: ti: k3-j721s2*: Add bootph-* properties

[Andrew Davis]

On 7/30/24 4:53 AM, Manorit Chawdhry wrote:
> Adds bootph-* properties to the leaf nodes to enable U-boot to
> utilise them.

U-Boot? Let's try to pretend like this is a generic property and
just say "bootloader" :)

Thinking out loud, what happens when we want to re-use these DT
source files in Zephyr, or some other software, will we keep adding
these new metadata tags?.. bootph-* and other "domain info" might
better belong to some higher level device tree source (System
Device Tree I'd guess, time to add Lopper to kernel? :D)

For now, lgtm,

Reviewed-by: Andrew Davis <afd@ti.com>

> 
> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
> ---
>   arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts | 14 ++++++++++++++
>   arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi             |  2 ++
>   arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi       | 11 +++++++++++
>   arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi           |  2 ++
>   4 files changed, 29 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
> index c5a0b7cbb14f..6ce14f9e087b 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
> @@ -138,6 +138,7 @@ J721S2_IOPAD(0x044, PIN_OUTPUT, 14) /* (Y26) MCASP0_AXR1.UART8_RTSn */
>   			J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */
>   			J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */
>   		>;
> +		bootph-all;
>   	};
>   
>   	main_i2c3_pins_default: main-i2c3-default-pins {
> @@ -165,6 +166,7 @@ J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */
>   			J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */
>   			J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */
>   		>;
> +		bootph-all;
>   	};
>   
>   	vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
> @@ -177,6 +179,7 @@ main_usbss0_pins_default: main-usbss0-default-pins {
>   		pinctrl-single,pins = <
>   			J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */
>   		>;
> +		bootph-all;
>   	};
>   
>   	main_mcan3_pins_default: main-mcan3-default-pins {
> @@ -200,6 +203,7 @@ wkup_uart0_pins_default: wkup-uart0-default-pins {
>   			J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */
>   			J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */
>   		>;
> +		bootph-all;
>   	};
>   
>   	mcu_uart0_pins_default: mcu-uart0-default-pins {
> @@ -209,6 +213,7 @@ J721S2_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (D25) WKUP_GPIO0_15.MCU_UART0_RTSn */
>   			J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */
>   			J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */
>   		>;
> +		bootph-all;
>   	};
>   
>   	mcu_cpsw_pins_default: mcu-cpsw-default-pins {
> @@ -301,6 +306,7 @@ J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */
>   			J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */
>   			J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */
>   		>;
> +		bootph-all;
>   	};
>   };
>   
> @@ -316,12 +322,14 @@ &wkup_uart0 {
>   	status = "reserved";
>   	pinctrl-names = "default";
>   	pinctrl-0 = <&wkup_uart0_pins_default>;
> +	bootph-all;
>   };
>   
>   &mcu_uart0 {
>   	status = "okay";
>   	pinctrl-names = "default";
>   	pinctrl-0 = <&mcu_uart0_pins_default>;
> +	bootph-all;
>   };
>   
>   &main_uart8 {
> @@ -330,6 +338,7 @@ &main_uart8 {
>   	pinctrl-0 = <&main_uart8_pins_default>;
>   	/* Shared with TFA on this platform */
>   	power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>;
> +	bootph-all;
>   };
>   
>   &main_i2c0 {
> @@ -385,6 +394,7 @@ &main_sdhci0 {
>   	non-removable;
>   	ti,driver-strength-ohm = <50>;
>   	disable-wp;
> +	bootph-all;
>   };
>   
>   &main_sdhci1 {
> @@ -395,6 +405,7 @@ &main_sdhci1 {
>   	disable-wp;
>   	vmmc-supply = <&vdd_mmc1>;
>   	vqmmc-supply = <&vdd_sd_dv>;
> +	bootph-all;
>   };
>   
>   &mcu_cpsw {
> @@ -446,11 +457,13 @@ &usbss0 {
>   	pinctrl-names = "default";
>   	ti,vbus-divider;
>   	ti,usb2-only;
> +	bootph-all;
>   };
>   
>   &usb0 {
>   	dr_mode = "otg";
>   	maximum-speed = "high-speed";
> +	bootph-all;
>   };
>   
>   &ospi1 {
> @@ -469,6 +482,7 @@ flash@0 {
>   		cdns,tchsh-ns = <60>;
>   		cdns,tslch-ns = <60>;
>   		cdns,read-delay = <2>;
> +		bootph-all;
>   	};
>   };
>   
> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> index 9ed6949b40e9..0ea6817de65c 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> @@ -816,6 +816,7 @@ secure_proxy_main: mailbox@32c00000 {
>   			      <0x00 0x32800000 0x00 0x100000>;
>   			interrupt-names = "rx_011";
>   			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> +			bootph-all;
>   		};
>   
>   		hwspinlock: spinlock@30e00000 {
> @@ -1225,6 +1226,7 @@ usb0: usb@6000000 {
>   			interrupt-names = "host", "peripheral", "otg";
>   			maximum-speed = "super-speed";
>   			dr_mode = "otg";
> +			bootph-all;
>   		};
>   	};
>   
> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
> index 8feb42c89e47..8345313f8d94 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
> @@ -21,16 +21,19 @@ sms: system-controller@44083000 {
>   		k3_pds: power-controller {
>   			compatible = "ti,sci-pm-domain";
>   			#power-domain-cells = <2>;
> +			bootph-all;
>   		};
>   
>   		k3_clks: clock-controller {
>   			compatible = "ti,k2g-sci-clk";
>   			#clock-cells = <2>;
> +			bootph-all;
>   		};
>   
>   		k3_reset: reset-controller {
>   			compatible = "ti,sci-reset";
>   			#reset-cells = <2>;
> +			bootph-all;
>   		};
>   	};
>   
> @@ -43,6 +46,7 @@ wkup_conf: bus@43000000 {
>   		chipid: chipid@14 {
>   			compatible = "ti,am654-chipid";
>   			reg = <0x14 0x4>;
> +			bootph-all;
>   		};
>   	};
>   
> @@ -59,6 +63,7 @@ secure_proxy_sa3: mailbox@43600000 {
>   		 * firmware on non-MPU processors
>   		 */
>   		status = "disabled";
> +		bootph-pre-ram;
>   	};
>   
>   	mcu_ram: sram@41c00000 {
> @@ -170,6 +175,7 @@ mcu_timer0: timer@40400000 {
>   		ti,timer-pwm;
>   		/* Non-MPU Firmware usage */
>   		status = "reserved";
> +		bootph-pre-ram;
>   	};
>   
>   	mcu_timer1: timer@40410000 {
> @@ -362,6 +368,7 @@ wkup_i2c0: i2c@42120000 {
>   		clock-names = "fck";
>   		power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>;
>   		status = "disabled";
> +		bootph-all;
>   	};
>   
>   	mcu_i2c0: i2c@40b00000 {
> @@ -474,6 +481,7 @@ mcu_ringacc: ringacc@2b800000 {
>   			ti,sci = <&sms>;
>   			ti,sci-dev-id = <272>;
>   			msi-parent = <&main_udmass_inta>;
> +			bootph-all;
>   		};
>   
>   		mcu_udmap: dma-controller@285c0000 {
> @@ -497,6 +505,7 @@ mcu_udmap: dma-controller@285c0000 {
>   			ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
>   						<0x0b>; /* RX_HCHAN */
>   			ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
> +			bootph-all;
>   		};
>   	};
>   
> @@ -513,6 +522,7 @@ secure_proxy_mcu: mailbox@2a480000 {
>   		 * firmware on non-MPU processors
>   		 */
>   		status = "disabled";
> +		bootph-pre-ram;
>   	};
>   
>   	mcu_cpsw: ethernet@46000000 {
> @@ -667,6 +677,7 @@ wkup_vtm0: temperature-sensor@42040000 {
>   		      <0x00 0x42050000 0x0 0x350>;
>   		power-domains = <&k3_pds 180 TI_SCI_PD_SHARED>;
>   		#thermal-sensor-cells = <1>;
> +		bootph-pre-ram;
>   	};
>   
>   	mcu_r5fss0: r5fss@41000000 {
> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
> index 82aacc01e8fe..dfcc223809e7 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
> @@ -170,6 +170,7 @@ J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */
>   			J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */
>   			J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */
>   		>;
> +		bootph-all;
>   	};
>   };
>   
> @@ -445,6 +446,7 @@ flash@0 {
>   		cdns,tchsh-ns = <60>;
>   		cdns,tslch-ns = <60>;
>   		cdns,read-delay = <4>;
> +		bootph-all;
>   	};
>   };
>   
> 

Re: [PATCH v3 1/5] arm64: dts: ti: k3-j721s2*: Add bootph-* properties

[Nishanth Menon]

On 09:43-20240806, Andrew Davis wrote:
> On 7/30/24 4:53 AM, Manorit Chawdhry wrote:
> > Adds bootph-* properties to the leaf nodes to enable U-boot to
> > utilise them.
> 
> U-Boot? Let's try to pretend like this is a generic property and
> just say "bootloader" :)

Yes please - respin with wording fixup.

-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

Re: [PATCH v3 1/5] arm64: dts: ti: k3-j721s2*: Add bootph-* properties

[Nishanth Menon]

On 09:43-20240806, Andrew Davis wrote:
> On 7/30/24 4:53 AM, Manorit Chawdhry wrote:
> > Adds bootph-* properties to the leaf nodes to enable U-boot to
> > utilise them.
> 
> U-Boot? Let's try to pretend like this is a generic property and
> just say "bootloader" :)
> > @@ -445,6 +446,7 @@ flash@0 {
> >   		cdns,tchsh-ns = <60>;
> >   		cdns,tslch-ns = <60>;
> >   		cdns,read-delay = <4>;
> > +		bootph-all;

Here and elsewhere, follow:
	https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/dts-coding-style.rst#n117

> >   	};
> >   };
> > 

-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

Re: [PATCH v3 1/5] arm64: dts: ti: k3-j721s2*: Add bootph-* properties

[Manorit Chawdhry]

Hi Nishanth,

On 10:07-20240806, Nishanth Menon wrote:
> On 09:43-20240806, Andrew Davis wrote:
> > On 7/30/24 4:53 AM, Manorit Chawdhry wrote:
> > > Adds bootph-* properties to the leaf nodes to enable U-boot to
> > > utilise them.
> > 
> > U-Boot? Let's try to pretend like this is a generic property and
> > just say "bootloader" :)
> > > @@ -445,6 +446,7 @@ flash@0 {
> > >   		cdns,tchsh-ns = <60>;
> > >   		cdns,tslch-ns = <60>;
> > >   		cdns,read-delay = <4>;
> > > +		bootph-all;
> 
> Here and elsewhere, follow:
> 	https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/dts-coding-style.rst#n117

Could you tell me what are you seeing wrong? The dts-coding-style that
you shared doesn't tell a specific location for bootph-* properties so
using the generic reasoning.

"1. Most important properties start the node: compatible then bus addressing to
   match unit address."

This is the least important property considering Linux and hence the
reasoning was that it should come in the last. Also, j722s and am62p
follow the same convention so it was taken from there only.

Regards,
Manorit

> 
> 
> > >   	};
> > >   };
> > > 
> 
> -- 
> Regards,
> Nishanth Menon
> Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

Re: [PATCH v3 1/5] arm64: dts: ti: k3-j721s2*: Add bootph-* properties

[Manorit Chawdhry]

Hi Andrew,

On 09:43-20240806, Andrew Davis wrote:
> On 7/30/24 4:53 AM, Manorit Chawdhry wrote:
> > Adds bootph-* properties to the leaf nodes to enable U-boot to
> > utilise them.
> 
> U-Boot? Let's try to pretend like this is a generic property and
> just say "bootloader" :)
>
> Thinking out loud, what happens when we want to re-use these DT
> source files in Zephyr, or some other software, will we keep adding
> these new metadata tags?.. bootph-* and other "domain info" might
> better belong to some higher level device tree source (System
> Device Tree I'd guess, time to add Lopper to kernel? :D)
> 
> For now, lgtm,
> 
> Reviewed-by: Andrew Davis <afd@ti.com>

Thanks for reviewing! Would update the commit description.

Regards,
Manorit

> > 
> > Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
> > ---
> >   arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts | 14 ++++++++++++++
> >   arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi             |  2 ++
> >   arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi       | 11 +++++++++++
> >   arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi           |  2 ++
> >   4 files changed, 29 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
> > index c5a0b7cbb14f..6ce14f9e087b 100644
> > --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
> > +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
> > @@ -138,6 +138,7 @@ J721S2_IOPAD(0x044, PIN_OUTPUT, 14) /* (Y26) MCASP0_AXR1.UART8_RTSn */
> >   			J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */
> >   			J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */
> >   		>;
> > +		bootph-all;
> >   	};
> >   	main_i2c3_pins_default: main-i2c3-default-pins {
> > @@ -165,6 +166,7 @@ J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */
> >   			J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */
> >   			J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */
> >   		>;
> > +		bootph-all;
> >   	};
> >   	vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
> > @@ -177,6 +179,7 @@ main_usbss0_pins_default: main-usbss0-default-pins {
> >   		pinctrl-single,pins = <
> >   			J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */
> >   		>;
> > +		bootph-all;
> >   	};
> >   	main_mcan3_pins_default: main-mcan3-default-pins {
> > @@ -200,6 +203,7 @@ wkup_uart0_pins_default: wkup-uart0-default-pins {
> >   			J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */
> >   			J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */
> >   		>;
> > +		bootph-all;
> >   	};
> >   	mcu_uart0_pins_default: mcu-uart0-default-pins {
> > @@ -209,6 +213,7 @@ J721S2_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (D25) WKUP_GPIO0_15.MCU_UART0_RTSn */
> >   			J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */
> >   			J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */
> >   		>;
> > +		bootph-all;
> >   	};
> >   	mcu_cpsw_pins_default: mcu-cpsw-default-pins {
> > @@ -301,6 +306,7 @@ J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */
> >   			J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */
> >   			J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */
> >   		>;
> > +		bootph-all;
> >   	};
> >   };
> > @@ -316,12 +322,14 @@ &wkup_uart0 {
> >   	status = "reserved";
> >   	pinctrl-names = "default";
> >   	pinctrl-0 = <&wkup_uart0_pins_default>;
> > +	bootph-all;
> >   };
> >   &mcu_uart0 {
> >   	status = "okay";
> >   	pinctrl-names = "default";
> >   	pinctrl-0 = <&mcu_uart0_pins_default>;
> > +	bootph-all;
> >   };
> >   &main_uart8 {
> > @@ -330,6 +338,7 @@ &main_uart8 {
> >   	pinctrl-0 = <&main_uart8_pins_default>;
> >   	/* Shared with TFA on this platform */
> >   	power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>;
> > +	bootph-all;
> >   };
> >   &main_i2c0 {
> > @@ -385,6 +394,7 @@ &main_sdhci0 {
> >   	non-removable;
> >   	ti,driver-strength-ohm = <50>;
> >   	disable-wp;
> > +	bootph-all;
> >   };
> >   &main_sdhci1 {
> > @@ -395,6 +405,7 @@ &main_sdhci1 {
> >   	disable-wp;
> >   	vmmc-supply = <&vdd_mmc1>;
> >   	vqmmc-supply = <&vdd_sd_dv>;
> > +	bootph-all;
> >   };
> >   &mcu_cpsw {
> > @@ -446,11 +457,13 @@ &usbss0 {
> >   	pinctrl-names = "default";
> >   	ti,vbus-divider;
> >   	ti,usb2-only;
> > +	bootph-all;
> >   };
> >   &usb0 {
> >   	dr_mode = "otg";
> >   	maximum-speed = "high-speed";
> > +	bootph-all;
> >   };
> >   &ospi1 {
> > @@ -469,6 +482,7 @@ flash@0 {
> >   		cdns,tchsh-ns = <60>;
> >   		cdns,tslch-ns = <60>;
> >   		cdns,read-delay = <2>;
> > +		bootph-all;
> >   	};
> >   };
> > diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> > index 9ed6949b40e9..0ea6817de65c 100644
> > --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> > +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> > @@ -816,6 +816,7 @@ secure_proxy_main: mailbox@32c00000 {
> >   			      <0x00 0x32800000 0x00 0x100000>;
> >   			interrupt-names = "rx_011";
> >   			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> > +			bootph-all;
> >   		};
> >   		hwspinlock: spinlock@30e00000 {
> > @@ -1225,6 +1226,7 @@ usb0: usb@6000000 {
> >   			interrupt-names = "host", "peripheral", "otg";
> >   			maximum-speed = "super-speed";
> >   			dr_mode = "otg";
> > +			bootph-all;
> >   		};
> >   	};
> > diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
> > index 8feb42c89e47..8345313f8d94 100644
> > --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
> > +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
> > @@ -21,16 +21,19 @@ sms: system-controller@44083000 {
> >   		k3_pds: power-controller {
> >   			compatible = "ti,sci-pm-domain";
> >   			#power-domain-cells = <2>;
> > +			bootph-all;
> >   		};
> >   		k3_clks: clock-controller {
> >   			compatible = "ti,k2g-sci-clk";
> >   			#clock-cells = <2>;
> > +			bootph-all;
> >   		};
> >   		k3_reset: reset-controller {
> >   			compatible = "ti,sci-reset";
> >   			#reset-cells = <2>;
> > +			bootph-all;
> >   		};
> >   	};
> > @@ -43,6 +46,7 @@ wkup_conf: bus@43000000 {
> >   		chipid: chipid@14 {
> >   			compatible = "ti,am654-chipid";
> >   			reg = <0x14 0x4>;
> > +			bootph-all;
> >   		};
> >   	};
> > @@ -59,6 +63,7 @@ secure_proxy_sa3: mailbox@43600000 {
> >   		 * firmware on non-MPU processors
> >   		 */
> >   		status = "disabled";
> > +		bootph-pre-ram;
> >   	};
> >   	mcu_ram: sram@41c00000 {
> > @@ -170,6 +175,7 @@ mcu_timer0: timer@40400000 {
> >   		ti,timer-pwm;
> >   		/* Non-MPU Firmware usage */
> >   		status = "reserved";
> > +		bootph-pre-ram;
> >   	};
> >   	mcu_timer1: timer@40410000 {
> > @@ -362,6 +368,7 @@ wkup_i2c0: i2c@42120000 {
> >   		clock-names = "fck";
> >   		power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>;
> >   		status = "disabled";
> > +		bootph-all;
> >   	};
> >   	mcu_i2c0: i2c@40b00000 {
> > @@ -474,6 +481,7 @@ mcu_ringacc: ringacc@2b800000 {
> >   			ti,sci = <&sms>;
> >   			ti,sci-dev-id = <272>;
> >   			msi-parent = <&main_udmass_inta>;
> > +			bootph-all;
> >   		};
> >   		mcu_udmap: dma-controller@285c0000 {
> > @@ -497,6 +505,7 @@ mcu_udmap: dma-controller@285c0000 {
> >   			ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
> >   						<0x0b>; /* RX_HCHAN */
> >   			ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
> > +			bootph-all;
> >   		};
> >   	};
> > @@ -513,6 +522,7 @@ secure_proxy_mcu: mailbox@2a480000 {
> >   		 * firmware on non-MPU processors
> >   		 */
> >   		status = "disabled";
> > +		bootph-pre-ram;
> >   	};
> >   	mcu_cpsw: ethernet@46000000 {
> > @@ -667,6 +677,7 @@ wkup_vtm0: temperature-sensor@42040000 {
> >   		      <0x00 0x42050000 0x0 0x350>;
> >   		power-domains = <&k3_pds 180 TI_SCI_PD_SHARED>;
> >   		#thermal-sensor-cells = <1>;
> > +		bootph-pre-ram;
> >   	};
> >   	mcu_r5fss0: r5fss@41000000 {
> > diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
> > index 82aacc01e8fe..dfcc223809e7 100644
> > --- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
> > +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
> > @@ -170,6 +170,7 @@ J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */
> >   			J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */
> >   			J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */
> >   		>;
> > +		bootph-all;
> >   	};
> >   };
> > @@ -445,6 +446,7 @@ flash@0 {
> >   		cdns,tchsh-ns = <60>;
> >   		cdns,tslch-ns = <60>;
> >   		cdns,read-delay = <4>;
> > +		bootph-all;
> >   	};
> >   };
> > 

Re: [PATCH v3 1/5] arm64: dts: ti: k3-j721s2*: Add bootph-* properties

[Neha Malcom Francis]

Hi Manorit

On 07/08/24 10:56, Manorit Chawdhry wrote:
> Hi Nishanth,
> 
> On 10:07-20240806, Nishanth Menon wrote:
>> On 09:43-20240806, Andrew Davis wrote:
>>> On 7/30/24 4:53 AM, Manorit Chawdhry wrote:
>>>> Adds bootph-* properties to the leaf nodes to enable U-boot to
>>>> utilise them.
>>>
>>> U-Boot? Let's try to pretend like this is a generic property and
>>> just say "bootloader" :)
>>>> @@ -445,6 +446,7 @@ flash@0 {
>>>>    		cdns,tchsh-ns = <60>;
>>>>    		cdns,tslch-ns = <60>;
>>>>    		cdns,read-delay = <4>;
>>>> +		bootph-all;
>>
>> Here and elsewhere, follow:
>> 	https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/dts-coding-style.rst#n117
> 
> Could you tell me what are you seeing wrong? The dts-coding-style that
> you shared doesn't tell a specific location for bootph-* properties so
> using the generic reasoning.
> 
> "1. Most important properties start the node: compatible then bus addressing to
>     match unit address."
> 
> This is the least important property considering Linux and hence the
> reasoning was that it should come in the last. Also, j722s and am62p
> follow the same convention so it was taken from there only.
> 

Not sure if this is what he meant, but bootph-* comes under standard/common 
properties as per my understanding of the coding style. And status needs to be 
at the very end if it's there (in this case it's not but just mentioning).

> Regards,
> Manorit
> 
>>
>>
>>>>    	};
>>>>    };
>>>>
>>
>> -- 
>> Regards,
>> Nishanth Menon
>> Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

-- 
Thanking You
Neha Malcom Francis

Re: [PATCH v3 1/5] arm64: dts: ti: k3-j721s2*: Add bootph-* properties

[Manorit Chawdhry]

Hi Neha,

On 11:03-20240807, Neha Malcom Francis wrote:
> Hi Manorit
> 
> On 07/08/24 10:56, Manorit Chawdhry wrote:
> > Hi Nishanth,
> > 
> > On 10:07-20240806, Nishanth Menon wrote:
> > > On 09:43-20240806, Andrew Davis wrote:
> > > > On 7/30/24 4:53 AM, Manorit Chawdhry wrote:
> > > > > Adds bootph-* properties to the leaf nodes to enable U-boot to
> > > > > utilise them.
> > > > 
> > > > U-Boot? Let's try to pretend like this is a generic property and
> > > > just say "bootloader" :)
> > > > > @@ -445,6 +446,7 @@ flash@0 {
> > > > >    		cdns,tchsh-ns = <60>;
> > > > >    		cdns,tslch-ns = <60>;
> > > > >    		cdns,read-delay = <4>;
> > > > > +		bootph-all;
> > > 
> > > Here and elsewhere, follow:
> > > 	https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/dts-coding-style.rst#n117
> > 
> > Could you tell me what are you seeing wrong? The dts-coding-style that
> > you shared doesn't tell a specific location for bootph-* properties so
> > using the generic reasoning.
> > 
> > "1. Most important properties start the node: compatible then bus addressing to
> >     match unit address."
> > 
> > This is the least important property considering Linux and hence the
> > reasoning was that it should come in the last. Also, j722s and am62p
> > follow the same convention so it was taken from there only.
> > 
> 
> Not sure if this is what he meant, but bootph-* comes under standard/common
> properties as per my understanding of the coding style. And status needs to
> be at the very end if it's there (in this case it's not but just
> mentioning).

I see status property being at the top of many nodes so I don't think
it's even followed right now, with that reasoning, I don't think I can
use that point for ordering the dt nodes. If it's under common nodes
then also I think it's in the appropriate location considering that even
in those properties it is the least important and should be coming in
the last. If you see any problem with this node then please let me know
in the ordering.

Regards,
Manorit

> 
> > Regards,
> > Manorit
> > 
> > > 
> > > 
> > > > >    	};
> > > > >    };
> > > > > 
> > > 
> > > -- 
> > > Regards,
> > > Nishanth Menon
> > > Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D
> 
> -- 
> Thanking You
> Neha Malcom Francis

Re: [PATCH v3 1/5] arm64: dts: ti: k3-j721s2*: Add bootph-* properties

[Neha Malcom Francis]

On 07/08/24 11:12, Manorit Chawdhry wrote:
> Hi Neha,
> 
> On 11:03-20240807, Neha Malcom Francis wrote:
>> Hi Manorit
>>
>> On 07/08/24 10:56, Manorit Chawdhry wrote:
>>> Hi Nishanth,
>>>
>>> On 10:07-20240806, Nishanth Menon wrote:
>>>> On 09:43-20240806, Andrew Davis wrote:
>>>>> On 7/30/24 4:53 AM, Manorit Chawdhry wrote:
>>>>>> Adds bootph-* properties to the leaf nodes to enable U-boot to
>>>>>> utilise them.
>>>>>
>>>>> U-Boot? Let's try to pretend like this is a generic property and
>>>>> just say "bootloader" :)
>>>>>> @@ -445,6 +446,7 @@ flash@0 {
>>>>>>     		cdns,tchsh-ns = <60>;
>>>>>>     		cdns,tslch-ns = <60>;
>>>>>>     		cdns,read-delay = <4>;
>>>>>> +		bootph-all;
>>>>
>>>> Here and elsewhere, follow:
>>>> 	https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/dts-coding-style.rst#n117
>>>
>>> Could you tell me what are you seeing wrong? The dts-coding-style that
>>> you shared doesn't tell a specific location for bootph-* properties so
>>> using the generic reasoning.
>>>
>>> "1. Most important properties start the node: compatible then bus addressing to
>>>      match unit address."
>>>
>>> This is the least important property considering Linux and hence the
>>> reasoning was that it should come in the last. Also, j722s and am62p
>>> follow the same convention so it was taken from there only.
>>>
>>
>> Not sure if this is what he meant, but bootph-* comes under standard/common
>> properties as per my understanding of the coding style. And status needs to
>> be at the very end if it's there (in this case it's not but just
>> mentioning).
> 
> I see status property being at the top of many nodes so I don't think
> it's even followed right now, with that reasoning, I don't think I can
> use that point for ordering the dt nodes. If it's under common nodes
> then also I think it's in the appropriate location considering that even
> in those properties it is the least important and should be coming in
> the last. If you see any problem with this node then please let me know
> in the ordering.
> 

Aren't cdns,-* vendor specific properties?

Also I understand that most DTS aren't following majority of the rules, but 
considering it was a review comment I assume they want a check on what goes in 
at least so I've mentioned what I think they're asking for.

> Regards,
> Manorit
> 
>>
>>> Regards,
>>> Manorit
>>>
>>>>
>>>>
>>>>>>     	};
>>>>>>     };
>>>>>>
>>>>
>>>> -- 
>>>> Regards,
>>>> Nishanth Menon
>>>> Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D
>>
>> -- 
>> Thanking You
>> Neha Malcom Francis

-- 
Thanking You
Neha Malcom Francis

Re: [PATCH v3 1/5] arm64: dts: ti: k3-j721s2*: Add bootph-* properties

[Manorit Chawdhry]

Hi Neha,

On 11:12-20240807, Manorit Chawdhry wrote:
> Hi Neha,
> 
> On 11:03-20240807, Neha Malcom Francis wrote:
> > Hi Manorit
> > 
> > On 07/08/24 10:56, Manorit Chawdhry wrote:
> > > Hi Nishanth,
> > > 
> > > On 10:07-20240806, Nishanth Menon wrote:
> > > > On 09:43-20240806, Andrew Davis wrote:
> > > > > On 7/30/24 4:53 AM, Manorit Chawdhry wrote:
> > > > > > Adds bootph-* properties to the leaf nodes to enable U-boot to
> > > > > > utilise them.
> > > > > 
> > > > > U-Boot? Let's try to pretend like this is a generic property and
> > > > > just say "bootloader" :)
> > > > > > @@ -445,6 +446,7 @@ flash@0 {
> > > > > >    		cdns,tchsh-ns = <60>;
> > > > > >    		cdns,tslch-ns = <60>;
> > > > > >    		cdns,read-delay = <4>;
> > > > > > +		bootph-all;
> > > > 
> > > > Here and elsewhere, follow:
> > > > 	https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/dts-coding-style.rst#n117
> > > 
> > > Could you tell me what are you seeing wrong? The dts-coding-style that
> > > you shared doesn't tell a specific location for bootph-* properties so
> > > using the generic reasoning.
> > > 
> > > "1. Most important properties start the node: compatible then bus addressing to
> > >     match unit address."
> > > 
> > > This is the least important property considering Linux and hence the
> > > reasoning was that it should come in the last. Also, j722s and am62p
> > > follow the same convention so it was taken from there only.
> > > 
> > 
> > Not sure if this is what he meant, but bootph-* comes under standard/common
> > properties as per my understanding of the coding style. And status needs to
> > be at the very end if it's there (in this case it's not but just
> > mentioning).
> 
> I see status property being at the top of many nodes so I don't think
> it's even followed right now, with that reasoning, I don't think I can
> use that point for ordering the dt nodes. If it's under common nodes
> then also I think it's in the appropriate location considering that even
> in those properties it is the least important and should be coming in
> the last. If you see any problem with this node then please let me know
> in the ordering.

Maybe I missed, cdns would be vendor property I assume, let me get
Nishanth's ack as to that is what he wants and this is indeed under
common/standard nodes then would move it to the appropriate location. 

Though again, j722s and am62p don't seem to be following this
convention so not really sure what he means actually tbh.

Regards,
Manorit

> 
> Regards,
> Manorit
> 
> > 
> > > Regards,
> > > Manorit
> > > 
> > > > 
> > > > 
> > > > > >    	};
> > > > > >    };
> > > > > > 
> > > > 
> > > > -- 
> > > > Regards,
> > > > Nishanth Menon
> > > > Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D
> > 
> > -- 
> > Thanking You
> > Neha Malcom Francis

Re: [PATCH v3 1/5] arm64: dts: ti: k3-j721s2*: Add bootph-* properties

[Manorit Chawdhry]

Hi Neha,

On 11:18-20240807, Neha Malcom Francis wrote:
> 
> 
> On 07/08/24 11:12, Manorit Chawdhry wrote:
> > Hi Neha,
> > 
> > On 11:03-20240807, Neha Malcom Francis wrote:
> > > Hi Manorit
> > > 
> > > On 07/08/24 10:56, Manorit Chawdhry wrote:
> > > > Hi Nishanth,
> > > > 
> > > > On 10:07-20240806, Nishanth Menon wrote:
> > > > > On 09:43-20240806, Andrew Davis wrote:
> > > > > > On 7/30/24 4:53 AM, Manorit Chawdhry wrote:
> > > > > > > Adds bootph-* properties to the leaf nodes to enable U-boot to
> > > > > > > utilise them.
> > > > > > 
> > > > > > U-Boot? Let's try to pretend like this is a generic property and
> > > > > > just say "bootloader" :)
> > > > > > > @@ -445,6 +446,7 @@ flash@0 {
> > > > > > >     		cdns,tchsh-ns = <60>;
> > > > > > >     		cdns,tslch-ns = <60>;
> > > > > > >     		cdns,read-delay = <4>;
> > > > > > > +		bootph-all;
> > > > > 
> > > > > Here and elsewhere, follow:
> > > > > 	https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/dts-coding-style.rst#n117
> > > > 
> > > > Could you tell me what are you seeing wrong? The dts-coding-style that
> > > > you shared doesn't tell a specific location for bootph-* properties so
> > > > using the generic reasoning.
> > > > 
> > > > "1. Most important properties start the node: compatible then bus addressing to
> > > >      match unit address."
> > > > 
> > > > This is the least important property considering Linux and hence the
> > > > reasoning was that it should come in the last. Also, j722s and am62p
> > > > follow the same convention so it was taken from there only.
> > > > 
> > > 
> > > Not sure if this is what he meant, but bootph-* comes under standard/common
> > > properties as per my understanding of the coding style. And status needs to
> > > be at the very end if it's there (in this case it's not but just
> > > mentioning).
> > 
> > I see status property being at the top of many nodes so I don't think
> > it's even followed right now, with that reasoning, I don't think I can
> > use that point for ordering the dt nodes. If it's under common nodes
> > then also I think it's in the appropriate location considering that even
> > in those properties it is the least important and should be coming in
> > the last. If you see any problem with this node then please let me know
> > in the ordering.
> > 
> 
> Aren't cdns,-* vendor specific properties?
> 
> Also I understand that most DTS aren't following majority of the rules, but
> considering it was a review comment I assume they want a check on what goes
> in at least so I've mentioned what I think they're asking for.

I can fix it in places where it can be fixed ( I see few places where
order exist ) but where there is no order there this will be difficult
to handle. That'd require a total fix for ordering across all the places
and that will require a separate cleanup ig. So if people are okay, in
those places I'll be keeping bootph-* in the last like how it's followed
in right now.

Regards,
Manorit

> 
> > Regards,
> > Manorit
> > 
> > > 
> > > > Regards,
> > > > Manorit
> > > > 
> > > > > 
> > > > > 
> > > > > > >     	};
> > > > > > >     };
> > > > > > > 
> > > > > 
> > > > > -- 
> > > > > Regards,
> > > > > Nishanth Menon
> > > > > Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D
> > > 
> > > -- 
> > > Thanking You
> > > Neha Malcom Francis
> 
> -- 
> Thanking You
> Neha Malcom Francis

Re: [PATCH v3 5/5] arm64: dts: ti: k3-j7200*: Add bootph-* properties

[Kumar, Udit]

On 7/30/2024 3:23 PM, Manorit Chawdhry wrote:
> Adds bootph-* properties to the leaf nodes to enable U-boot to
> utilise them.
>
> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
> ---
>   .../arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 20 ++++++++++++++++++++
>   arch/arm64/boot/dts/ti/k3-j7200-main.dtsi            |  2 ++
>   arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi      | 10 ++++++++++
>   arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi          |  7 +++++++
>   4 files changed, 39 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> index 6593c5da82c0..ec522595fc83 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> [..]
>   
>   
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> index 9386bf3ef9f6..b95656942412 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> @@ -136,6 +136,7 @@ secure_proxy_main: mailbox@32c00000 {
>   			      <0x00 0x32800000 0x00 0x100000>;
>   			interrupt-names = "rx_011";
>   			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> +			bootph-all;
>   		};
>   
>   		hwspinlock: spinlock@30e00000 {
> @@ -1528,5 +1529,6 @@ main_esm: esm@700000 {
>   		compatible = "ti,j721e-esm";
>   		reg = <0x0 0x700000 0x0 0x1000>;
>   		ti,esm-pins = <656>, <657>;
> +		bootph-all;

Should be bootph-pre-ram

if you think otherwise then please update mcu_esm

>   	};
>   };
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
> index 5097d192c2b2..f8a5ad4737da 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
> @@ -21,16 +21,19 @@ dmsc: system-controller@44083000 {
>   		k3_pds: power-controller {
>   			compatible = "ti,sci-pm-domain";
>   			#power-domain-cells = <2>;
> +			bootph-all;
>   		};
>   
>   		k3_clks: clock-controller {
>   			compatible = "ti,k2g-sci-clk";
>   			#clock-cells = <2>;
> +			bootph-all;
>   		};
>   
>   		k3_reset: reset-controller {
>   			compatible = "ti,sci-reset";
>   			#reset-cells = <2>;
> +			bootph-all;
>   		};
>   	};
>   
> @@ -45,6 +48,7 @@ mcu_timer0: timer@40400000 {
>   		assigned-clock-parents = <&k3_clks 35 2>;
>   		power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
>   		ti,timer-pwm;
> +		bootph-pre-ram;

I see this node is marked as reserved

Do we plan to use in bootloader ?

>   	};
>   
>   	mcu_timer1: timer@40410000 {
> @@ -191,6 +195,7 @@ wkup_conf: bus@43000000 {
>   		chipid: chipid@14 {
>   			compatible = "ti,am654-chipid";
>   			reg = <0x14 0x4>;
> [...]
> @@ -389,6 +396,7 @@ secure_proxy_mcu: mailbox@2a480000 {
>   		 * firmware on non-MPU processors
>   		 */
>   		status = "disabled";
> +		bootph-pre-ram;
>   	};
>   
>   	mcu_cpsw: ethernet@46000000 {
> @@ -534,6 +542,7 @@ hbmc_mux: mux-controller@47000004 {
>   			reg = <0x00 0x47000004 0x00 0x4>;
>   			#mux-control-cells = <1>;
>   			mux-reg-masks = <0x0 0x2>; /* HBMC select */
> +			bootph-pre-ram;
>   		};
>   
>   		hbmc: hyperbus@47034000 {

I think you should consider to mark hbmc node for boot phase as well


> @@ -652,6 +661,7 @@ wkup_vtm0: temperature-sensor@42040000 {
>   		      <0x00 0x42050000 0x00 0x350>;
>   		power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
>   		#thermal-sensor-cells = <1>;
> +		bootph-pre-ram;
>   	};
>   
>   	mcu_esm: esm@40800000 {
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
> index 21fe194a5766..d78f86889bf9 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
> @@ -121,6 +121,7 @@ J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (B8) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
>   			J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
>   			J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
>   		>;
> [..]
>   			bucka2: buck2 {
> @@ -464,6 +470,7 @@ flash@0 {
>   		cdns,tchsh-ns = <60>;
>   		cdns,tslch-ns = <60>;
>   		cdns,read-delay = <4>;
> +		bootph-all;
>   
>   		partitions {
>   			compatible = "fixed-partitions";


Please consider, adding bootph in ospi0 node as well around 
"ospi.phypattern"


>

Re: [PATCH v3 4/5] arm64: dts: ti: k3-j721e*: Add bootph-* properties

[Kumar, Udit]

On 7/30/2024 3:23 PM, Manorit Chawdhry wrote:
> Adds bootph-* properties to the leaf nodes to enable U-boot to
> utilise them.
>
> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
> ---
>   .../arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 20 ++++++++++++++++++++
>   arch/arm64/boot/dts/ti/k3-j721e-main.dtsi            |  2 ++
>   arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi      |  9 +++++++++
>   arch/arm64/boot/dts/ti/k3-j721e-sk.dts               | 18 ++++++++++++++++++
>   arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi          |  5 +++++
>   5 files changed, 54 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
> index 8230d53cd696..ebc9ab3b6790 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
> @@ -193,6 +193,7 @@ J721E_IOPAD(0x1c0, PIN_OUTPUT, 1) /* (AA2) SPI0_CS0.UART0_RTSn */
>   			J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
>   			J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
>   		>;
> [...]
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> index 0da785be80ff..584badcb796d 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> @@ -226,6 +226,7 @@ secure_proxy_main: mailbox@32c00000 {
>   			      <0x00 0x32800000 0x00 0x100000>;
>   			interrupt-names = "rx_011";
>   			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> +			bootph-all;
>   		};
>   
>   		smmu0: iommu@36600000 {
> @@ -2854,5 +2855,6 @@ main_esm: esm@700000 {
>   		compatible = "ti,j721e-esm";
>   		reg = <0x0 0x700000 0x0 0x1000>;
>   		ti,esm-pins = <344>, <345>;
> +		bootph-all;

bootph-all or bootph-pre-ram. Please align with other esm nodes

>   	};
>   };
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
> index 6b6ef6a30614..6ecbf5ee8b78 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
> [..]
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
> index 89fbfb21e5d3..b63d48719090 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
> @@ -346,6 +346,7 @@ J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
>   			J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
>   			J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
>   		>;
> +		bootph-all;
>   	};
>   
>   	main_uart0_pins_default: main-uart0-default-pins {
> @@ -355,6 +356,7 @@ J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */
>   			J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
>   			J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
>   		>;
> +		bootph-all;
>   	};
>   
>   	main_uart1_pins_default: main-uart1-default-pins {
> @@ -390,12 +392,14 @@ main_usbss0_pins_default: main-usbss0-default-pins {
>   			J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
>   			J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
>   		>;
> +		bootph-all;
>   	};
>   
>   	main_usbss1_pins_default: main-usbss1-default-pins {
>   		pinctrl-single,pins = <
>   			J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
>   		>;
> +		bootph-all;
>   	};
>   
>   	main_csi_mux_sel_pins_default: main-csi-mux-sel-default-pins {
> @@ -594,6 +598,7 @@ J721E_WKUP_IOPAD(0x24, PIN_INPUT, 0) /* (B22) MCU_OSPI0_D6 */
>   			J721E_WKUP_IOPAD(0x28, PIN_INPUT, 0) /* (G21) MCU_OSPI0_D7 */
>   			J721E_WKUP_IOPAD(0x8, PIN_INPUT, 0) /* (D21) MCU_OSPI0_DQS */
>   		>;
> +		bootph-all;
>   	};
>   
>   	vdd_mmc1_en_pins_default: vdd-mmc1-en-default-pins {
> @@ -622,6 +627,7 @@ J721E_WKUP_IOPAD(0xf4, PIN_OUTPUT, 2)/* (D25) MCU_I3C0_SDA.MCU_UART0_RTSn */
>   			J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */
>   			J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0)/* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */
>   		>;
> +		bootph-pre-ram;


Please make consistency between pin mux and node.

Here I see pin mux is bootph-pre-ram and mcu_uart is bootph-all

>   	};
>   
>   	wkup_i2c0_pins_default: wkup-i2c0-default-pins {
> @@ -629,6 +635,7 @@ wkup_i2c0_pins_default: wkup-i2c0-default-pins {
>   			J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
>   			J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
>   		>;
> +		bootph-all;
>   	};
>   
>   	mcu_mcan0_pins_default: mcu-mcan0-default-pins {
> @@ -657,6 +664,7 @@ &wkup_uart0 {
>   	status = "reserved";
>   	pinctrl-names = "default";
>   	pinctrl-0 = <&wkup_uart0_pins_default>;
> +	bootph-all;
>   };
>   
>   &wkup_i2c0 {
> @@ -821,6 +829,7 @@ &mcu_uart0 {
>   	status = "okay";
>   	pinctrl-names = "default";
>   	pinctrl-0 = <&mcu_uart0_pins_default>;
> +	bootph-all;
>   };
>   
>   &main_uart0 {
> @@ -829,6 +838,7 @@ &main_uart0 {
>   	pinctrl-0 = <&main_uart0_pins_default>;
>   	/* Shared with ATF on this platform */
>   	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
> +	bootph-all;
>   };
>   
>   &main_uart1 {
> @@ -846,6 +856,7 @@ &main_sdhci1 {
>   	pinctrl-0 = <&main_mmc1_pins_default>;
>   	ti,driver-strength-ohm = <50>;
>   	disable-wp;
> +	bootph-all;
>   };
>   
>   &ospi0 {
> @@ -864,6 +875,7 @@ flash@0 {
>   		cdns,tchsh-ns = <60>;
>   		cdns,tslch-ns = <60>;
>   		cdns,read-delay = <4>;
> +		bootph-all;
>   
>   		partitions {
>   			compatible = "fixed-partitions";


Boot-loader may need to access ospi.phypattern, please add needed tags

> @@ -1003,6 +1015,7 @@ &wkup_gpio0 {
>   
> [...]
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
> index 5ba947771b84..86bfc5e21eed 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
> @@ -151,6 +151,7 @@ wkup_i2c0_pins_default: wkup-i2c0-default-pins {
>   			J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
>   			J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
>   		>;
> +		bootph-all;
>   	};
>   
>   	pmic_irq_pins_default: pmic-irq-default-pins {
> @@ -173,6 +174,7 @@ J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0)  /* MCU_OSPI0_D6 */
>   			J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0)  /* MCU_OSPI0_D7 */
>   			J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */
>   		>;
> +		bootph-all;
>   	};
>   
>   	mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-default-pins {
> @@ -192,6 +194,7 @@ J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1)  /* MCU_HYPERBUS0_DQ5 */
>   			J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1)  /* MCU_HYPERBUS0_DQ6 */
>   			J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1)  /* MCU_HYPERBUS0_DQ7 */
>   		>;
> +		bootph-all;
>   	};
>   };
>   
> @@ -378,6 +381,7 @@ flash@0 {
>   		cdns,tchsh-ns = <60>;
>   		cdns,tslch-ns = <60>;
>   		cdns,read-delay = <0>;
> +		bootph-all;
>   
>   		partitions {
>   			compatible = "fixed-partitions";


Same as above for "ospi.phypattern"

> @@ -440,6 +444,7 @@ &hbmc {
>   	flash@0,0 {
>   		compatible = "cypress,hyperflash", "cfi-flash";
>   		reg = <0x00 0x00 0x4000000>;
> +		bootph-all;
>   
>   		partitions {
>   			compatible = "fixed-partitions";
>

Re: [PATCH v3 5/5] arm64: dts: ti: k3-j7200*: Add bootph-* properties

[Manorit Chawdhry]

Hi Udit,

On 12:58-20240807, Kumar, Udit wrote:
> 
> On 7/30/2024 3:23 PM, Manorit Chawdhry wrote:
> > Adds bootph-* properties to the leaf nodes to enable U-boot to
> > utilise them.
> > 
> > Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
> > ---
> >   .../arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 20 ++++++++++++++++++++
> >   arch/arm64/boot/dts/ti/k3-j7200-main.dtsi            |  2 ++
> >   arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi      | 10 ++++++++++
> >   arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi          |  7 +++++++
> >   4 files changed, 39 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> > index 6593c5da82c0..ec522595fc83 100644
> > --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> > +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> > [..]
> > 
> > diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> > index 9386bf3ef9f6..b95656942412 100644
> > --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> > +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> > @@ -136,6 +136,7 @@ secure_proxy_main: mailbox@32c00000 {
> >   			      <0x00 0x32800000 0x00 0x100000>;
> >   			interrupt-names = "rx_011";
> >   			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> > +			bootph-all;
> >   		};
> >   		hwspinlock: spinlock@30e00000 {
> > @@ -1528,5 +1529,6 @@ main_esm: esm@700000 {
> >   		compatible = "ti,j721e-esm";
> >   		reg = <0x0 0x700000 0x0 0x1000>;
> >   		ti,esm-pins = <656>, <657>;
> > +		bootph-all;
> 
> Should be bootph-pre-ram
> 
> if you think otherwise then please update mcu_esm

Will update to bootph-pre-ram;

> 
[..]
> > @@ -45,6 +48,7 @@ mcu_timer0: timer@40400000 {
> >   		assigned-clock-parents = <&k3_clks 35 2>;
> >   		power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
> >   		ti,timer-pwm;
> > +		bootph-pre-ram;
> 
> I see this node is marked as reserved
> 
> Do we plan to use in bootloader ?

mcu_timer0 is used in R5 stage [0].

[0]: https://github.com/u-boot/u-boot/blob/master/arch/arm/dts/k3-j7200-r5-common-proc-board.dts#L56

> 
> >   	};
[..]
> >   		hbmc: hyperbus@47034000 {
> 
> I think you should consider to mark hbmc node for boot phase as well
> 

It's already marked in k3-j7200-som-p0.dtsi file with bootph-all inside
the flash node that describe it, is that okay?

> 
> > @@ -652,6 +661,7 @@ wkup_vtm0: temperature-sensor@42040000 {
> >   		      <0x00 0x42050000 0x00 0x350>;
> >   		power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
> >   		#thermal-sensor-cells = <1>;
> > +		bootph-pre-ram;
> >   	};
> >   	mcu_esm: esm@40800000 {
> > diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
> > index 21fe194a5766..d78f86889bf9 100644
> > --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
> > +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
> > @@ -121,6 +121,7 @@ J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (B8) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
> >   			J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
> >   			J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
> >   		>;
> > [..]
> >   			bucka2: buck2 {
> > @@ -464,6 +470,7 @@ flash@0 {
> >   		cdns,tchsh-ns = <60>;
> >   		cdns,tslch-ns = <60>;
> >   		cdns,read-delay = <4>;
> > +		bootph-all;
> >   		partitions {
> >   			compatible = "fixed-partitions";
> 
> 
> Please consider, adding bootph in ospi0 node as well around
> "ospi.phypattern"
> 

Okay sure, will move the bootph-all from flash@0 node to under
ospi.phypattern node as putting it in the child node should propagate
it.

Thanks for reviewing Udit!

Regards,
Manorit
> 
> > 

Re: [PATCH v3 2/5] arm64: dts: ti: k3-j784s4*: Remove bootph properties from parent nodes

[Kumar, Udit]

On 7/30/2024 3:23 PM, Manorit Chawdhry wrote:
> Removes bootph-* properties from parent nodes and aligns the bootph-* to
> other u-boot.dtsi
>
> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
> ---
>   arch/arm64/boot/dts/ti/k3-j784s4-evm.dts         | 9 +--------
>   arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 8 ++++----
>   2 files changed, 5 insertions(+), 12 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
> index ffa38f41679d..311844490027 100644
> --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
> @@ -461,7 +461,6 @@ J784S4_IOPAD(0x078, PIN_OUTPUT, 1) /* (AH37) MCAN2_RX.AUDIO_EXT_REFCLK1 */
>   };
>   

main_pmx0 has bootph-all in parent node, please consider to clean that 
as well


>   &wkup_pmx2 {
> -	bootph-all;
>   	wkup_uart0_pins_default: wkup-uart0-default-pins {
>   		bootph-all;
>   		pinctrl-single,pins = <
> @@ -577,7 +576,6 @@ J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 7)
>   };
>   
>   &wkup_pmx0 {
> -	bootph-all;
>   	mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
>   		bootph-all;
>   		pinctrl-single,pins = <
> @@ -597,7 +595,6 @@ J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */
>   };
>   
>   &wkup_pmx1 {
> -	bootph-all;
>   	mcu_fss0_ospi0_1_pins_default: mcu-fss0-ospi0-1-default-pins {
>   		bootph-all;
>   		pinctrl-single,pins = <
> @@ -668,6 +665,7 @@ bucka12: buck12 {
>   				regulator-max-microvolt = <1100000>;
>   				regulator-boot-on;
>   				regulator-always-on;
> +				bootph-pre-ram;
>   			};
>   
>   			bucka3: buck3 {
> @@ -769,18 +767,15 @@ &ufs_wrapper {
>   };
>   
>   &fss {
> -	bootph-all;
>   	status = "okay";
>   };
>   
>   &ospi0 {
> -	bootph-all;
>   	status = "okay";
>   	pinctrl-names = "default";
>   	pinctrl-0 = <&mcu_fss0_ospi0_pins_default>, <&mcu_fss0_ospi0_1_pins_default>;
>   
>   	flash@0 {
> -		bootph-all;
>   		compatible = "jedec,spi-nor";
>   		reg = <0x0>;
>   		spi-tx-bus-width = <8>;
> @@ -837,13 +832,11 @@ partition@3fc0000 {
>   };
>   
>   &ospi1 {
> -	bootph-all;
>   	status = "okay";
>   	pinctrl-names = "default";
>   	pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
>   
>   	flash@0 {
> -		bootph-all;
>   		compatible = "jedec,spi-nor";
>   		reg = <0x0>;
>   		spi-tx-bus-width = <1>;
> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
> index f3a6ed1c979d..3f89277e3c2c 100644
> --- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
> @@ -7,7 +7,6 @@
>   
>   &cbass_mcu_wakeup {
>   	sms: system-controller@44083000 {
> -		bootph-all;
>   		compatible = "ti,k2g-sci";
>   		ti,host-id = <12>;
>   
> @@ -39,7 +38,6 @@ k3_reset: reset-controller {
>   	};
>   
>   	wkup_conf: bus@43000000 {
> -		bootph-all;
>   		compatible = "simple-bus";
>   		#address-cells = <1>;
>   		#size-cells = <1>;
> @@ -65,6 +63,7 @@ secure_proxy_sa3: mailbox@43600000 {
>   		 * firmware on non-MPU processors
>   		 */
>   		status = "disabled";
> +		bootph-pre-ram;
>   	};
>   
>   	mcu_ram: sram@41c00000 {
> @@ -175,10 +174,10 @@ mcu_timer0: timer@40400000 {
>   		ti,timer-pwm;
>   		/* Non-MPU Firmware usage */
>   		status = "reserved";
> +		bootph-all;

both nodes mcu_timer0 and mcu_timer1 as marked as

/* Non-MPU Firmware usage */, Please provide some message added bootph in first and removed from second

>   	};
>   
>   	mcu_timer1: timer@40410000 {
> -		bootph-all;
>   		compatible = "ti,am654-timer";
>   		reg = <0x00 0x40410000 0x00 0x400>;
>   		interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>;
> @@ -458,7 +457,6 @@ mcu_spi2: spi@40320000 {
>   	};
> [..]

Re: [PATCH v3 4/5] arm64: dts: ti: k3-j721e*: Add bootph-* properties

[Manorit Chawdhry]

Hi Udit,

On 13:07-20240807, Kumar, Udit wrote:
> 
> >   	};
> >   	vdd_mmc1_en_pins_default: vdd-mmc1-en-default-pins {
> > @@ -622,6 +627,7 @@ J721E_WKUP_IOPAD(0xf4, PIN_OUTPUT, 2)/* (D25) MCU_I3C0_SDA.MCU_UART0_RTSn */
> >   			J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */
> >   			J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0)/* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */
> >   		>;
> > +		bootph-pre-ram;
> 
> 
> Please make consistency between pin mux and node.
> 
> Here I see pin mux is bootph-pre-ram and mcu_uart is bootph-all

Do we want it to be bootph-pre-ram or bootph-all?

Regards,
Manorit

Re: [PATCH v3 5/5] arm64: dts: ti: k3-j7200*: Add bootph-* properties

[Kumar, Udit]

On 8/7/2024 1:20 PM, Manorit Chawdhry wrote:
> Hi Udit,
>
> On 12:58-20240807, Kumar, Udit wrote:
>> On 7/30/2024 3:23 PM, Manorit Chawdhry wrote:
>>> [..]
>>> I think you should consider to mark hbmc node for boot phase as well
>>>
> It's already marked in k3-j7200-som-p0.dtsi file with bootph-all inside
> the flash node that describe it, is that okay?


yes

>
>>> @@ -652,6 +661,7 @@ wkup_vtm0: temperature-sensor@42040000 {
>>>    		      <0x00 0x42050000 0x00 0x350>;
>>>    		power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
>>>    		#thermal-sensor-cells = <1>;
>>> +		bootph-pre-ram;
>>>    	};
>>>    	mcu_esm: esm@40800000 {
>>> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
>>> index 21fe194a5766..d78f86889bf9 100644
>>> --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
>>> +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
>>> @@ -121,6 +121,7 @@ J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (B8) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
>>>    			J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
>>>    			J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
>>>    		>;
>>> [..]
>>>    			bucka2: buck2 {
>>> @@ -464,6 +470,7 @@ flash@0 {
>>>    		cdns,tchsh-ns = <60>;
>>>    		cdns,tslch-ns = <60>;
>>>    		cdns,read-delay = <4>;
>>> +		bootph-all;
>>>    		partitions {
>>>    			compatible = "fixed-partitions";
>>
>> Please consider, adding bootph in ospi0 node as well around
>> "ospi.phypattern"
>>
> Okay sure, will move the bootph-all from flash@0 node to under
> ospi.phypattern node as putting it in the child node should propagate
> it.
>
> Thanks for reviewing Udit!
>
> Regards,
> Manorit

Re: [PATCH v3 4/5] arm64: dts: ti: k3-j721e*: Add bootph-* properties

[Kumar, Udit]

Hi Manorit

On 8/7/2024 2:05 PM, Manorit Chawdhry wrote:
> Hi Udit,
>
> On 13:07-20240807, Kumar, Udit wrote:
>>>    	};
>>>    	vdd_mmc1_en_pins_default: vdd-mmc1-en-default-pins {
>>> @@ -622,6 +627,7 @@ J721E_WKUP_IOPAD(0xf4, PIN_OUTPUT, 2)/* (D25) MCU_I3C0_SDA.MCU_UART0_RTSn */
>>>    			J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */
>>>    			J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0)/* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */
>>>    		>;
>>> +		bootph-pre-ram;
>>
>> Please make consistency between pin mux and node.
>>
>> Here I see pin mux is bootph-pre-ram and mcu_uart is bootph-all
> Do we want it to be bootph-pre-ram or bootph-all?


My suggestion will be bootph-all

>
> Regards,
> Manorit

Re: [PATCH v3 4/5] arm64: dts: ti: k3-j721e*: Add bootph-* properties

[Neha Malcom Francis]

Hi Manorit,

On 30/07/24 15:23, Manorit Chawdhry wrote:
> Adds bootph-* properties to the leaf nodes to enable U-boot to
> utilise them.
> 
> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
> ---
>   .../arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 20 ++++++++++++++++++++
>   arch/arm64/boot/dts/ti/k3-j721e-main.dtsi            |  2 ++
>   arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi      |  9 +++++++++
>   arch/arm64/boot/dts/ti/k3-j721e-sk.dts               | 18 ++++++++++++++++++
>   arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi          |  5 +++++
>   5 files changed, 54 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
> index 8230d53cd696..ebc9ab3b6790 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
> @@ -193,6 +193,7 @@ J721E_IOPAD(0x1c0, PIN_OUTPUT, 1) /* (AA2) SPI0_CS0.UART0_RTSn */
>   			J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
>   			J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
>   		>;
> +		bootph-all;
>   	};
>   
>   	main_uart1_pins_default: main-uart1-default-pins {
> @@ -234,6 +235,7 @@ J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
>   			J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
>   			J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */
>   		>;
> +		bootph-all;
>   	};
>   
>   	vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins {
> @@ -247,6 +249,7 @@ main_usbss0_pins_default: main-usbss0-default-pins {
>   			J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
>   			J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
>   		>;
> +		bootph-all;
>   	};
>   
>   	main_usbss1_pins_default: main-usbss1-default-pins {
> @@ -272,6 +275,7 @@ main_i2c0_pins_default: main-i2c0-default-pins {
>   			J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
>   			J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
>   		>;
> +		bootph-all;
>   	};
>   
>   	main_i2c1_pins_default: main-i2c1-default-pins {
> @@ -342,6 +346,7 @@ wkup_uart0_pins_default: wkup-uart0-default-pins {
>   			J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */
>   			J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */
>   		>;
> +		bootph-all;
>   	};
>   
>   	mcu_uart0_pins_default: mcu-uart0-default-pins {
> @@ -351,6 +356,7 @@ J721E_WKUP_IOPAD(0xec, PIN_OUTPUT, 0) /* (J27) WKUP_GPIO0_15.MCU_UART0_RTSn */
>   			J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */
>   			J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0) /* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */
>   		>;
> +		bootph-all;
>   	};
>   
>   	sw11_button_pins_default: sw11-button-default-pins {
> @@ -370,6 +376,7 @@ J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23) MCU_OSPI1_D3 */
>   			J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */
>   			J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */
>   		>;
> +		bootph-all;
>   	};
>   
>   	mcu_cpsw_pins_default: mcu-cpsw-default-pins {
> @@ -427,6 +434,7 @@ wkup_gpio_pins_default: wkup-gpio-default-pins {
>   		pinctrl-single,pins = <
>   			J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_8 */
>   		>;
> +		bootph-all;
>   	};
>   };
>   
> @@ -435,12 +443,14 @@ &wkup_uart0 {
>   	status = "reserved";
>   	pinctrl-names = "default";
>   	pinctrl-0 = <&wkup_uart0_pins_default>;
> +	bootph-all;
>   };
>   
>   &mcu_uart0 {
>   	status = "okay";
>   	pinctrl-names = "default";
>   	pinctrl-0 = <&mcu_uart0_pins_default>;
> +	bootph-all;
>   };
>   
>   &main_uart0 {
> @@ -449,6 +459,7 @@ &main_uart0 {
>   	pinctrl-0 = <&main_uart0_pins_default>;
>   	/* Shared with ATF on this platform */
>   	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
> +	bootph-all;
>   };
>   
>   &main_uart1 {
> @@ -473,6 +484,7 @@ &wkup_gpio0 {
>   	status = "okay";
>   	pinctrl-names = "default";
>   	pinctrl-0 = <&wkup_gpio_pins_default>;
> +	bootph-all;
>   };
>   
>   &main_gpio0 {
> @@ -489,6 +501,7 @@ &main_sdhci0 {
>   	non-removable;
>   	ti,driver-strength-ohm = <50>;
>   	disable-wp;
> +	bootph-all;
>   };
>   
>   &main_sdhci1 {
> @@ -500,10 +513,12 @@ &main_sdhci1 {
>   	pinctrl-0 = <&main_mmc1_pins_default>;
>   	ti,driver-strength-ohm = <50>;
>   	disable-wp;
> +	bootph-all;
>   };
>   
>   &usb_serdes_mux {
>   	idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */
> +	bootph-all;
>   };
>   
>   &serdes_ln_ctrl {
> @@ -513,6 +528,7 @@ &serdes_ln_ctrl {
>   		      <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
>   		      <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
>   		      <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
> +	bootph-all;
>   };
>   
>   &serdes_wiz3 {
> @@ -534,6 +550,7 @@ &usbss0 {
>   	pinctrl-names = "default";
>   	pinctrl-0 = <&main_usbss0_pins_default>;
>   	ti,vbus-divider;
> +	bootph-all;
>   };
>   
>   &usb0 {
> @@ -541,6 +558,7 @@ &usb0 {
>   	maximum-speed = "super-speed";
>   	phys = <&serdes3_usb_link>;
>   	phy-names = "cdns3,usb3-phy";
> +	bootph-all;
>   };
>   
>   &usbss1 {
> @@ -569,6 +587,7 @@ flash@0 {
>   		cdns,tchsh-ns = <60>;
>   		cdns,tslch-ns = <60>;
>   		cdns,read-delay = <2>;
> +		bootph-all;
>   
>   		partitions {
>   			compatible = "fixed-partitions";
> @@ -650,6 +669,7 @@ exp2: gpio@22 {
>   		reg = <0x22>;
>   		gpio-controller;
>   		#gpio-cells = <2>;
> +		bootph-all;
>   
>   		p09-hog {
>   			/* P11 - MCASP/TRACE_MUX_S0 */
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> index 0da785be80ff..584badcb796d 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> @@ -226,6 +226,7 @@ secure_proxy_main: mailbox@32c00000 {
>   			      <0x00 0x32800000 0x00 0x100000>;
>   			interrupt-names = "rx_011";
>   			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> +			bootph-all;
>   		};
>   
>   		smmu0: iommu@36600000 {
> @@ -2854,5 +2855,6 @@ main_esm: esm@700000 {
>   		compatible = "ti,j721e-esm";
>   		reg = <0x0 0x700000 0x0 0x1000>;
>   		ti,esm-pins = <344>, <345>;
> +		bootph-all;
>   	};
>   };
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
> index 6b6ef6a30614..6ecbf5ee8b78 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
> @@ -21,16 +21,19 @@ dmsc: system-controller@44083000 {
>   		k3_pds: power-controller {
>   			compatible = "ti,sci-pm-domain";
>   			#power-domain-cells = <2>;
> +			bootph-all;
>   		};
>   
>   		k3_clks: clock-controller {
>   			compatible = "ti,k2g-sci-clk";
>   			#clock-cells = <2>;
> +			bootph-all;
>   		};
>   
>   		k3_reset: reset-controller {
>   			compatible = "ti,sci-reset";
>   			#reset-cells = <2>;
> +			bootph-all;
>   		};
>   	};
>   
> @@ -61,6 +64,7 @@ wkup_conf: bus@43000000 {
>   		chipid: chipid@14 {
>   			compatible = "ti,am654-chipid";
>   			reg = <0x14 0x4>;
> +			bootph-all;
>   		};
>   	};
>   
> @@ -115,6 +119,7 @@ mcu_timer0: timer@40400000 {
>   		ti,timer-pwm;
>   		/* Non-MPU Firmware usage */
>   		status = "reserved";
> +		bootph-pre-ram;
>   	};
>   
>   	mcu_timer1: timer@40410000 {
> @@ -475,6 +480,7 @@ mcu_ringacc: ringacc@2b800000 {
>   			ti,sci = <&dmsc>;
>   			ti,sci-dev-id = <235>;
>   			msi-parent = <&main_udmass_inta>;
> +			bootph-all;
>   		};
>   
>   		mcu_udmap: dma-controller@285c0000 {
> @@ -499,6 +505,7 @@ mcu_udmap: dma-controller@285c0000 {
>   			ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
>   						<0x0b>; /* RX_HCHAN */
>   			ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
> +			bootph-all;
>   		};
>   	};
>   
> @@ -515,6 +522,7 @@ secure_proxy_mcu: mailbox@2a480000 {
>   		 * firmware on non-MPU processors
>   		 */
>   		status = "disabled";
> +		bootph-pre-ram;
>   	};
>   
>   	mcu_cpsw: ethernet@46000000 {
> @@ -687,6 +695,7 @@ wkup_vtm0: temperature-sensor@42040000 {
>   		      <0x00 0x43000300 0x00 0x10>;
>   		power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
>   		#thermal-sensor-cells = <1>;
> +		bootph-pre-ram;
>   	};
>   
>   	mcu_esm: esm@40800000 {
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
> index 89fbfb21e5d3..b63d48719090 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
> @@ -346,6 +346,7 @@ J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
>   			J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
>   			J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
>   		>;
> +		bootph-all;
>   	};
>   
>   	main_uart0_pins_default: main-uart0-default-pins {
> @@ -355,6 +356,7 @@ J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */
>   			J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
>   			J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
>   		>;
> +		bootph-all;
>   	};
>   
>   	main_uart1_pins_default: main-uart1-default-pins {
> @@ -390,12 +392,14 @@ main_usbss0_pins_default: main-usbss0-default-pins {
>   			J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
>   			J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
>   		>;
> +		bootph-all;
>   	};
>   
>   	main_usbss1_pins_default: main-usbss1-default-pins {
>   		pinctrl-single,pins = <
>   			J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
>   		>;
> +		bootph-all;
>   	};
>   
>   	main_csi_mux_sel_pins_default: main-csi-mux-sel-default-pins {
> @@ -594,6 +598,7 @@ J721E_WKUP_IOPAD(0x24, PIN_INPUT, 0) /* (B22) MCU_OSPI0_D6 */
>   			J721E_WKUP_IOPAD(0x28, PIN_INPUT, 0) /* (G21) MCU_OSPI0_D7 */
>   			J721E_WKUP_IOPAD(0x8, PIN_INPUT, 0) /* (D21) MCU_OSPI0_DQS */
>   		>;
> +		bootph-all;
>   	};
>   
>   	vdd_mmc1_en_pins_default: vdd-mmc1-en-default-pins {
> @@ -622,6 +627,7 @@ J721E_WKUP_IOPAD(0xf4, PIN_OUTPUT, 2)/* (D25) MCU_I3C0_SDA.MCU_UART0_RTSn */
>   			J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */
>   			J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0)/* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */
>   		>;
> +		bootph-pre-ram;
>   	};
>   
>   	wkup_i2c0_pins_default: wkup-i2c0-default-pins {
> @@ -629,6 +635,7 @@ wkup_i2c0_pins_default: wkup-i2c0-default-pins {
>   			J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
>   			J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
>   		>;
> +		bootph-all;
>   	};
>   
>   	mcu_mcan0_pins_default: mcu-mcan0-default-pins {
> @@ -657,6 +664,7 @@ &wkup_uart0 {
>   	status = "reserved";
>   	pinctrl-names = "default";
>   	pinctrl-0 = <&wkup_uart0_pins_default>;
> +	bootph-all;
>   };
>   
>   &wkup_i2c0 {
> @@ -821,6 +829,7 @@ &mcu_uart0 {
>   	status = "okay";
>   	pinctrl-names = "default";
>   	pinctrl-0 = <&mcu_uart0_pins_default>;
> +	bootph-all;
>   };
>   
>   &main_uart0 {
> @@ -829,6 +838,7 @@ &main_uart0 {
>   	pinctrl-0 = <&main_uart0_pins_default>;
>   	/* Shared with ATF on this platform */
>   	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
> +	bootph-all;
>   };
>   
>   &main_uart1 {
> @@ -846,6 +856,7 @@ &main_sdhci1 {
>   	pinctrl-0 = <&main_mmc1_pins_default>;
>   	ti,driver-strength-ohm = <50>;
>   	disable-wp;
> +	bootph-all;
>   };
>   
>   &ospi0 {
> @@ -864,6 +875,7 @@ flash@0 {
>   		cdns,tchsh-ns = <60>;
>   		cdns,tslch-ns = <60>;
>   		cdns,read-delay = <4>;
> +		bootph-all;
>   
>   		partitions {
>   			compatible = "fixed-partitions";
> @@ -1003,6 +1015,7 @@ &wkup_gpio0 {
>   
>   &usb_serdes_mux {
>   	idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */
> +	bootph-all;
>   };
>   
>   &serdes_ln_ctrl {
> @@ -1012,6 +1025,7 @@ &serdes_ln_ctrl {
>   		      <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
>   		      <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
>   		      <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
> +	bootph-all;
>   };
>   
>   &serdes_wiz3 {
> @@ -1051,6 +1065,7 @@ &usbss0 {
>   	pinctrl-names = "default";
>   	pinctrl-0 = <&main_usbss0_pins_default>;
>   	ti,vbus-divider;
> +	bootph-all;
>   };
>   
>   &usb0 {
> @@ -1058,6 +1073,7 @@ &usb0 {
>   	maximum-speed = "super-speed";
>   	phys = <&serdes3_usb_link>;
>   	phy-names = "cdns3,usb3-phy";
> +	bootph-all;
>   };
>   
>   &serdes2 {
> @@ -1074,6 +1090,7 @@ &usbss1 {
>   	pinctrl-names = "default";
>   	pinctrl-0 = <&main_usbss1_pins_default>;
>   	ti,vbus-divider;
> +	bootph-all;
>   };
>   
>   &usb1 {
> @@ -1081,6 +1098,7 @@ &usb1 {
>   	maximum-speed = "super-speed";
>   	phys = <&serdes2_usb_link>;
>   	phy-names = "cdns3,usb3-phy";
> +	bootph-all;
>   };
>   
>   &mcu_cpsw {
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
> index 5ba947771b84..86bfc5e21eed 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
> @@ -151,6 +151,7 @@ wkup_i2c0_pins_default: wkup-i2c0-default-pins {
>   			J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
>   			J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
>   		>;
> +		bootph-all;
>   	};
>   
>   	pmic_irq_pins_default: pmic-irq-default-pins {
> @@ -173,6 +174,7 @@ J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0)  /* MCU_OSPI0_D6 */
>   			J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0)  /* MCU_OSPI0_D7 */
>   			J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */
>   		>;
> +		bootph-all;
>   	};
>   
>   	mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-default-pins {
> @@ -192,6 +194,7 @@ J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1)  /* MCU_HYPERBUS0_DQ5 */
>   			J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1)  /* MCU_HYPERBUS0_DQ6 */
>   			J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1)  /* MCU_HYPERBUS0_DQ7 */
>   		>;
> +		bootph-all;
>   	};
>   };
>   
> @@ -378,6 +381,7 @@ flash@0 {
>   		cdns,tchsh-ns = <60>;
>   		cdns,tslch-ns = <60>;
>   		cdns,read-delay = <0>;
> +		bootph-all;
>   
>   		partitions {
>   			compatible = "fixed-partitions";
> @@ -440,6 +444,7 @@ &hbmc {
>   	flash@0,0 {
>   		compatible = "cypress,hyperflash", "cfi-flash";
>   		reg = <0x00 0x00 0x4000000>;
> +		bootph-all;
>   
>   		partitions {
>   			compatible = "fixed-partitions";
> 

Sanity boot tested on J721E-SK after porting to U-Boot. Thanks for the patch, 
along with the reviews made by Udit (although one additional mention: IIRC, OSPI 
partitions are cosmetic for the U-Boot driver, but better to add bootph even if 
it's cosmetic in case the driver changes the next day), with those addressed:

Reviewed-by: Neha Malcom Francis <n-francis@ti.com>

-- 
Thanking You
Neha Malcom Francis

Re: [PATCH v3 4/5] arm64: dts: ti: k3-j721e*: Add bootph-* properties

[Manorit Chawdhry]

Hi Neha,

On 14:54-20240807, Neha Malcom Francis wrote:
> Hi Manorit,
> 
> On 30/07/24 15:23, Manorit Chawdhry wrote:
> > Adds bootph-* properties to the leaf nodes to enable U-boot to
> > utilise them.
> > 
> > Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
> > ---
> >   .../arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 20 ++++++++++++++++++++
> >   arch/arm64/boot/dts/ti/k3-j721e-main.dtsi            |  2 ++
> >   arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi      |  9 +++++++++
> >   arch/arm64/boot/dts/ti/k3-j721e-sk.dts               | 18 ++++++++++++++++++
> >   arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi          |  5 +++++
> >   5 files changed, 54 insertions(+)
> > 
[..]
> > @@ -440,6 +444,7 @@ &hbmc {
> >   	flash@0,0 {
> >   		compatible = "cypress,hyperflash", "cfi-flash";
> >   		reg = <0x00 0x00 0x4000000>;
> > +		bootph-all;
> >   		partitions {
> >   			compatible = "fixed-partitions";
> > 
> 
> Sanity boot tested on J721E-SK after porting to U-Boot. Thanks for the
> patch, along with the reviews made by Udit (although one additional mention:
> IIRC, OSPI partitions are cosmetic for the U-Boot driver, but better to add
> bootph even if it's cosmetic in case the driver changes the next day), with
> those addressed:
> 
> Reviewed-by: Neha Malcom Francis <n-francis@ti.com>

Would be following up on those comments. Thanks for reviewing and
testing!

Regards,
Manorit

> 
> -- 
> Thanking You
> Neha Malcom Francis

Re: [PATCH v3 1/5] arm64: dts: ti: k3-j721s2*: Add bootph-* properties

[Nishanth Menon]

On 10:56-20240807, Manorit Chawdhry wrote:
> Hi Nishanth,
> 
> On 10:07-20240806, Nishanth Menon wrote:
> > On 09:43-20240806, Andrew Davis wrote:
> > > On 7/30/24 4:53 AM, Manorit Chawdhry wrote:
> > > > Adds bootph-* properties to the leaf nodes to enable U-boot to
> > > > utilise them.
> > > 
> > > U-Boot? Let's try to pretend like this is a generic property and
> > > just say "bootloader" :)
> > > > @@ -445,6 +446,7 @@ flash@0 {
> > > >   		cdns,tchsh-ns = <60>;
> > > >   		cdns,tslch-ns = <60>;
> > > >   		cdns,read-delay = <4>;
> > > > +		bootph-all;
> > 
> > Here and elsewhere, follow:
> > 	https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/dts-coding-style.rst#n117
> 
> Could you tell me what are you seeing wrong? The dts-coding-style that
> you shared doesn't tell a specific location for bootph-* properties so
> using the generic reasoning.

it falls under standard properties

> 
> "1. Most important properties start the node: compatible then bus addressing to
>    match unit address."
> 
> This is the least important property considering Linux and hence the
> reasoning was that it should come in the last. Also, j722s and am62p
> follow the same convention so it was taken from there only.

follow the order - bootph-all is before the vendor properties

-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

Re: [PATCH v3 1/5] arm64: dts: ti: k3-j721s2*: Add bootph-* properties

[Nishanth Menon]

On 12:06-20240807, Manorit Chawdhry wrote:
[...]

> > > > 
> > > > Not sure if this is what he meant, but bootph-* comes under standard/common
> > > > properties as per my understanding of the coding style. And status needs to
> > > > be at the very end if it's there (in this case it's not but just
> > > > mentioning).
> > > 
> > > I see status property being at the top of many nodes so I don't think
> > > it's even followed right now, with that reasoning, I don't think I can
> > > use that point for ordering the dt nodes. If it's under common nodes
> > > then also I think it's in the appropriate location considering that even
> > > in those properties it is the least important and should be coming in
> > > the last. If you see any problem with this node then please let me know
> > > in the ordering.
> > > 
> > 
> > Aren't cdns,-* vendor specific properties?
> > 
> > Also I understand that most DTS aren't following majority of the rules, but
> > considering it was a review comment I assume they want a check on what goes
> > in at least so I've mentioned what I think they're asking for.
> 
> I can fix it in places where it can be fixed ( I see few places where
> order exist ) but where there is no order there this will be difficult
> to handle. That'd require a total fix for ordering across all the places
> and that will require a separate cleanup ig. So if people are okay, in
> those places I'll be keeping bootph-* in the last like how it's followed
> in right now.

Just make sure that when new properties or nodes are introduced, follow
the convention. For new SoCs, this is mandatory for new nodes that are
introduced (not when renaming file etc).

-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

Re: [PATCH v3 5/5] arm64: dts: ti: k3-j7200*: Add bootph-* properties

[Limaye, Aniket]

Hi Manorit,

On 7/30/2024 3:23 PM, Manorit Chawdhry wrote:
> Adds bootph-* properties to the leaf nodes to enable U-boot to
> utilise them.
> 
> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
> ---
>   .../arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 20 ++++++++++++++++++++
>   arch/arm64/boot/dts/ti/k3-j7200-main.dtsi            |  2 ++
>   arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi      | 10 ++++++++++
>   arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi          |  7 +++++++
>   4 files changed, 39 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> index 6593c5da82c0..ec522595fc83 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> @@ -129,6 +129,7 @@ J721E_WKUP_IOPAD(0x94, PIN_OUTPUT, 0) /* (E21) MCU_UART0_RTSn */
>   			J721E_WKUP_IOPAD(0x8c, PIN_INPUT, 0) /* (D20) MCU_UART0_RXD */
>   			J721E_WKUP_IOPAD(0x88, PIN_OUTPUT, 0) /* (D19) MCU_UART0_TXD */
>   		>;
> +		bootph-all;
>   	};
>   
>   	wkup_uart0_pins_default: wkup-uart0-default-pins {
> @@ -136,6 +137,7 @@ wkup_uart0_pins_default: wkup-uart0-default-pins {
>   			J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */
>   			J721E_WKUP_IOPAD(0x4c, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */
>   		>;
> +		bootph-all;
>   	};
>   
>   	mcu_cpsw_pins_default: mcu-cpsw-default-pins {
> @@ -159,6 +161,7 @@ wkup_gpio_pins_default: wkup-gpio-default-pins {
>   		pinctrl-single,pins = <
>   			J721E_WKUP_IOPAD(0x70, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */
>   		>;
> +		bootph-all;
>   	};
>   
>   	mcu_mdio_pins_default: mcu-mdio1-default-pins {
> @@ -204,6 +207,7 @@ J721E_IOPAD(0xb4, PIN_OUTPUT, 0) /* (T17) UART0_TXD */
>   			J721E_IOPAD(0xc0, PIN_INPUT, 2) /* (W3) SPI0_CS0.UART0_CTSn */
>   			J721E_IOPAD(0xc4, PIN_OUTPUT, 2) /* (U5) SPI0_CS1.UART0_RTSn */
>   		>;
> +		bootph-all;
>   	};
>   
>   	main_uart1_pins_default: main-uart1-default-pins {
> @@ -238,6 +242,7 @@ J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */
>   			J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */
>   			J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */
>   		>;
> +		bootph-all;
>   	};
>   
>   	vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
> @@ -259,6 +264,7 @@ main_usbss0_pins_default: main-usbss0-default-pins {
>   		pinctrl-single,pins = <
>   			J721E_IOPAD(0x04, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
>   		>;
> +		bootph-all;
>   	};
>   };
>   
> @@ -267,12 +273,14 @@ &wkup_uart0 {
>   	status = "reserved";
>   	pinctrl-names = "default";
>   	pinctrl-0 = <&wkup_uart0_pins_default>;
> +	bootph-all;
>   };
>   
>   &mcu_uart0 {
>   	status = "okay";
>   	pinctrl-names = "default";
>   	pinctrl-0 = <&mcu_uart0_pins_default>;
> +	bootph-all;
>   };
>   
>   &main_uart0 {
> @@ -281,6 +289,7 @@ &main_uart0 {
>   	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
>   	pinctrl-names = "default";
>   	pinctrl-0 = <&main_uart0_pins_default>;
> +	bootph-all;
>   };
>   
>   &main_uart1 {
> @@ -310,6 +319,7 @@ &wkup_gpio0 {
>   	status = "okay";
>   	pinctrl-names = "default";
>   	pinctrl-0 = <&wkup_gpio_pins_default>;
> +	bootph-all;
>   };
>   
>   &mcu_cpsw {
> @@ -341,6 +351,7 @@ exp1: gpio@20 {
>   		reg = <0x20>;
>   		gpio-controller;
>   		#gpio-cells = <2>;
> +		bootph-all;
>   	};
>   
>   	exp2: gpio@22 {
> @@ -348,6 +359,7 @@ exp2: gpio@22 {
>   		reg = <0x22>;
>   		gpio-controller;
>   		#gpio-cells = <2>;
> +		bootph-all;
>   	};
>   };
>   
> @@ -381,6 +393,7 @@ &main_sdhci0 {
>   	non-removable;
>   	ti,driver-strength-ohm = <50>;
>   	disable-wp;
> +	bootph-all;
>   };
>   
>   &main_sdhci1 {
> @@ -392,15 +405,18 @@ &main_sdhci1 {
>   	vqmmc-supply = <&vdd_sd_dv>;
>   	ti,driver-strength-ohm = <50>;
>   	disable-wp;
> +	bootph-all;
>   };
>   
>   &serdes_ln_ctrl {
>   	idle-states = <J7200_SERDES0_LANE0_PCIE1_LANE0>, <J7200_SERDES0_LANE1_PCIE1_LANE1>,
>   		      <J7200_SERDES0_LANE2_QSGMII_LANE1>, <J7200_SERDES0_LANE3_IP4_UNUSED>;
> +	bootph-all;
>   };
>   
>   &usb_serdes_mux {
>   	idle-states = <1>; /* USB0 to SERDES lane 3 */
> +	bootph-all;
>   };
>   
>   &usbss0 {
> @@ -408,11 +424,13 @@ &usbss0 {
>   	pinctrl-0 = <&main_usbss0_pins_default>;
>   	ti,vbus-divider;
>   	ti,usb2-only;
> +	bootph-all;
>   };
>   
>   &usb0 {
>   	dr_mode = "otg";
>   	maximum-speed = "high-speed";
> +	bootph-all;
>   };
>   
>   &tscadc0 {
> @@ -432,6 +450,7 @@ serdes0_pcie_link: phy@0 {
>   		#phy-cells = <0>;
>   		cdns,phy-type = <PHY_TYPE_PCIE>;
>   		resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
> +		bootph-all;
>   	};
>   
>   	serdes0_qsgmii_link: phy@1 {
> @@ -440,6 +459,7 @@ serdes0_qsgmii_link: phy@1 {
>   		#phy-cells = <0>;
>   		cdns,phy-type = <PHY_TYPE_QSGMII>;
>   		resets = <&serdes_wiz0 3>;
> +		bootph-all;
>   	};
>   };
>   
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> index 9386bf3ef9f6..b95656942412 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> @@ -136,6 +136,7 @@ secure_proxy_main: mailbox@32c00000 {
>   			      <0x00 0x32800000 0x00 0x100000>;
>   			interrupt-names = "rx_011";
>   			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> +			bootph-all;
>   		};
>   
>   		hwspinlock: spinlock@30e00000 {
> @@ -1528,5 +1529,6 @@ main_esm: esm@700000 {
>   		compatible = "ti,j721e-esm";
>   		reg = <0x0 0x700000 0x0 0x1000>;
>   		ti,esm-pins = <656>, <657>;
> +		bootph-all;
>   	};
>   };
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
> index 5097d192c2b2..f8a5ad4737da 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
> @@ -21,16 +21,19 @@ dmsc: system-controller@44083000 {

Referring to the thread from v2 [0], I see that you have removed the 
bootph-all from the parent dmsc node. With current patch j7200-evm fails 
to boot (Stuck somewhere in tispl or right after that) as discussed in 
the same thread [0].

I have boot tested this patch (SD boot) and the device boots with an 
additional bootph-all at dmsc node.

I assume the removal was done intentionally, meaning we intend to fix 
the bug in u-boot or carry the one extra bootph-all there. If NOT, 
please add the same in the parent dmsc node here as well.

So taking care of the above,

Reviewed-by: Aniket Limaye <a-limaye@ti.com>

[0]: https://lore.kernel.org/all/20240709084857.nf7c57mi6miajeau@uda0497581/

>   		k3_pds: power-controller {
>   			compatible = "ti,sci-pm-domain";
>   			#power-domain-cells = <2>;
> +			bootph-all;
>   		};
>   
>   		k3_clks: clock-controller {
>   			compatible = "ti,k2g-sci-clk";
>   			#clock-cells = <2>;
> +			bootph-all;
>   		};
>   
>   		k3_reset: reset-controller {
>   			compatible = "ti,sci-reset";
>   			#reset-cells = <2>;
> +			bootph-all;
>   		};
>   	};
>   
> @@ -45,6 +48,7 @@ mcu_timer0: timer@40400000 {
>   		assigned-clock-parents = <&k3_clks 35 2>;
>   		power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
>   		ti,timer-pwm;
> +		bootph-pre-ram;
>   	};
>   
>   	mcu_timer1: timer@40410000 {
> @@ -191,6 +195,7 @@ wkup_conf: bus@43000000 {
>   		chipid: chipid@14 {
>   			compatible = "ti,am654-chipid";
>   			reg = <0x14 0x4>;
> +			bootph-all;
>   		};
>   	};
>   
> @@ -349,6 +354,7 @@ mcu_ringacc: ringacc@2b800000 {
>   			ti,sci = <&dmsc>;
>   			ti,sci-dev-id = <235>;
>   			msi-parent = <&main_udmass_inta>;
> +			bootph-all;
>   		};
>   
>   		mcu_udmap: dma-controller@285c0000 {
> @@ -373,6 +379,7 @@ mcu_udmap: dma-controller@285c0000 {
>   			ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
>   						<0x0b>; /* RX_HCHAN */
>   			ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
> +			bootph-all;
>   		};
>   	};
>   
> @@ -389,6 +396,7 @@ secure_proxy_mcu: mailbox@2a480000 {
>   		 * firmware on non-MPU processors
>   		 */
>   		status = "disabled";
> +		bootph-pre-ram;
>   	};
>   
>   	mcu_cpsw: ethernet@46000000 {
> @@ -534,6 +542,7 @@ hbmc_mux: mux-controller@47000004 {
>   			reg = <0x00 0x47000004 0x00 0x4>;
>   			#mux-control-cells = <1>;
>   			mux-reg-masks = <0x0 0x2>; /* HBMC select */
> +			bootph-pre-ram;
>   		};
>   
>   		hbmc: hyperbus@47034000 {
> @@ -652,6 +661,7 @@ wkup_vtm0: temperature-sensor@42040000 {
>   		      <0x00 0x42050000 0x00 0x350>;
>   		power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
>   		#thermal-sensor-cells = <1>;
> +		bootph-pre-ram;
>   	};
>   
>   	mcu_esm: esm@40800000 {
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
> index 21fe194a5766..d78f86889bf9 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
> @@ -121,6 +121,7 @@ J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (B8) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
>   			J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
>   			J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
>   		>;
> +		bootph-all;
>   	};
>   
>   	mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
> @@ -137,6 +138,7 @@ J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0)  /* MCU_OSPI0_D6 */
>   			J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0)  /* MCU_OSPI0_D7 */
>   			J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0)  /* MCU_OSPI0_DQS */
>   		>;
> +		bootph-all;
>   	};
>   };
>   
> @@ -146,6 +148,7 @@ wkup_i2c0_pins_default: wkup-i2c0-default-pins {
>   			J721E_WKUP_IOPAD(0x98, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */
>   			J721E_WKUP_IOPAD(0x9c, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */
>   		>;
> +		bootph-all;
>   	};
>   };
>   
> @@ -163,6 +166,7 @@ main_i2c0_pins_default: main-i2c0-default-pins {
>   			J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
>   			J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
>   		>;
> +		bootph-all;
>   	};
>   
>   	main_mcan0_pins_default: main-mcan0-default-pins {
> @@ -186,6 +190,7 @@ &hbmc {
>   	flash@0,0 {
>   		compatible = "cypress,hyperflash", "cfi-flash";
>   		reg = <0x00 0x00 0x4000000>;
> +		bootph-all;
>   
>   		partitions {
>   			compatible = "fixed-partitions";
> @@ -330,6 +335,7 @@ bucka1: buck1 {
>   				regulator-max-microvolt = <1800000>;
>   				regulator-boot-on;
>   				regulator-always-on;
> +				bootph-all;
>   			};
>   
>   			bucka2: buck2 {
> @@ -464,6 +470,7 @@ flash@0 {
>   		cdns,tchsh-ns = <60>;
>   		cdns,tslch-ns = <60>;
>   		cdns,read-delay = <4>;
> +		bootph-all;
>   
>   		partitions {
>   			compatible = "fixed-partitions";
> 

Re: [PATCH v3 5/5] arm64: dts: ti: k3-j7200*: Add bootph-* properties

[Manorit Chawdhry]

Hi Aniket,

On 20:07-20240807, Limaye, Aniket wrote:
> Hi Manorit,
> 
> On 7/30/2024 3:23 PM, Manorit Chawdhry wrote:
> > Adds bootph-* properties to the leaf nodes to enable U-boot to
> > utilise them.
> > 
> > Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
> > ---
> >   .../arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 20 ++++++++++++++++++++
> >   arch/arm64/boot/dts/ti/k3-j7200-main.dtsi            |  2 ++
> >   arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi      | 10 ++++++++++
> >   arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi          |  7 +++++++
> >   4 files changed, 39 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
> > index 5097d192c2b2..f8a5ad4737da 100644
> > --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
> > +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
> > @@ -21,16 +21,19 @@ dmsc: system-controller@44083000 {
> 
> Referring to the thread from v2 [0], I see that you have removed the
> bootph-all from the parent dmsc node. With current patch j7200-evm fails to
> boot (Stuck somewhere in tispl or right after that) as discussed in the same
> thread [0].
> 
> I have boot tested this patch (SD boot) and the device boots with an
> additional bootph-all at dmsc node.
> 
> I assume the removal was done intentionally, meaning we intend to fix the
> bug in u-boot or carry the one extra bootph-all there. If NOT, please add
> the same in the parent dmsc node here as well.

Yes, the removal was intentional and there is a fix that can be done in
U-boot for this so we'll take that up there.

Thanks for reviewing!

Regards,
Manorit

> 
> So taking care of the above,
> 
> Reviewed-by: Aniket Limaye <a-limaye@ti.com>
> 
> [0]: https://lore.kernel.org/all/20240709084857.nf7c57mi6miajeau@uda0497581/